2 * This file configures the internal USB PHY in OMAP4430. Used
3 * with TWL6030 transceiver and MUSB on OMAP4430.
5 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * Author: Hema HK <hemahk@ti.com>
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/types.h>
25 #include <linux/delay.h>
26 #include <linux/clk.h>
28 #include <linux/err.h>
29 #include <linux/usb.h>
31 #include <plat/hardware.h>
36 /* OMAP control module register for UTMI PHY */
37 #define CONTROL_DEV_CONF 0x300
40 #define USBOTGHS_CONTROL 0x33c
43 #define VBUSVALID BIT(2)
44 #define SESSEND BIT(3)
47 static struct clk
*phyclk
, *clk48m
, *clk32k
;
48 static void __iomem
*ctrl_base
;
49 static int usbotghs_control
;
51 int omap4430_phy_init(struct device
*dev
)
53 ctrl_base
= ioremap(OMAP443X_SCM_BASE
, SZ_1K
);
55 pr_err("control module ioremap failed\n");
58 /* Power down the phy */
59 __raw_writel(PHY_PD
, ctrl_base
+ CONTROL_DEV_CONF
);
66 phyclk
= clk_get(dev
, "ocp2scp_usb_phy_ick");
68 dev_err(dev
, "cannot clk_get ocp2scp_usb_phy_ick\n");
70 return PTR_ERR(phyclk
);
73 clk48m
= clk_get(dev
, "ocp2scp_usb_phy_phy_48m");
75 dev_err(dev
, "cannot clk_get ocp2scp_usb_phy_phy_48m\n");
78 return PTR_ERR(clk48m
);
81 clk32k
= clk_get(dev
, "usb_phy_cm_clk32k");
83 dev_err(dev
, "cannot clk_get usb_phy_cm_clk32k\n");
87 return PTR_ERR(clk32k
);
92 int omap4430_phy_set_clk(struct device
*dev
, int on
)
97 /* Enable the phy clocks */
103 /* Disable the phy clocks */
112 int omap4430_phy_power(struct device
*dev
, int ID
, int on
)
116 /* enable VBUS valid, IDDIG groung */
117 __raw_writel(AVALID
| VBUSVALID
, ctrl_base
+
121 * Enable VBUS Valid, AValid and IDDIG
124 __raw_writel(IDDIG
| AVALID
| VBUSVALID
,
125 ctrl_base
+ USBOTGHS_CONTROL
);
127 /* Enable session END and IDIG to high impedance. */
128 __raw_writel(SESSEND
| IDDIG
, ctrl_base
+
134 int omap4430_phy_suspend(struct device
*dev
, int suspend
)
137 /* Disable the clocks */
138 omap4430_phy_set_clk(dev
, 0);
139 /* Power down the phy */
140 __raw_writel(PHY_PD
, ctrl_base
+ CONTROL_DEV_CONF
);
142 /* save the context */
143 usbotghs_control
= __raw_readl(ctrl_base
+ USBOTGHS_CONTROL
);
145 /* Enable the internel phy clcoks */
146 omap4430_phy_set_clk(dev
, 1);
147 /* power on the phy */
148 if (__raw_readl(ctrl_base
+ CONTROL_DEV_CONF
) & PHY_PD
) {
149 __raw_writel(~PHY_PD
, ctrl_base
+ CONTROL_DEV_CONF
);
153 /* restore the context */
154 __raw_writel(usbotghs_control
, ctrl_base
+ USBOTGHS_CONTROL
);
160 int omap4430_phy_exit(struct device
*dev
)
174 void am35x_musb_reset(void)
178 /* Reset the musb interface */
179 regval
= omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET
);
181 regval
|= AM35XX_USBOTGSS_SW_RST
;
182 omap_ctrl_writel(regval
, AM35XX_CONTROL_IP_SW_RESET
);
184 regval
&= ~AM35XX_USBOTGSS_SW_RST
;
185 omap_ctrl_writel(regval
, AM35XX_CONTROL_IP_SW_RESET
);
187 regval
= omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET
);
190 void am35x_musb_phy_power(u8 on
)
192 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
197 * Start the on-chip PHY and its PLL.
199 devconf2
= omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2
);
201 devconf2
&= ~(CONF2_RESET
| CONF2_PHYPWRDN
| CONF2_OTGPWRDN
);
202 devconf2
|= CONF2_PHY_PLLON
;
204 omap_ctrl_writel(devconf2
, AM35XX_CONTROL_DEVCONF2
);
206 pr_info(KERN_INFO
"Waiting for PHY clock good...\n");
207 while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2
)
211 if (time_after(jiffies
, timeout
)) {
212 pr_err(KERN_ERR
"musb PHY clock good timed out\n");
218 * Power down the on-chip PHY.
220 devconf2
= omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2
);
222 devconf2
&= ~CONF2_PHY_PLLON
;
223 devconf2
|= CONF2_PHYPWRDN
| CONF2_OTGPWRDN
;
224 omap_ctrl_writel(devconf2
, AM35XX_CONTROL_DEVCONF2
);
228 void am35x_musb_clear_irq(void)
232 regval
= omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR
);
233 regval
|= AM35XX_USBOTGSS_INT_CLR
;
234 omap_ctrl_writel(regval
, AM35XX_CONTROL_LVL_INTR_CLEAR
);
235 regval
= omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR
);
238 void am35x_set_mode(u8 musb_mode
)
240 u32 devconf2
= omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2
);
242 devconf2
&= ~CONF2_OTGMODE
;
244 case MUSB_HOST
: /* Force VBUS valid, ID = 0 */
245 devconf2
|= CONF2_FORCE_HOST
;
247 case MUSB_PERIPHERAL
: /* Force VBUS valid, ID = 1 */
248 devconf2
|= CONF2_FORCE_DEVICE
;
250 case MUSB_OTG
: /* Don't override the VBUS/ID comparators */
251 devconf2
|= CONF2_NO_OVERRIDE
;
254 pr_info(KERN_INFO
"Unsupported mode %u\n", musb_mode
);
257 omap_ctrl_writel(devconf2
, AM35XX_CONTROL_DEVCONF2
);
260 void ti81xx_musb_phy_power(u8 on
)
262 void __iomem
*scm_base
= NULL
;
265 scm_base
= ioremap(TI81XX_SCM_BASE
, SZ_2K
);
267 pr_err("system control module ioremap failed\n");
271 usbphycfg
= __raw_readl(scm_base
+ USBCTRL0
);
274 if (cpu_is_ti816x()) {
275 usbphycfg
|= TI816X_USBPHY0_NORMAL_MODE
;
276 usbphycfg
&= ~TI816X_USBPHY_REFCLK_OSC
;
277 } else if (cpu_is_ti814x()) {
278 usbphycfg
&= ~(USBPHY_CM_PWRDN
| USBPHY_OTG_PWRDN
279 | USBPHY_DPINPUT
| USBPHY_DMINPUT
);
280 usbphycfg
|= (USBPHY_OTGVDET_EN
| USBPHY_OTGSESSEND_EN
281 | USBPHY_DPOPBUFCTL
| USBPHY_DMOPBUFCTL
);
285 usbphycfg
&= ~TI816X_USBPHY0_NORMAL_MODE
;
286 else if (cpu_is_ti814x())
287 usbphycfg
|= USBPHY_CM_PWRDN
| USBPHY_OTG_PWRDN
;
290 __raw_writel(usbphycfg
, scm_base
+ USBCTRL0
);