2 * OMAP2 Power Management Routines
4 * Copyright (C) 2005 Texas Instruments, Inc.
5 * Copyright (C) 2006-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * Amit Kucheria <amit.kucheria@nokia.com>
12 * Igor Stoppa <igor.stoppa@nokia.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/suspend.h>
22 #include <linux/sched.h>
23 #include <linux/proc_fs.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysfs.h>
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/clk.h>
30 #include <linux/irq.h>
31 #include <linux/time.h>
32 #include <linux/gpio.h>
34 #include <asm/mach/time.h>
35 #include <asm/mach/irq.h>
36 #include <asm/mach-types.h>
38 #include <mach/irqs.h>
39 #include <plat/clock.h>
40 #include <plat/sram.h>
42 #include <plat/board.h>
45 #include "prm2xxx_3xxx.h"
46 #include "prm-regbits-24xx.h"
47 #include "cm2xxx_3xxx.h"
48 #include "cm-regbits-24xx.h"
53 #include "powerdomain.h"
54 #include "clockdomain.h"
57 static suspend_state_t suspend_state
= PM_SUSPEND_ON
;
58 static inline bool is_suspending(void)
60 return (suspend_state
!= PM_SUSPEND_ON
);
63 static inline bool is_suspending(void)
69 static void (*omap2_sram_idle
)(void);
70 static void (*omap2_sram_suspend
)(u32 dllctrl
, void __iomem
*sdrc_dlla_ctrl
,
71 void __iomem
*sdrc_power
);
73 static struct powerdomain
*mpu_pwrdm
, *core_pwrdm
;
74 static struct clockdomain
*dsp_clkdm
, *mpu_clkdm
, *wkup_clkdm
, *gfx_clkdm
;
76 static struct clk
*osc_ck
, *emul_ck
;
78 static int omap2_fclks_active(void)
82 f1
= omap2_cm_read_mod_reg(CORE_MOD
, CM_FCLKEN1
);
83 f2
= omap2_cm_read_mod_reg(CORE_MOD
, OMAP24XX_CM_FCLKEN2
);
85 return (f1
| f2
) ? 1 : 0;
88 static void omap2_enter_full_retention(void)
92 /* There is 1 reference hold for all children of the oscillator
93 * clock, the following will remove it. If no one else uses the
94 * oscillator itself it will be disabled if/when we enter retention
99 /* Clear old wake-up events */
100 /* REVISIT: These write to reserved bits? */
101 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD
, PM_WKST1
);
102 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD
, OMAP24XX_PM_WKST2
);
103 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD
, PM_WKST
);
106 * Set MPU powerdomain's next power state to RETENTION;
107 * preserve logic state during retention
109 pwrdm_set_logic_retst(mpu_pwrdm
, PWRDM_POWER_RET
);
110 pwrdm_set_next_pwrst(mpu_pwrdm
, PWRDM_POWER_RET
);
112 /* Workaround to kill USB */
113 l
= omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0
) | OMAP24XX_USBSTANDBYCTRL
;
114 omap_ctrl_writel(l
, OMAP2_CONTROL_DEVCONF0
);
116 omap2_gpio_prepare_for_idle(0);
118 /* One last check for pending IRQs to avoid extra latency due
119 * to sleeping unnecessarily. */
120 if (omap_irq_pending())
123 /* Jump to SRAM suspend code */
124 omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL
),
125 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL
),
126 OMAP_SDRC_REGADDR(SDRC_POWER
));
129 omap2_gpio_resume_after_idle();
133 /* clear CORE wake-up events */
134 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD
, PM_WKST1
);
135 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD
, OMAP24XX_PM_WKST2
);
137 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
138 omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD
, PM_WKST
);
140 /* MPU domain wake events */
141 l
= omap2_prm_read_mod_reg(OCP_MOD
, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
);
143 omap2_prm_write_mod_reg(0x01, OCP_MOD
,
144 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
);
146 omap2_prm_write_mod_reg(0x20, OCP_MOD
,
147 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
);
149 /* Mask future PRCM-to-MPU interrupts */
150 omap2_prm_write_mod_reg(0x0, OCP_MOD
, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
);
153 static int omap2_i2c_active(void)
157 l
= omap2_cm_read_mod_reg(CORE_MOD
, CM_FCLKEN1
);
158 return l
& (OMAP2420_EN_I2C2_MASK
| OMAP2420_EN_I2C1_MASK
);
161 static int sti_console_enabled
;
163 static int omap2_allow_mpu_retention(void)
167 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
168 l
= omap2_cm_read_mod_reg(CORE_MOD
, CM_FCLKEN1
);
169 if (l
& (OMAP2420_EN_MMC_MASK
| OMAP24XX_EN_UART2_MASK
|
170 OMAP24XX_EN_UART1_MASK
| OMAP24XX_EN_MCSPI2_MASK
|
171 OMAP24XX_EN_MCSPI1_MASK
| OMAP24XX_EN_DSS1_MASK
))
173 /* Check for UART3. */
174 l
= omap2_cm_read_mod_reg(CORE_MOD
, OMAP24XX_CM_FCLKEN2
);
175 if (l
& OMAP24XX_EN_UART3_MASK
)
177 if (sti_console_enabled
)
183 static void omap2_enter_mpu_retention(void)
187 /* Putting MPU into the WFI state while a transfer is active
188 * seems to cause the I2C block to timeout. Why? Good question. */
189 if (omap2_i2c_active())
192 /* The peripherals seem not to be able to wake up the MPU when
193 * it is in retention mode. */
194 if (omap2_allow_mpu_retention()) {
195 /* REVISIT: These write to reserved bits? */
196 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD
, PM_WKST1
);
197 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD
, OMAP24XX_PM_WKST2
);
198 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD
, PM_WKST
);
200 /* Try to enter MPU retention */
201 omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT
) |
202 OMAP_LOGICRETSTATE_MASK
,
203 MPU_MOD
, OMAP2_PM_PWSTCTRL
);
205 /* Block MPU retention */
207 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK
, MPU_MOD
,
215 static int omap2_can_sleep(void)
217 if (omap2_fclks_active())
219 if (osc_ck
->usecount
> 1)
221 if (omap_dma_running())
227 static void omap2_pm_idle(void)
231 if (!omap2_can_sleep()) {
232 if (omap_irq_pending())
234 omap2_enter_mpu_retention();
238 if (omap_irq_pending())
241 omap2_enter_full_retention();
247 #ifdef CONFIG_SUSPEND
248 static int omap2_pm_begin(suspend_state_t state
)
251 suspend_state
= state
;
255 static int omap2_pm_suspend(void)
259 wken_wkup
= omap2_prm_read_mod_reg(WKUP_MOD
, PM_WKEN
);
260 wken_wkup
&= ~OMAP24XX_EN_GPT1_MASK
;
261 omap2_prm_write_mod_reg(wken_wkup
, WKUP_MOD
, PM_WKEN
);
264 mir1
= omap_readl(0x480fe0a4);
265 omap_writel(1 << 5, 0x480fe0ac);
267 omap2_enter_full_retention();
269 omap_writel(mir1
, 0x480fe0a4);
270 omap2_prm_write_mod_reg(wken_wkup
, WKUP_MOD
, PM_WKEN
);
275 static int omap2_pm_enter(suspend_state_t state
)
280 case PM_SUSPEND_STANDBY
:
282 ret
= omap2_pm_suspend();
291 static void omap2_pm_end(void)
293 suspend_state
= PM_SUSPEND_ON
;
297 static const struct platform_suspend_ops omap_pm_ops
= {
298 .begin
= omap2_pm_begin
,
299 .enter
= omap2_pm_enter
,
301 .valid
= suspend_valid_only_mem
,
304 static const struct platform_suspend_ops __initdata omap_pm_ops
;
305 #endif /* CONFIG_SUSPEND */
307 /* XXX This function should be shareable between OMAP2xxx and OMAP3 */
308 static int __init
clkdms_setup(struct clockdomain
*clkdm
, void *unused
)
310 if (clkdm
->flags
& CLKDM_CAN_ENABLE_AUTO
)
311 clkdm_allow_idle(clkdm
);
312 else if (clkdm
->flags
& CLKDM_CAN_FORCE_SLEEP
&&
313 atomic_read(&clkdm
->usecount
) == 0)
318 static void __init
prcm_setup_regs(void)
320 int i
, num_mem_banks
;
321 struct powerdomain
*pwrdm
;
325 * XXX This should be handled by hwmod code or PRCM init code
327 omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK
, OCP_MOD
,
328 OMAP2_PRCM_SYSCONFIG_OFFSET
);
331 * Set CORE powerdomain memory banks to retain their contents
334 num_mem_banks
= pwrdm_get_mem_bank_count(core_pwrdm
);
335 for (i
= 0; i
< num_mem_banks
; i
++)
336 pwrdm_set_mem_retst(core_pwrdm
, i
, PWRDM_POWER_RET
);
338 /* Set CORE powerdomain's next power state to RETENTION */
339 pwrdm_set_next_pwrst(core_pwrdm
, PWRDM_POWER_RET
);
342 * Set MPU powerdomain's next power state to RETENTION;
343 * preserve logic state during retention
345 pwrdm_set_logic_retst(mpu_pwrdm
, PWRDM_POWER_RET
);
346 pwrdm_set_next_pwrst(mpu_pwrdm
, PWRDM_POWER_RET
);
348 /* Force-power down DSP, GFX powerdomains */
350 pwrdm
= clkdm_get_pwrdm(dsp_clkdm
);
351 pwrdm_set_next_pwrst(pwrdm
, PWRDM_POWER_OFF
);
352 clkdm_sleep(dsp_clkdm
);
354 pwrdm
= clkdm_get_pwrdm(gfx_clkdm
);
355 pwrdm_set_next_pwrst(pwrdm
, PWRDM_POWER_OFF
);
356 clkdm_sleep(gfx_clkdm
);
358 /* Enable hardware-supervised idle for all clkdms */
359 clkdm_for_each(clkdms_setup
, NULL
);
360 clkdm_add_wkdep(mpu_clkdm
, wkup_clkdm
);
362 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
364 omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT
, OMAP24XX_GR_MOD
,
365 OMAP2_PRCM_CLKSSETUP_OFFSET
);
367 /* Configure automatic voltage transition */
368 omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT
, OMAP24XX_GR_MOD
,
369 OMAP2_PRCM_VOLTSETUP_OFFSET
);
370 omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK
|
371 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT
) |
372 OMAP24XX_MEMRETCTRL_MASK
|
373 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT
) |
374 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT
),
375 OMAP24XX_GR_MOD
, OMAP2_PRCM_VOLTCTRL_OFFSET
);
377 /* Enable wake-up events */
378 omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK
| OMAP24XX_EN_GPT1_MASK
,
382 static int __init
omap2_pm_init(void)
386 if (!cpu_is_omap24xx())
389 printk(KERN_INFO
"Power Management for OMAP2 initializing\n");
390 l
= omap2_prm_read_mod_reg(OCP_MOD
, OMAP2_PRCM_REVISION_OFFSET
);
391 printk(KERN_INFO
"PRCM revision %d.%d\n", (l
>> 4) & 0x0f, l
& 0x0f);
393 /* Look up important powerdomains */
395 mpu_pwrdm
= pwrdm_lookup("mpu_pwrdm");
397 pr_err("PM: mpu_pwrdm not found\n");
399 core_pwrdm
= pwrdm_lookup("core_pwrdm");
401 pr_err("PM: core_pwrdm not found\n");
403 /* Look up important clockdomains */
405 mpu_clkdm
= clkdm_lookup("mpu_clkdm");
407 pr_err("PM: mpu_clkdm not found\n");
409 wkup_clkdm
= clkdm_lookup("wkup_clkdm");
411 pr_err("PM: wkup_clkdm not found\n");
413 dsp_clkdm
= clkdm_lookup("dsp_clkdm");
415 pr_err("PM: dsp_clkdm not found\n");
417 gfx_clkdm
= clkdm_lookup("gfx_clkdm");
419 pr_err("PM: gfx_clkdm not found\n");
422 osc_ck
= clk_get(NULL
, "osc_ck");
423 if (IS_ERR(osc_ck
)) {
424 printk(KERN_ERR
"could not get osc_ck\n");
428 if (cpu_is_omap242x()) {
429 emul_ck
= clk_get(NULL
, "emul_ck");
430 if (IS_ERR(emul_ck
)) {
431 printk(KERN_ERR
"could not get emul_ck\n");
439 /* Hack to prevent MPU retention when STI console is enabled. */
441 const struct omap_sti_console_config
*sti
;
443 sti
= omap_get_config(OMAP_TAG_STI_CONSOLE
,
444 struct omap_sti_console_config
);
445 if (sti
!= NULL
&& sti
->enable
)
446 sti_console_enabled
= 1;
450 * We copy the assembler sleep/wakeup routines to SRAM.
451 * These routines need to be in SRAM as that's the only
452 * memory the MPU can see when it wakes up.
454 if (cpu_is_omap24xx()) {
455 omap2_sram_idle
= omap_sram_push(omap24xx_idle_loop_suspend
,
456 omap24xx_idle_loop_suspend_sz
);
458 omap2_sram_suspend
= omap_sram_push(omap24xx_cpu_suspend
,
459 omap24xx_cpu_suspend_sz
);
462 suspend_set_ops(&omap_pm_ops
);
463 arm_pm_idle
= omap2_pm_idle
;
468 late_initcall(omap2_pm_init
);