2 * OMAP2 Power Management Routines
4 * Copyright (C) 2005 Texas Instruments, Inc.
5 * Copyright (C) 2006-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * Amit Kucheria <amit.kucheria@nokia.com>
12 * Igor Stoppa <igor.stoppa@nokia.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/suspend.h>
22 #include <linux/sched.h>
23 #include <linux/proc_fs.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysfs.h>
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/clk-provider.h>
29 #include <linux/irq.h>
30 #include <linux/time.h>
31 #include <linux/gpio.h>
32 #include <linux/platform_data/gpio-omap.h>
34 #include <asm/fncpy.h>
36 #include <asm/mach/time.h>
37 #include <asm/mach/irq.h>
38 #include <asm/mach-types.h>
39 #include <asm/system_misc.h>
41 #include <linux/omap-dma.h>
47 #include "prm-regbits-24xx.h"
49 #include "cm-regbits-24xx.h"
54 #include "powerdomain.h"
55 #include "clockdomain.h"
57 static void (*omap2_sram_suspend
)(u32 dllctrl
, void __iomem
*sdrc_dlla_ctrl
,
58 void __iomem
*sdrc_power
);
60 static struct powerdomain
*mpu_pwrdm
, *core_pwrdm
;
61 static struct clockdomain
*dsp_clkdm
, *mpu_clkdm
, *wkup_clkdm
, *gfx_clkdm
;
63 static struct clk
*osc_ck
, *emul_ck
;
65 static int omap2_enter_full_retention(void)
69 /* There is 1 reference hold for all children of the oscillator
70 * clock, the following will remove it. If no one else uses the
71 * oscillator itself it will be disabled if/when we enter retention
76 /* Clear old wake-up events */
77 /* REVISIT: These write to reserved bits? */
78 omap2xxx_prm_clear_mod_irqs(CORE_MOD
, PM_WKST1
, ~0);
79 omap2xxx_prm_clear_mod_irqs(CORE_MOD
, OMAP24XX_PM_WKST2
, ~0);
80 omap2xxx_prm_clear_mod_irqs(WKUP_MOD
, PM_WKST
, ~0);
82 pwrdm_set_next_pwrst(core_pwrdm
, PWRDM_POWER_RET
);
83 pwrdm_set_next_pwrst(mpu_pwrdm
, PWRDM_POWER_RET
);
85 /* Workaround to kill USB */
86 l
= omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0
) | OMAP24XX_USBSTANDBYCTRL
;
87 omap_ctrl_writel(l
, OMAP2_CONTROL_DEVCONF0
);
89 omap2_gpio_prepare_for_idle(0);
91 /* One last check for pending IRQs to avoid extra latency due
92 * to sleeping unnecessarily. */
93 if (omap_irq_pending())
96 /* Jump to SRAM suspend code */
97 omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL
),
98 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL
),
99 OMAP_SDRC_REGADDR(SDRC_POWER
));
102 omap2_gpio_resume_after_idle();
106 /* clear CORE wake-up events */
107 omap2xxx_prm_clear_mod_irqs(CORE_MOD
, PM_WKST1
, ~0);
108 omap2xxx_prm_clear_mod_irqs(CORE_MOD
, OMAP24XX_PM_WKST2
, ~0);
110 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
111 omap2xxx_prm_clear_mod_irqs(WKUP_MOD
, PM_WKST
, 0x4 | 0x1);
113 /* MPU domain wake events */
114 omap2xxx_prm_clear_mod_irqs(OCP_MOD
, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
,
117 omap2xxx_prm_clear_mod_irqs(OCP_MOD
, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
,
120 pwrdm_set_next_pwrst(mpu_pwrdm
, PWRDM_POWER_ON
);
121 pwrdm_set_next_pwrst(core_pwrdm
, PWRDM_POWER_ON
);
126 static int sti_console_enabled
;
128 static int omap2_allow_mpu_retention(void)
130 if (!omap2xxx_cm_mpu_retention_allowed())
132 if (sti_console_enabled
)
138 static void omap2_enter_mpu_retention(void)
142 /* The peripherals seem not to be able to wake up the MPU when
143 * it is in retention mode. */
144 if (omap2_allow_mpu_retention()) {
145 /* REVISIT: These write to reserved bits? */
146 omap2xxx_prm_clear_mod_irqs(CORE_MOD
, PM_WKST1
, ~0);
147 omap2xxx_prm_clear_mod_irqs(CORE_MOD
, OMAP24XX_PM_WKST2
, ~0);
148 omap2xxx_prm_clear_mod_irqs(WKUP_MOD
, PM_WKST
, ~0);
150 /* Try to enter MPU retention */
151 pwrdm_set_next_pwrst(mpu_pwrdm
, PWRDM_POWER_RET
);
154 /* Block MPU retention */
155 pwrdm_set_next_pwrst(mpu_pwrdm
, PWRDM_POWER_ON
);
159 asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero
) : "memory", "cc");
161 pwrdm_set_next_pwrst(mpu_pwrdm
, PWRDM_POWER_ON
);
164 static int omap2_can_sleep(void)
166 if (omap2xxx_cm_fclks_active())
168 if (__clk_is_enabled(osc_ck
))
170 if (omap_dma_running())
176 static void omap2_pm_idle(void)
178 if (!omap2_can_sleep()) {
179 if (omap_irq_pending())
181 omap2_enter_mpu_retention();
185 if (omap_irq_pending())
188 omap2_enter_full_retention();
191 static void __init
prcm_setup_regs(void)
193 int i
, num_mem_banks
;
194 struct powerdomain
*pwrdm
;
198 * XXX This should be handled by hwmod code or PRCM init code
200 omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK
, OCP_MOD
,
201 OMAP2_PRCM_SYSCONFIG_OFFSET
);
204 * Set CORE powerdomain memory banks to retain their contents
207 num_mem_banks
= pwrdm_get_mem_bank_count(core_pwrdm
);
208 for (i
= 0; i
< num_mem_banks
; i
++)
209 pwrdm_set_mem_retst(core_pwrdm
, i
, PWRDM_POWER_RET
);
211 pwrdm_set_logic_retst(core_pwrdm
, PWRDM_POWER_RET
);
213 pwrdm_set_logic_retst(mpu_pwrdm
, PWRDM_POWER_RET
);
215 /* Force-power down DSP, GFX powerdomains */
217 pwrdm
= clkdm_get_pwrdm(dsp_clkdm
);
218 pwrdm_set_next_pwrst(pwrdm
, PWRDM_POWER_OFF
);
220 pwrdm
= clkdm_get_pwrdm(gfx_clkdm
);
221 pwrdm_set_next_pwrst(pwrdm
, PWRDM_POWER_OFF
);
223 /* Enable hardware-supervised idle for all clkdms */
224 clkdm_for_each(omap_pm_clkdms_setup
, NULL
);
225 clkdm_add_wkdep(mpu_clkdm
, wkup_clkdm
);
227 omap_common_suspend_init(omap2_enter_full_retention
);
229 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
231 omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT
, OMAP24XX_GR_MOD
,
232 OMAP2_PRCM_CLKSSETUP_OFFSET
);
234 /* Configure automatic voltage transition */
235 omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT
, OMAP24XX_GR_MOD
,
236 OMAP2_PRCM_VOLTSETUP_OFFSET
);
237 omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK
|
238 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT
) |
239 OMAP24XX_MEMRETCTRL_MASK
|
240 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT
) |
241 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT
),
242 OMAP24XX_GR_MOD
, OMAP2_PRCM_VOLTCTRL_OFFSET
);
244 /* Enable wake-up events */
245 omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK
| OMAP24XX_EN_GPT1_MASK
,
248 /* Enable SYS_CLKEN control when all domains idle */
249 omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK
, OMAP24XX_GR_MOD
,
250 OMAP2_PRCM_CLKSRC_CTRL_OFFSET
);
253 int __init
omap2_pm_init(void)
257 printk(KERN_INFO
"Power Management for OMAP2 initializing\n");
258 l
= omap2_prm_read_mod_reg(OCP_MOD
, OMAP2_PRCM_REVISION_OFFSET
);
259 printk(KERN_INFO
"PRCM revision %d.%d\n", (l
>> 4) & 0x0f, l
& 0x0f);
261 /* Look up important powerdomains */
263 mpu_pwrdm
= pwrdm_lookup("mpu_pwrdm");
265 pr_err("PM: mpu_pwrdm not found\n");
267 core_pwrdm
= pwrdm_lookup("core_pwrdm");
269 pr_err("PM: core_pwrdm not found\n");
271 /* Look up important clockdomains */
273 mpu_clkdm
= clkdm_lookup("mpu_clkdm");
275 pr_err("PM: mpu_clkdm not found\n");
277 wkup_clkdm
= clkdm_lookup("wkup_clkdm");
279 pr_err("PM: wkup_clkdm not found\n");
281 dsp_clkdm
= clkdm_lookup("dsp_clkdm");
283 pr_err("PM: dsp_clkdm not found\n");
285 gfx_clkdm
= clkdm_lookup("gfx_clkdm");
287 pr_err("PM: gfx_clkdm not found\n");
290 osc_ck
= clk_get(NULL
, "osc_ck");
291 if (IS_ERR(osc_ck
)) {
292 printk(KERN_ERR
"could not get osc_ck\n");
296 if (cpu_is_omap242x()) {
297 emul_ck
= clk_get(NULL
, "emul_ck");
298 if (IS_ERR(emul_ck
)) {
299 printk(KERN_ERR
"could not get emul_ck\n");
308 * We copy the assembler sleep/wakeup routines to SRAM.
309 * These routines need to be in SRAM as that's the only
310 * memory the MPU can see when it wakes up after the entire
313 omap2_sram_suspend
= omap_sram_push(omap24xx_cpu_suspend
,
314 omap24xx_cpu_suspend_sz
);
316 arm_pm_idle
= omap2_pm_idle
;