2 * OMAP2 Power Management Routines
4 * Copyright (C) 2005 Texas Instruments, Inc.
5 * Copyright (C) 2006-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * Amit Kucheria <amit.kucheria@nokia.com>
12 * Igor Stoppa <igor.stoppa@nokia.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/suspend.h>
22 #include <linux/sched.h>
23 #include <linux/proc_fs.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysfs.h>
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/clk.h>
30 #include <linux/irq.h>
31 #include <linux/time.h>
32 #include <linux/gpio.h>
34 #include <asm/mach/time.h>
35 #include <asm/mach/irq.h>
36 #include <asm/mach-types.h>
38 #include <mach/irqs.h>
39 #include <plat/clock.h>
40 #include <plat/sram.h>
41 #include <plat/control.h>
44 #include <plat/board.h>
47 #include "prm-regbits-24xx.h"
49 #include "cm-regbits-24xx.h"
53 #include <plat/powerdomain.h>
54 #include <plat/clockdomain.h>
56 static void (*omap2_sram_idle
)(void);
57 static void (*omap2_sram_suspend
)(u32 dllctrl
, void __iomem
*sdrc_dlla_ctrl
,
58 void __iomem
*sdrc_power
);
60 static struct powerdomain
*mpu_pwrdm
, *core_pwrdm
;
61 static struct clockdomain
*dsp_clkdm
, *mpu_clkdm
, *wkup_clkdm
, *gfx_clkdm
;
63 static struct clk
*osc_ck
, *emul_ck
;
65 static int omap2_fclks_active(void)
69 f1
= cm_read_mod_reg(CORE_MOD
, CM_FCLKEN1
);
70 f2
= cm_read_mod_reg(CORE_MOD
, OMAP24XX_CM_FCLKEN2
);
72 /* Ignore UART clocks. These are handled by UART core (serial.c) */
73 f1
&= ~(OMAP24XX_EN_UART1_MASK
| OMAP24XX_EN_UART2_MASK
);
74 f2
&= ~OMAP24XX_EN_UART3_MASK
;
81 static void omap2_enter_full_retention(void)
84 struct timespec ts_preidle
, ts_postidle
, ts_idle
;
86 /* There is 1 reference hold for all children of the oscillator
87 * clock, the following will remove it. If no one else uses the
88 * oscillator itself it will be disabled if/when we enter retention
93 /* Clear old wake-up events */
94 /* REVISIT: These write to reserved bits? */
95 prm_write_mod_reg(0xffffffff, CORE_MOD
, PM_WKST1
);
96 prm_write_mod_reg(0xffffffff, CORE_MOD
, OMAP24XX_PM_WKST2
);
97 prm_write_mod_reg(0xffffffff, WKUP_MOD
, PM_WKST
);
100 * Set MPU powerdomain's next power state to RETENTION;
101 * preserve logic state during retention
103 pwrdm_set_logic_retst(mpu_pwrdm
, PWRDM_POWER_RET
);
104 pwrdm_set_next_pwrst(mpu_pwrdm
, PWRDM_POWER_RET
);
106 /* Workaround to kill USB */
107 l
= omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0
) | OMAP24XX_USBSTANDBYCTRL
;
108 omap_ctrl_writel(l
, OMAP2_CONTROL_DEVCONF0
);
110 omap2_gpio_prepare_for_idle(PWRDM_POWER_RET
);
112 if (omap2_pm_debug
) {
113 omap2_pm_dump(0, 0, 0);
114 getnstimeofday(&ts_preidle
);
117 /* One last check for pending IRQs to avoid extra latency due
118 * to sleeping unnecessarily. */
119 if (omap_irq_pending())
122 omap_uart_prepare_idle(0);
123 omap_uart_prepare_idle(1);
124 omap_uart_prepare_idle(2);
126 /* Jump to SRAM suspend code */
127 omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL
),
128 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL
),
129 OMAP_SDRC_REGADDR(SDRC_POWER
));
131 omap_uart_resume_idle(2);
132 omap_uart_resume_idle(1);
133 omap_uart_resume_idle(0);
136 if (omap2_pm_debug
) {
137 unsigned long long tmp
;
139 getnstimeofday(&ts_postidle
);
140 ts_idle
= timespec_sub(ts_postidle
, ts_preidle
);
141 tmp
= timespec_to_ns(&ts_idle
) * NSEC_PER_USEC
;
142 omap2_pm_dump(0, 1, tmp
);
144 omap2_gpio_resume_after_idle();
148 /* clear CORE wake-up events */
149 prm_write_mod_reg(0xffffffff, CORE_MOD
, PM_WKST1
);
150 prm_write_mod_reg(0xffffffff, CORE_MOD
, OMAP24XX_PM_WKST2
);
152 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
153 prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD
, PM_WKST
);
155 /* MPU domain wake events */
156 l
= prm_read_mod_reg(OCP_MOD
, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
);
158 prm_write_mod_reg(0x01, OCP_MOD
,
159 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
);
161 prm_write_mod_reg(0x20, OCP_MOD
,
162 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
);
164 /* Mask future PRCM-to-MPU interrupts */
165 prm_write_mod_reg(0x0, OCP_MOD
, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
);
168 static int omap2_i2c_active(void)
172 l
= cm_read_mod_reg(CORE_MOD
, CM_FCLKEN1
);
173 return l
& (OMAP2420_EN_I2C2_MASK
| OMAP2420_EN_I2C1_MASK
);
176 static int sti_console_enabled
;
178 static int omap2_allow_mpu_retention(void)
182 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
183 l
= cm_read_mod_reg(CORE_MOD
, CM_FCLKEN1
);
184 if (l
& (OMAP2420_EN_MMC_MASK
| OMAP24XX_EN_UART2_MASK
|
185 OMAP24XX_EN_UART1_MASK
| OMAP24XX_EN_MCSPI2_MASK
|
186 OMAP24XX_EN_MCSPI1_MASK
| OMAP24XX_EN_DSS1_MASK
))
188 /* Check for UART3. */
189 l
= cm_read_mod_reg(CORE_MOD
, OMAP24XX_CM_FCLKEN2
);
190 if (l
& OMAP24XX_EN_UART3_MASK
)
192 if (sti_console_enabled
)
198 static void omap2_enter_mpu_retention(void)
201 struct timespec ts_preidle
, ts_postidle
, ts_idle
;
203 /* Putting MPU into the WFI state while a transfer is active
204 * seems to cause the I2C block to timeout. Why? Good question. */
205 if (omap2_i2c_active())
208 /* The peripherals seem not to be able to wake up the MPU when
209 * it is in retention mode. */
210 if (omap2_allow_mpu_retention()) {
211 /* REVISIT: These write to reserved bits? */
212 prm_write_mod_reg(0xffffffff, CORE_MOD
, PM_WKST1
);
213 prm_write_mod_reg(0xffffffff, CORE_MOD
, OMAP24XX_PM_WKST2
);
214 prm_write_mod_reg(0xffffffff, WKUP_MOD
, PM_WKST
);
216 /* Try to enter MPU retention */
217 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT
) |
218 OMAP_LOGICRETSTATE_MASK
,
219 MPU_MOD
, OMAP2_PM_PWSTCTRL
);
221 /* Block MPU retention */
223 prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK
, MPU_MOD
,
228 if (omap2_pm_debug
) {
229 omap2_pm_dump(only_idle
? 2 : 1, 0, 0);
230 getnstimeofday(&ts_preidle
);
235 if (omap2_pm_debug
) {
236 unsigned long long tmp
;
238 getnstimeofday(&ts_postidle
);
239 ts_idle
= timespec_sub(ts_postidle
, ts_preidle
);
240 tmp
= timespec_to_ns(&ts_idle
) * NSEC_PER_USEC
;
241 omap2_pm_dump(only_idle
? 2 : 1, 1, tmp
);
245 static int omap2_can_sleep(void)
247 if (omap2_fclks_active())
249 if (osc_ck
->usecount
> 1)
251 if (omap_dma_running())
257 static void omap2_pm_idle(void)
262 if (!omap2_can_sleep()) {
263 if (omap_irq_pending())
265 omap2_enter_mpu_retention();
269 if (omap_irq_pending())
272 omap2_enter_full_retention();
279 static int omap2_pm_prepare(void)
281 /* We cannot sleep in idle until we have resumed */
286 static int omap2_pm_suspend(void)
290 wken_wkup
= prm_read_mod_reg(WKUP_MOD
, PM_WKEN
);
291 wken_wkup
&= ~OMAP24XX_EN_GPT1_MASK
;
292 prm_write_mod_reg(wken_wkup
, WKUP_MOD
, PM_WKEN
);
295 mir1
= omap_readl(0x480fe0a4);
296 omap_writel(1 << 5, 0x480fe0ac);
298 omap_uart_prepare_suspend();
299 omap2_enter_full_retention();
301 omap_writel(mir1
, 0x480fe0a4);
302 prm_write_mod_reg(wken_wkup
, WKUP_MOD
, PM_WKEN
);
307 static int omap2_pm_enter(suspend_state_t state
)
312 case PM_SUSPEND_STANDBY
:
314 ret
= omap2_pm_suspend();
323 static void omap2_pm_finish(void)
328 static struct platform_suspend_ops omap_pm_ops
= {
329 .prepare
= omap2_pm_prepare
,
330 .enter
= omap2_pm_enter
,
331 .finish
= omap2_pm_finish
,
332 .valid
= suspend_valid_only_mem
,
335 /* XXX This function should be shareable between OMAP2xxx and OMAP3 */
336 static int __init
clkdms_setup(struct clockdomain
*clkdm
, void *unused
)
338 clkdm_clear_all_wkdeps(clkdm
);
339 clkdm_clear_all_sleepdeps(clkdm
);
341 if (clkdm
->flags
& CLKDM_CAN_ENABLE_AUTO
)
342 omap2_clkdm_allow_idle(clkdm
);
343 else if (clkdm
->flags
& CLKDM_CAN_FORCE_SLEEP
&&
344 atomic_read(&clkdm
->usecount
) == 0)
345 omap2_clkdm_sleep(clkdm
);
349 static void __init
prcm_setup_regs(void)
351 int i
, num_mem_banks
;
352 struct powerdomain
*pwrdm
;
354 /* Enable autoidle */
355 prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK
, OCP_MOD
,
356 OMAP2_PRCM_SYSCONFIG_OFFSET
);
359 * Set CORE powerdomain memory banks to retain their contents
362 num_mem_banks
= pwrdm_get_mem_bank_count(core_pwrdm
);
363 for (i
= 0; i
< num_mem_banks
; i
++)
364 pwrdm_set_mem_retst(core_pwrdm
, i
, PWRDM_POWER_RET
);
366 /* Set CORE powerdomain's next power state to RETENTION */
367 pwrdm_set_next_pwrst(core_pwrdm
, PWRDM_POWER_RET
);
370 * Set MPU powerdomain's next power state to RETENTION;
371 * preserve logic state during retention
373 pwrdm_set_logic_retst(mpu_pwrdm
, PWRDM_POWER_RET
);
374 pwrdm_set_next_pwrst(mpu_pwrdm
, PWRDM_POWER_RET
);
376 /* Force-power down DSP, GFX powerdomains */
378 pwrdm
= clkdm_get_pwrdm(dsp_clkdm
);
379 pwrdm_set_next_pwrst(pwrdm
, PWRDM_POWER_OFF
);
380 omap2_clkdm_sleep(dsp_clkdm
);
382 pwrdm
= clkdm_get_pwrdm(gfx_clkdm
);
383 pwrdm_set_next_pwrst(pwrdm
, PWRDM_POWER_OFF
);
384 omap2_clkdm_sleep(gfx_clkdm
);
387 * Clear clockdomain wakeup dependencies and enable
388 * hardware-supervised idle for all clkdms
390 clkdm_for_each(clkdms_setup
, NULL
);
391 clkdm_add_wkdep(mpu_clkdm
, wkup_clkdm
);
393 /* Enable clock autoidle for all domains */
394 cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK
|
395 OMAP24XX_AUTO_MAILBOXES_MASK
|
396 OMAP24XX_AUTO_WDT4_MASK
|
397 OMAP2420_AUTO_WDT3_MASK
|
398 OMAP24XX_AUTO_MSPRO_MASK
|
399 OMAP2420_AUTO_MMC_MASK
|
400 OMAP24XX_AUTO_FAC_MASK
|
401 OMAP2420_AUTO_EAC_MASK
|
402 OMAP24XX_AUTO_HDQ_MASK
|
403 OMAP24XX_AUTO_UART2_MASK
|
404 OMAP24XX_AUTO_UART1_MASK
|
405 OMAP24XX_AUTO_I2C2_MASK
|
406 OMAP24XX_AUTO_I2C1_MASK
|
407 OMAP24XX_AUTO_MCSPI2_MASK
|
408 OMAP24XX_AUTO_MCSPI1_MASK
|
409 OMAP24XX_AUTO_MCBSP2_MASK
|
410 OMAP24XX_AUTO_MCBSP1_MASK
|
411 OMAP24XX_AUTO_GPT12_MASK
|
412 OMAP24XX_AUTO_GPT11_MASK
|
413 OMAP24XX_AUTO_GPT10_MASK
|
414 OMAP24XX_AUTO_GPT9_MASK
|
415 OMAP24XX_AUTO_GPT8_MASK
|
416 OMAP24XX_AUTO_GPT7_MASK
|
417 OMAP24XX_AUTO_GPT6_MASK
|
418 OMAP24XX_AUTO_GPT5_MASK
|
419 OMAP24XX_AUTO_GPT4_MASK
|
420 OMAP24XX_AUTO_GPT3_MASK
|
421 OMAP24XX_AUTO_GPT2_MASK
|
422 OMAP2420_AUTO_VLYNQ_MASK
|
423 OMAP24XX_AUTO_DSS_MASK
,
424 CORE_MOD
, CM_AUTOIDLE1
);
425 cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK
|
426 OMAP24XX_AUTO_SSI_MASK
|
427 OMAP24XX_AUTO_USB_MASK
,
428 CORE_MOD
, CM_AUTOIDLE2
);
429 cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK
|
430 OMAP24XX_AUTO_GPMC_MASK
|
431 OMAP24XX_AUTO_SDMA_MASK
,
432 CORE_MOD
, CM_AUTOIDLE3
);
433 cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK
|
434 OMAP24XX_AUTO_AES_MASK
|
435 OMAP24XX_AUTO_RNG_MASK
|
436 OMAP24XX_AUTO_SHA_MASK
|
437 OMAP24XX_AUTO_DES_MASK
,
438 CORE_MOD
, OMAP24XX_CM_AUTOIDLE4
);
440 cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK
, OMAP24XX_DSP_MOD
,
443 /* Put DPLL and both APLLs into autoidle mode */
444 cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT
) |
445 (0x03 << OMAP24XX_AUTO_96M_SHIFT
) |
446 (0x03 << OMAP24XX_AUTO_54M_SHIFT
),
447 PLL_MOD
, CM_AUTOIDLE
);
449 cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK
|
450 OMAP24XX_AUTO_WDT1_MASK
|
451 OMAP24XX_AUTO_MPU_WDT_MASK
|
452 OMAP24XX_AUTO_GPIOS_MASK
|
453 OMAP24XX_AUTO_32KSYNC_MASK
|
454 OMAP24XX_AUTO_GPT1_MASK
,
455 WKUP_MOD
, CM_AUTOIDLE
);
457 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
459 prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT
, OMAP24XX_GR_MOD
,
460 OMAP2_PRCM_CLKSSETUP_OFFSET
);
462 /* Configure automatic voltage transition */
463 prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT
, OMAP24XX_GR_MOD
,
464 OMAP2_PRCM_VOLTSETUP_OFFSET
);
465 prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK
|
466 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT
) |
467 OMAP24XX_MEMRETCTRL_MASK
|
468 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT
) |
469 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT
),
470 OMAP24XX_GR_MOD
, OMAP2_PRCM_VOLTCTRL_OFFSET
);
472 /* Enable wake-up events */
473 prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK
| OMAP24XX_EN_GPT1_MASK
,
477 static int __init
omap2_pm_init(void)
481 if (!cpu_is_omap24xx())
484 printk(KERN_INFO
"Power Management for OMAP2 initializing\n");
485 l
= prm_read_mod_reg(OCP_MOD
, OMAP2_PRCM_REVISION_OFFSET
);
486 printk(KERN_INFO
"PRCM revision %d.%d\n", (l
>> 4) & 0x0f, l
& 0x0f);
488 /* Look up important powerdomains */
490 mpu_pwrdm
= pwrdm_lookup("mpu_pwrdm");
492 pr_err("PM: mpu_pwrdm not found\n");
494 core_pwrdm
= pwrdm_lookup("core_pwrdm");
496 pr_err("PM: core_pwrdm not found\n");
498 /* Look up important clockdomains */
500 mpu_clkdm
= clkdm_lookup("mpu_clkdm");
502 pr_err("PM: mpu_clkdm not found\n");
504 wkup_clkdm
= clkdm_lookup("wkup_clkdm");
506 pr_err("PM: wkup_clkdm not found\n");
508 dsp_clkdm
= clkdm_lookup("dsp_clkdm");
510 pr_err("PM: dsp_clkdm not found\n");
512 gfx_clkdm
= clkdm_lookup("gfx_clkdm");
514 pr_err("PM: gfx_clkdm not found\n");
517 osc_ck
= clk_get(NULL
, "osc_ck");
518 if (IS_ERR(osc_ck
)) {
519 printk(KERN_ERR
"could not get osc_ck\n");
523 if (cpu_is_omap242x()) {
524 emul_ck
= clk_get(NULL
, "emul_ck");
525 if (IS_ERR(emul_ck
)) {
526 printk(KERN_ERR
"could not get emul_ck\n");
534 /* Hack to prevent MPU retention when STI console is enabled. */
536 const struct omap_sti_console_config
*sti
;
538 sti
= omap_get_config(OMAP_TAG_STI_CONSOLE
,
539 struct omap_sti_console_config
);
540 if (sti
!= NULL
&& sti
->enable
)
541 sti_console_enabled
= 1;
545 * We copy the assembler sleep/wakeup routines to SRAM.
546 * These routines need to be in SRAM as that's the only
547 * memory the MPU can see when it wakes up.
549 if (cpu_is_omap24xx()) {
550 omap2_sram_idle
= omap_sram_push(omap24xx_idle_loop_suspend
,
551 omap24xx_idle_loop_suspend_sz
);
553 omap2_sram_suspend
= omap_sram_push(omap24xx_cpu_suspend
,
554 omap24xx_cpu_suspend_sz
);
557 suspend_set_ops(&omap_pm_ops
);
558 pm_idle
= omap2_pm_idle
;
563 late_initcall(omap2_pm_init
);