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ARM: OMAP2+: powerdomain: allow pre/post transtion to be per pwrdm
[deliverable/linux.git] / arch / arm / mach-omap2 / pm34xx.c
1 /*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21 #include <linux/pm.h>
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
31 #include <trace/events/power.h>
32
33 #include <asm/suspend.h>
34 #include <asm/system_misc.h>
35
36 #include <plat/sram.h>
37 #include "clockdomain.h"
38 #include "powerdomain.h"
39 #include <plat/sdrc.h>
40 #include <plat/prcm.h>
41 #include <plat/gpmc.h>
42 #include <plat/dma.h>
43
44 #include "common.h"
45 #include "cm2xxx_3xxx.h"
46 #include "cm-regbits-34xx.h"
47 #include "prm-regbits-34xx.h"
48
49 #include "prm2xxx_3xxx.h"
50 #include "pm.h"
51 #include "sdrc.h"
52 #include "control.h"
53
54 /* pm34xx errata defined in pm.h */
55 u16 pm34xx_errata;
56
57 struct power_state {
58 struct powerdomain *pwrdm;
59 u32 next_state;
60 #ifdef CONFIG_SUSPEND
61 u32 saved_state;
62 #endif
63 struct list_head node;
64 };
65
66 static LIST_HEAD(pwrst_list);
67
68 static int (*_omap_save_secure_sram)(u32 *addr);
69 void (*omap3_do_wfi_sram)(void);
70
71 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
72 static struct powerdomain *core_pwrdm, *per_pwrdm;
73 static struct powerdomain *cam_pwrdm;
74
75 static void omap3_core_save_context(void)
76 {
77 omap3_ctrl_save_padconf();
78
79 /*
80 * Force write last pad into memory, as this can fail in some
81 * cases according to errata 1.157, 1.185
82 */
83 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
84 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
85
86 /* Save the Interrupt controller context */
87 omap_intc_save_context();
88 /* Save the GPMC context */
89 omap3_gpmc_save_context();
90 /* Save the system control module context, padconf already save above*/
91 omap3_control_save_context();
92 omap_dma_global_context_save();
93 }
94
95 static void omap3_core_restore_context(void)
96 {
97 /* Restore the control module context, padconf restored by h/w */
98 omap3_control_restore_context();
99 /* Restore the GPMC context */
100 omap3_gpmc_restore_context();
101 /* Restore the interrupt controller context */
102 omap_intc_restore_context();
103 omap_dma_global_context_restore();
104 }
105
106 /*
107 * FIXME: This function should be called before entering off-mode after
108 * OMAP3 secure services have been accessed. Currently it is only called
109 * once during boot sequence, but this works as we are not using secure
110 * services.
111 */
112 static void omap3_save_secure_ram_context(void)
113 {
114 u32 ret;
115 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
116
117 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
118 /*
119 * MPU next state must be set to POWER_ON temporarily,
120 * otherwise the WFI executed inside the ROM code
121 * will hang the system.
122 */
123 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
124 ret = _omap_save_secure_sram((u32 *)
125 __pa(omap3_secure_ram_storage));
126 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
127 /* Following is for error tracking, it should not happen */
128 if (ret) {
129 pr_err("save_secure_sram() returns %08x\n", ret);
130 while (1)
131 ;
132 }
133 }
134 }
135
136 /*
137 * PRCM Interrupt Handler Helper Function
138 *
139 * The purpose of this function is to clear any wake-up events latched
140 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
141 * may occur whilst attempting to clear a PM_WKST_x register and thus
142 * set another bit in this register. A while loop is used to ensure
143 * that any peripheral wake-up events occurring while attempting to
144 * clear the PM_WKST_x are detected and cleared.
145 */
146 static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
147 {
148 u32 wkst, fclk, iclk, clken;
149 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
150 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
151 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
152 u16 grpsel_off = (regs == 3) ?
153 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
154 int c = 0;
155
156 wkst = omap2_prm_read_mod_reg(module, wkst_off);
157 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
158 wkst &= ~ignore_bits;
159 if (wkst) {
160 iclk = omap2_cm_read_mod_reg(module, iclk_off);
161 fclk = omap2_cm_read_mod_reg(module, fclk_off);
162 while (wkst) {
163 clken = wkst;
164 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
165 /*
166 * For USBHOST, we don't know whether HOST1 or
167 * HOST2 woke us up, so enable both f-clocks
168 */
169 if (module == OMAP3430ES2_USBHOST_MOD)
170 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
171 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
172 omap2_prm_write_mod_reg(wkst, module, wkst_off);
173 wkst = omap2_prm_read_mod_reg(module, wkst_off);
174 wkst &= ~ignore_bits;
175 c++;
176 }
177 omap2_cm_write_mod_reg(iclk, module, iclk_off);
178 omap2_cm_write_mod_reg(fclk, module, fclk_off);
179 }
180
181 return c;
182 }
183
184 static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
185 {
186 int c;
187
188 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
189 ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
190
191 return c ? IRQ_HANDLED : IRQ_NONE;
192 }
193
194 static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
195 {
196 int c;
197
198 /*
199 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
200 * these are handled in a separate handler to avoid acking
201 * IO events before parsing in mux code
202 */
203 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
204 OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
205 c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
206 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
207 if (omap_rev() > OMAP3430_REV_ES1_0) {
208 c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
209 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
210 }
211
212 return c ? IRQ_HANDLED : IRQ_NONE;
213 }
214
215 static void omap34xx_save_context(u32 *save)
216 {
217 u32 val;
218
219 /* Read Auxiliary Control Register */
220 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
221 *save++ = 1;
222 *save++ = val;
223
224 /* Read L2 AUX ctrl register */
225 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
226 *save++ = 1;
227 *save++ = val;
228 }
229
230 static int omap34xx_do_sram_idle(unsigned long save_state)
231 {
232 omap34xx_cpu_suspend(save_state);
233 return 0;
234 }
235
236 void omap_sram_idle(void)
237 {
238 /* Variable to tell what needs to be saved and restored
239 * in omap_sram_idle*/
240 /* save_state = 0 => Nothing to save and restored */
241 /* save_state = 1 => Only L1 and logic lost */
242 /* save_state = 2 => Only L2 lost */
243 /* save_state = 3 => L1, L2 and logic lost */
244 int save_state = 0;
245 int mpu_next_state = PWRDM_POWER_ON;
246 int per_next_state = PWRDM_POWER_ON;
247 int core_next_state = PWRDM_POWER_ON;
248 int per_going_off;
249 int core_prev_state;
250 u32 sdrc_pwr = 0;
251
252 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
253 switch (mpu_next_state) {
254 case PWRDM_POWER_ON:
255 case PWRDM_POWER_RET:
256 /* No need to save context */
257 save_state = 0;
258 break;
259 case PWRDM_POWER_OFF:
260 save_state = 3;
261 break;
262 default:
263 /* Invalid state */
264 pr_err("Invalid mpu state in sram_idle\n");
265 return;
266 }
267
268 /* NEON control */
269 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
270 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
271
272 /* Enable IO-PAD and IO-CHAIN wakeups */
273 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
274 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
275
276 pwrdm_pre_transition(NULL);
277
278 /* PER */
279 if (per_next_state < PWRDM_POWER_ON) {
280 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
281 omap2_gpio_prepare_for_idle(per_going_off);
282 }
283
284 /* CORE */
285 if (core_next_state < PWRDM_POWER_ON) {
286 if (core_next_state == PWRDM_POWER_OFF) {
287 omap3_core_save_context();
288 omap3_cm_save_context();
289 }
290 }
291
292 omap3_intc_prepare_idle();
293
294 /*
295 * On EMU/HS devices ROM code restores a SRDC value
296 * from scratchpad which has automatic self refresh on timeout
297 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
298 * Hence store/restore the SDRC_POWER register here.
299 */
300 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
301 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
302 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
303 core_next_state == PWRDM_POWER_OFF)
304 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
305
306 /*
307 * omap3_arm_context is the location where some ARM context
308 * get saved. The rest is placed on the stack, and restored
309 * from there before resuming.
310 */
311 if (save_state)
312 omap34xx_save_context(omap3_arm_context);
313 if (save_state == 1 || save_state == 3)
314 cpu_suspend(save_state, omap34xx_do_sram_idle);
315 else
316 omap34xx_do_sram_idle(save_state);
317
318 /* Restore normal SDRC POWER settings */
319 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
320 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
321 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
322 core_next_state == PWRDM_POWER_OFF)
323 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
324
325 /* CORE */
326 if (core_next_state < PWRDM_POWER_ON) {
327 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
328 if (core_prev_state == PWRDM_POWER_OFF) {
329 omap3_core_restore_context();
330 omap3_cm_restore_context();
331 omap3_sram_restore_context();
332 omap2_sms_restore_context();
333 }
334 if (core_next_state == PWRDM_POWER_OFF)
335 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
336 OMAP3430_GR_MOD,
337 OMAP3_PRM_VOLTCTRL_OFFSET);
338 }
339 omap3_intc_resume_idle();
340
341 pwrdm_post_transition(NULL);
342
343 /* PER */
344 if (per_next_state < PWRDM_POWER_ON)
345 omap2_gpio_resume_after_idle();
346
347 clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
348 }
349
350 static void omap3_pm_idle(void)
351 {
352 local_fiq_disable();
353
354 if (omap_irq_pending())
355 goto out;
356
357 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
358 trace_cpu_idle(1, smp_processor_id());
359
360 omap_sram_idle();
361
362 trace_power_end(smp_processor_id());
363 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
364
365 out:
366 local_fiq_enable();
367 }
368
369 #ifdef CONFIG_SUSPEND
370 static int omap3_pm_suspend(void)
371 {
372 struct power_state *pwrst;
373 int state, ret = 0;
374
375 /* Read current next_pwrsts */
376 list_for_each_entry(pwrst, &pwrst_list, node)
377 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
378 /* Set ones wanted by suspend */
379 list_for_each_entry(pwrst, &pwrst_list, node) {
380 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
381 goto restore;
382 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
383 goto restore;
384 }
385
386 omap3_intc_suspend();
387
388 omap_sram_idle();
389
390 restore:
391 /* Restore next_pwrsts */
392 list_for_each_entry(pwrst, &pwrst_list, node) {
393 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
394 if (state > pwrst->next_state) {
395 pr_info("Powerdomain (%s) didn't enter "
396 "target state %d\n",
397 pwrst->pwrdm->name, pwrst->next_state);
398 ret = -1;
399 }
400 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
401 }
402 if (ret)
403 pr_err("Could not enter target state in pm_suspend\n");
404 else
405 pr_info("Successfully put all powerdomains to target state\n");
406
407 return ret;
408 }
409
410 #endif /* CONFIG_SUSPEND */
411
412
413 /**
414 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
415 * retention
416 *
417 * In cases where IVA2 is activated by bootcode, it may prevent
418 * full-chip retention or off-mode because it is not idle. This
419 * function forces the IVA2 into idle state so it can go
420 * into retention/off and thus allow full-chip retention/off.
421 *
422 **/
423 static void __init omap3_iva_idle(void)
424 {
425 /* ensure IVA2 clock is disabled */
426 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
427
428 /* if no clock activity, nothing else to do */
429 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
430 OMAP3430_CLKACTIVITY_IVA2_MASK))
431 return;
432
433 /* Reset IVA2 */
434 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
435 OMAP3430_RST2_IVA2_MASK |
436 OMAP3430_RST3_IVA2_MASK,
437 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
438
439 /* Enable IVA2 clock */
440 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
441 OMAP3430_IVA2_MOD, CM_FCLKEN);
442
443 /* Set IVA2 boot mode to 'idle' */
444 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
445 OMAP343X_CONTROL_IVA2_BOOTMOD);
446
447 /* Un-reset IVA2 */
448 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
449
450 /* Disable IVA2 clock */
451 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
452
453 /* Reset IVA2 */
454 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
455 OMAP3430_RST2_IVA2_MASK |
456 OMAP3430_RST3_IVA2_MASK,
457 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
458 }
459
460 static void __init omap3_d2d_idle(void)
461 {
462 u16 mask, padconf;
463
464 /* In a stand alone OMAP3430 where there is not a stacked
465 * modem for the D2D Idle Ack and D2D MStandby must be pulled
466 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
467 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
468 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
469 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
470 padconf |= mask;
471 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
472
473 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
474 padconf |= mask;
475 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
476
477 /* reset modem */
478 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
479 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
480 CORE_MOD, OMAP2_RM_RSTCTRL);
481 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
482 }
483
484 static void __init prcm_setup_regs(void)
485 {
486 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
487 OMAP3630_EN_UART4_MASK : 0;
488 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
489 OMAP3630_GRPSEL_UART4_MASK : 0;
490
491 /* XXX This should be handled by hwmod code or SCM init code */
492 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
493
494 /*
495 * Enable control of expternal oscillator through
496 * sys_clkreq. In the long run clock framework should
497 * take care of this.
498 */
499 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
500 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
501 OMAP3430_GR_MOD,
502 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
503
504 /* setup wakup source */
505 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
506 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
507 WKUP_MOD, PM_WKEN);
508 /* No need to write EN_IO, that is always enabled */
509 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
510 OMAP3430_GRPSEL_GPT1_MASK |
511 OMAP3430_GRPSEL_GPT12_MASK,
512 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
513
514 /* Enable PM_WKEN to support DSS LPR */
515 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
516 OMAP3430_DSS_MOD, PM_WKEN);
517
518 /* Enable wakeups in PER */
519 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
520 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
521 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
522 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
523 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
524 OMAP3430_EN_MCBSP4_MASK,
525 OMAP3430_PER_MOD, PM_WKEN);
526 /* and allow them to wake up MPU */
527 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
528 OMAP3430_GRPSEL_GPIO2_MASK |
529 OMAP3430_GRPSEL_GPIO3_MASK |
530 OMAP3430_GRPSEL_GPIO4_MASK |
531 OMAP3430_GRPSEL_GPIO5_MASK |
532 OMAP3430_GRPSEL_GPIO6_MASK |
533 OMAP3430_GRPSEL_UART3_MASK |
534 OMAP3430_GRPSEL_MCBSP2_MASK |
535 OMAP3430_GRPSEL_MCBSP3_MASK |
536 OMAP3430_GRPSEL_MCBSP4_MASK,
537 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
538
539 /* Don't attach IVA interrupts */
540 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
541 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
542 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
543 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
544
545 /* Clear any pending 'reset' flags */
546 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
547 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
548 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
549 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
550 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
551 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
552 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
553
554 /* Clear any pending PRCM interrupts */
555 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
556
557 omap3_iva_idle();
558 omap3_d2d_idle();
559 }
560
561 void omap3_pm_off_mode_enable(int enable)
562 {
563 struct power_state *pwrst;
564 u32 state;
565
566 if (enable)
567 state = PWRDM_POWER_OFF;
568 else
569 state = PWRDM_POWER_RET;
570
571 list_for_each_entry(pwrst, &pwrst_list, node) {
572 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
573 pwrst->pwrdm == core_pwrdm &&
574 state == PWRDM_POWER_OFF) {
575 pwrst->next_state = PWRDM_POWER_RET;
576 pr_warn("%s: Core OFF disabled due to errata i583\n",
577 __func__);
578 } else {
579 pwrst->next_state = state;
580 }
581 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
582 }
583 }
584
585 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
586 {
587 struct power_state *pwrst;
588
589 list_for_each_entry(pwrst, &pwrst_list, node) {
590 if (pwrst->pwrdm == pwrdm)
591 return pwrst->next_state;
592 }
593 return -EINVAL;
594 }
595
596 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
597 {
598 struct power_state *pwrst;
599
600 list_for_each_entry(pwrst, &pwrst_list, node) {
601 if (pwrst->pwrdm == pwrdm) {
602 pwrst->next_state = state;
603 return 0;
604 }
605 }
606 return -EINVAL;
607 }
608
609 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
610 {
611 struct power_state *pwrst;
612
613 if (!pwrdm->pwrsts)
614 return 0;
615
616 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
617 if (!pwrst)
618 return -ENOMEM;
619 pwrst->pwrdm = pwrdm;
620 pwrst->next_state = PWRDM_POWER_RET;
621 list_add(&pwrst->node, &pwrst_list);
622
623 if (pwrdm_has_hdwr_sar(pwrdm))
624 pwrdm_enable_hdwr_sar(pwrdm);
625
626 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
627 }
628
629 /*
630 * Push functions to SRAM
631 *
632 * The minimum set of functions is pushed to SRAM for execution:
633 * - omap3_do_wfi for erratum i581 WA,
634 * - save_secure_ram_context for security extensions.
635 */
636 void omap_push_sram_idle(void)
637 {
638 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
639
640 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
641 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
642 save_secure_ram_context_sz);
643 }
644
645 static void __init pm_errata_configure(void)
646 {
647 if (cpu_is_omap3630()) {
648 pm34xx_errata |= PM_RTA_ERRATUM_i608;
649 /* Enable the l2 cache toggling in sleep logic */
650 enable_omap3630_toggle_l2_on_restore();
651 if (omap_rev() < OMAP3630_REV_ES1_2)
652 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
653 }
654 }
655
656 int __init omap3_pm_init(void)
657 {
658 struct power_state *pwrst, *tmp;
659 struct clockdomain *neon_clkdm, *mpu_clkdm;
660 int ret;
661
662 if (!omap3_has_io_chain_ctrl())
663 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
664
665 pm_errata_configure();
666
667 /* XXX prcm_setup_regs needs to be before enabling hw
668 * supervised mode for powerdomains */
669 prcm_setup_regs();
670
671 ret = request_irq(omap_prcm_event_to_irq("wkup"),
672 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
673
674 if (ret) {
675 pr_err("pm: Failed to request pm_wkup irq\n");
676 goto err1;
677 }
678
679 /* IO interrupt is shared with mux code */
680 ret = request_irq(omap_prcm_event_to_irq("io"),
681 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
682 omap3_pm_init);
683 enable_irq(omap_prcm_event_to_irq("io"));
684
685 if (ret) {
686 pr_err("pm: Failed to request pm_io irq\n");
687 goto err2;
688 }
689
690 ret = pwrdm_for_each(pwrdms_setup, NULL);
691 if (ret) {
692 pr_err("Failed to setup powerdomains\n");
693 goto err3;
694 }
695
696 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
697
698 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
699 if (mpu_pwrdm == NULL) {
700 pr_err("Failed to get mpu_pwrdm\n");
701 ret = -EINVAL;
702 goto err3;
703 }
704
705 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
706 per_pwrdm = pwrdm_lookup("per_pwrdm");
707 core_pwrdm = pwrdm_lookup("core_pwrdm");
708 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
709
710 neon_clkdm = clkdm_lookup("neon_clkdm");
711 mpu_clkdm = clkdm_lookup("mpu_clkdm");
712
713 #ifdef CONFIG_SUSPEND
714 omap_pm_suspend = omap3_pm_suspend;
715 #endif
716
717 arm_pm_idle = omap3_pm_idle;
718 omap3_idle_init();
719
720 /*
721 * RTA is disabled during initialization as per erratum i608
722 * it is safer to disable RTA by the bootloader, but we would like
723 * to be doubly sure here and prevent any mishaps.
724 */
725 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
726 omap3630_ctrl_disable_rta();
727
728 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
729 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
730 omap3_secure_ram_storage =
731 kmalloc(0x803F, GFP_KERNEL);
732 if (!omap3_secure_ram_storage)
733 pr_err("Memory allocation failed when "
734 "allocating for secure sram context\n");
735
736 local_irq_disable();
737 local_fiq_disable();
738
739 omap_dma_global_context_save();
740 omap3_save_secure_ram_context();
741 omap_dma_global_context_restore();
742
743 local_irq_enable();
744 local_fiq_enable();
745 }
746
747 omap3_save_scratchpad_contents();
748 return ret;
749
750 err3:
751 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
752 list_del(&pwrst->node);
753 kfree(pwrst);
754 }
755 free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
756 err2:
757 free_irq(omap_prcm_event_to_irq("wkup"), NULL);
758 err1:
759 return ret;
760 }
Linux kernel - Deliverables
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