2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
32 #include <plat/sram.h>
33 #include <plat/clockdomain.h>
34 #include <plat/powerdomain.h>
35 #include <plat/control.h>
36 #include <plat/serial.h>
37 #include <plat/sdrc.h>
38 #include <plat/prcm.h>
39 #include <plat/gpmc.h>
41 #include <plat/dmtimer.h>
43 #include <asm/tlbflush.h>
46 #include "cm-regbits-34xx.h"
47 #include "prm-regbits-34xx.h"
53 /* Scratchpad offsets */
54 #define OMAP343X_TABLE_ADDRESS_OFFSET 0x31
55 #define OMAP343X_TABLE_VALUE_OFFSET 0x30
56 #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
60 u32 wakeup_timer_seconds
;
61 u32 wakeup_timer_milliseconds
;
64 struct powerdomain
*pwrdm
;
69 struct list_head node
;
72 static LIST_HEAD(pwrst_list
);
74 static void (*_omap_sram_idle
)(u32
*addr
, int save_state
);
76 static int (*_omap_save_secure_sram
)(u32
*addr
);
78 static struct powerdomain
*mpu_pwrdm
, *neon_pwrdm
;
79 static struct powerdomain
*core_pwrdm
, *per_pwrdm
;
80 static struct powerdomain
*cam_pwrdm
;
82 static inline void omap3_per_save_context(void)
84 omap_gpio_save_context();
87 static inline void omap3_per_restore_context(void)
89 omap_gpio_restore_context();
92 static void omap3_enable_io_chain(void)
96 if (omap_rev() >= OMAP3430_REV_ES3_1
) {
97 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK
, WKUP_MOD
,
99 /* Do a readback to assure write has been done */
100 prm_read_mod_reg(WKUP_MOD
, PM_WKEN
);
102 while (!(prm_read_mod_reg(WKUP_MOD
, PM_WKEN
) &
103 OMAP3430_ST_IO_CHAIN_MASK
)) {
105 if (timeout
> 1000) {
106 printk(KERN_ERR
"Wake up daisy chain "
107 "activation failed.\n");
110 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK
,
116 static void omap3_disable_io_chain(void)
118 if (omap_rev() >= OMAP3430_REV_ES3_1
)
119 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK
, WKUP_MOD
,
123 static void omap3_core_save_context(void)
125 u32 control_padconf_off
;
127 /* Save the padconf registers */
128 control_padconf_off
= omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF
);
129 control_padconf_off
|= START_PADCONF_SAVE
;
130 omap_ctrl_writel(control_padconf_off
, OMAP343X_CONTROL_PADCONF_OFF
);
131 /* wait for the save to complete */
132 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS
)
133 & PADCONF_SAVE_DONE
))
137 * Force write last pad into memory, as this can fail in some
138 * cases according to erratas 1.157, 1.185
140 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14
),
141 OMAP343X_CONTROL_MEM_WKUP
+ 0x2a0);
143 /* Save the Interrupt controller context */
144 omap_intc_save_context();
145 /* Save the GPMC context */
146 omap3_gpmc_save_context();
147 /* Save the system control module context, padconf already save above*/
148 omap3_control_save_context();
149 omap_dma_global_context_save();
152 static void omap3_core_restore_context(void)
154 /* Restore the control module context, padconf restored by h/w */
155 omap3_control_restore_context();
156 /* Restore the GPMC context */
157 omap3_gpmc_restore_context();
158 /* Restore the interrupt controller context */
159 omap_intc_restore_context();
160 omap_dma_global_context_restore();
164 * FIXME: This function should be called before entering off-mode after
165 * OMAP3 secure services have been accessed. Currently it is only called
166 * once during boot sequence, but this works as we are not using secure
169 static void omap3_save_secure_ram_context(u32 target_mpu_state
)
173 if (omap_type() != OMAP2_DEVICE_TYPE_GP
) {
175 * MPU next state must be set to POWER_ON temporarily,
176 * otherwise the WFI executed inside the ROM code
177 * will hang the system.
179 pwrdm_set_next_pwrst(mpu_pwrdm
, PWRDM_POWER_ON
);
180 ret
= _omap_save_secure_sram((u32
*)
181 __pa(omap3_secure_ram_storage
));
182 pwrdm_set_next_pwrst(mpu_pwrdm
, target_mpu_state
);
183 /* Following is for error tracking, it should not happen */
185 printk(KERN_ERR
"save_secure_sram() returns %08x\n",
194 * PRCM Interrupt Handler Helper Function
196 * The purpose of this function is to clear any wake-up events latched
197 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
198 * may occur whilst attempting to clear a PM_WKST_x register and thus
199 * set another bit in this register. A while loop is used to ensure
200 * that any peripheral wake-up events occurring while attempting to
201 * clear the PM_WKST_x are detected and cleared.
203 static int prcm_clear_mod_irqs(s16 module
, u8 regs
)
205 u32 wkst
, fclk
, iclk
, clken
;
206 u16 wkst_off
= (regs
== 3) ? OMAP3430ES2_PM_WKST3
: PM_WKST1
;
207 u16 fclk_off
= (regs
== 3) ? OMAP3430ES2_CM_FCLKEN3
: CM_FCLKEN1
;
208 u16 iclk_off
= (regs
== 3) ? CM_ICLKEN3
: CM_ICLKEN1
;
209 u16 grpsel_off
= (regs
== 3) ?
210 OMAP3430ES2_PM_MPUGRPSEL3
: OMAP3430_PM_MPUGRPSEL
;
213 wkst
= prm_read_mod_reg(module
, wkst_off
);
214 wkst
&= prm_read_mod_reg(module
, grpsel_off
);
216 iclk
= cm_read_mod_reg(module
, iclk_off
);
217 fclk
= cm_read_mod_reg(module
, fclk_off
);
220 cm_set_mod_reg_bits(clken
, module
, iclk_off
);
222 * For USBHOST, we don't know whether HOST1 or
223 * HOST2 woke us up, so enable both f-clocks
225 if (module
== OMAP3430ES2_USBHOST_MOD
)
226 clken
|= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT
;
227 cm_set_mod_reg_bits(clken
, module
, fclk_off
);
228 prm_write_mod_reg(wkst
, module
, wkst_off
);
229 wkst
= prm_read_mod_reg(module
, wkst_off
);
232 cm_write_mod_reg(iclk
, module
, iclk_off
);
233 cm_write_mod_reg(fclk
, module
, fclk_off
);
239 static int _prcm_int_handle_wakeup(void)
243 c
= prcm_clear_mod_irqs(WKUP_MOD
, 1);
244 c
+= prcm_clear_mod_irqs(CORE_MOD
, 1);
245 c
+= prcm_clear_mod_irqs(OMAP3430_PER_MOD
, 1);
246 if (omap_rev() > OMAP3430_REV_ES1_0
) {
247 c
+= prcm_clear_mod_irqs(CORE_MOD
, 3);
248 c
+= prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD
, 1);
255 * PRCM Interrupt Handler
257 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
258 * interrupts from the PRCM for the MPU. These bits must be cleared in
259 * order to clear the PRCM interrupt. The PRCM interrupt handler is
260 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
261 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
262 * register indicates that a wake-up event is pending for the MPU and
263 * this bit can only be cleared if the all the wake-up events latched
264 * in the various PM_WKST_x registers have been cleared. The interrupt
265 * handler is implemented using a do-while loop so that if a wake-up
266 * event occurred during the processing of the prcm interrupt handler
267 * (setting a bit in the corresponding PM_WKST_x register and thus
268 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
269 * this would be handled.
271 static irqreturn_t
prcm_interrupt_handler (int irq
, void *dev_id
)
273 u32 irqenable_mpu
, irqstatus_mpu
;
276 irqenable_mpu
= prm_read_mod_reg(OCP_MOD
,
277 OMAP3_PRM_IRQENABLE_MPU_OFFSET
);
278 irqstatus_mpu
= prm_read_mod_reg(OCP_MOD
,
279 OMAP3_PRM_IRQSTATUS_MPU_OFFSET
);
280 irqstatus_mpu
&= irqenable_mpu
;
283 if (irqstatus_mpu
& (OMAP3430_WKUP_ST_MASK
|
284 OMAP3430_IO_ST_MASK
)) {
285 c
= _prcm_int_handle_wakeup();
288 * Is the MPU PRCM interrupt handler racing with the
289 * IVA2 PRCM interrupt handler ?
291 WARN(c
== 0, "prcm: WARNING: PRCM indicated MPU wakeup "
292 "but no wakeup sources are marked\n");
294 /* XXX we need to expand our PRCM interrupt handler */
295 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
296 "no code to handle it (%08x)\n", irqstatus_mpu
);
299 prm_write_mod_reg(irqstatus_mpu
, OCP_MOD
,
300 OMAP3_PRM_IRQSTATUS_MPU_OFFSET
);
302 irqstatus_mpu
= prm_read_mod_reg(OCP_MOD
,
303 OMAP3_PRM_IRQSTATUS_MPU_OFFSET
);
304 irqstatus_mpu
&= irqenable_mpu
;
306 } while (irqstatus_mpu
);
311 static void restore_control_register(u32 val
)
313 __asm__
__volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val
));
316 /* Function to restore the table entry that was modified for enabling MMU */
317 static void restore_table_entry(void)
319 u32
*scratchpad_address
;
320 u32 previous_value
, control_reg_value
;
323 scratchpad_address
= OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD
);
325 /* Get address of entry that was modified */
326 address
= (u32
*)__raw_readl(scratchpad_address
+
327 OMAP343X_TABLE_ADDRESS_OFFSET
);
328 /* Get the previous value which needs to be restored */
329 previous_value
= __raw_readl(scratchpad_address
+
330 OMAP343X_TABLE_VALUE_OFFSET
);
331 address
= __va(address
);
332 *address
= previous_value
;
334 control_reg_value
= __raw_readl(scratchpad_address
335 + OMAP343X_CONTROL_REG_VALUE_OFFSET
);
336 /* This will enable caches and prediction */
337 restore_control_register(control_reg_value
);
340 void omap_sram_idle(void)
342 /* Variable to tell what needs to be saved and restored
343 * in omap_sram_idle*/
344 /* save_state = 0 => Nothing to save and restored */
345 /* save_state = 1 => Only L1 and logic lost */
346 /* save_state = 2 => Only L2 lost */
347 /* save_state = 3 => L1, L2 and logic lost */
349 int mpu_next_state
= PWRDM_POWER_ON
;
350 int per_next_state
= PWRDM_POWER_ON
;
351 int core_next_state
= PWRDM_POWER_ON
;
352 int core_prev_state
, per_prev_state
;
354 int per_state_modified
= 0;
356 if (!_omap_sram_idle
)
359 pwrdm_clear_all_prev_pwrst(mpu_pwrdm
);
360 pwrdm_clear_all_prev_pwrst(neon_pwrdm
);
361 pwrdm_clear_all_prev_pwrst(core_pwrdm
);
362 pwrdm_clear_all_prev_pwrst(per_pwrdm
);
364 mpu_next_state
= pwrdm_read_next_pwrst(mpu_pwrdm
);
365 switch (mpu_next_state
) {
367 case PWRDM_POWER_RET
:
368 /* No need to save context */
371 case PWRDM_POWER_OFF
:
376 printk(KERN_ERR
"Invalid mpu state in sram_idle\n");
379 pwrdm_pre_transition();
382 if (pwrdm_read_pwrst(neon_pwrdm
) == PWRDM_POWER_ON
)
383 pwrdm_set_next_pwrst(neon_pwrdm
, mpu_next_state
);
385 /* Enable IO-PAD and IO-CHAIN wakeups */
386 per_next_state
= pwrdm_read_next_pwrst(per_pwrdm
);
387 core_next_state
= pwrdm_read_next_pwrst(core_pwrdm
);
388 if (omap3_has_io_wakeup() && \
389 (per_next_state
< PWRDM_POWER_ON
||
390 core_next_state
< PWRDM_POWER_ON
)) {
391 prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK
, WKUP_MOD
, PM_WKEN
);
392 omap3_enable_io_chain();
396 if (per_next_state
< PWRDM_POWER_ON
) {
397 omap_uart_prepare_idle(2);
398 omap2_gpio_prepare_for_idle(per_next_state
);
399 if (per_next_state
== PWRDM_POWER_OFF
) {
400 if (core_next_state
== PWRDM_POWER_ON
) {
401 per_next_state
= PWRDM_POWER_RET
;
402 pwrdm_set_next_pwrst(per_pwrdm
, per_next_state
);
403 per_state_modified
= 1;
405 omap3_per_save_context();
409 if (pwrdm_read_pwrst(cam_pwrdm
) == PWRDM_POWER_ON
)
410 omap2_clkdm_deny_idle(mpu_pwrdm
->pwrdm_clkdms
[0]);
413 if (core_next_state
< PWRDM_POWER_ON
) {
414 omap_uart_prepare_idle(0);
415 omap_uart_prepare_idle(1);
416 if (core_next_state
== PWRDM_POWER_OFF
) {
417 omap3_core_save_context();
418 omap3_prcm_save_context();
422 omap3_intc_prepare_idle();
425 * On EMU/HS devices ROM code restores a SRDC value
426 * from scratchpad which has automatic self refresh on timeout
427 * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
428 * Hence store/restore the SDRC_POWER register here.
430 if (omap_rev() >= OMAP3430_REV_ES3_0
&&
431 omap_type() != OMAP2_DEVICE_TYPE_GP
&&
432 core_next_state
== PWRDM_POWER_OFF
)
433 sdrc_pwr
= sdrc_read_reg(SDRC_POWER
);
436 * omap3_arm_context is the location where ARM registers
437 * get saved. The restore path then reads from this
438 * location and restores them back.
440 _omap_sram_idle(omap3_arm_context
, save_state
);
443 /* Restore normal SDRC POWER settings */
444 if (omap_rev() >= OMAP3430_REV_ES3_0
&&
445 omap_type() != OMAP2_DEVICE_TYPE_GP
&&
446 core_next_state
== PWRDM_POWER_OFF
)
447 sdrc_write_reg(sdrc_pwr
, SDRC_POWER
);
449 /* Restore table entry modified during MMU restoration */
450 if (pwrdm_read_prev_pwrst(mpu_pwrdm
) == PWRDM_POWER_OFF
)
451 restore_table_entry();
454 if (core_next_state
< PWRDM_POWER_ON
) {
455 core_prev_state
= pwrdm_read_prev_pwrst(core_pwrdm
);
456 if (core_prev_state
== PWRDM_POWER_OFF
) {
457 omap3_core_restore_context();
458 omap3_prcm_restore_context();
459 omap3_sram_restore_context();
460 omap2_sms_restore_context();
462 omap_uart_resume_idle(0);
463 omap_uart_resume_idle(1);
464 if (core_next_state
== PWRDM_POWER_OFF
)
465 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK
,
467 OMAP3_PRM_VOLTCTRL_OFFSET
);
469 omap3_intc_resume_idle();
472 if (per_next_state
< PWRDM_POWER_ON
) {
473 per_prev_state
= pwrdm_read_prev_pwrst(per_pwrdm
);
474 omap2_gpio_resume_after_idle();
475 if (per_prev_state
== PWRDM_POWER_OFF
)
476 omap3_per_restore_context();
477 omap_uart_resume_idle(2);
478 if (per_state_modified
)
479 pwrdm_set_next_pwrst(per_pwrdm
, PWRDM_POWER_OFF
);
482 /* Disable IO-PAD and IO-CHAIN wakeup */
483 if (omap3_has_io_wakeup() &&
484 (per_next_state
< PWRDM_POWER_ON
||
485 core_next_state
< PWRDM_POWER_ON
)) {
486 prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK
, WKUP_MOD
, PM_WKEN
);
487 omap3_disable_io_chain();
490 pwrdm_post_transition();
492 omap2_clkdm_allow_idle(mpu_pwrdm
->pwrdm_clkdms
[0]);
495 int omap3_can_sleep(void)
497 if (!sleep_while_idle
)
499 if (!omap_uart_can_sleep())
504 /* This sets pwrdm state (other than mpu & core. Currently only ON &
505 * RET are supported. Function is assuming that clkdm doesn't have
506 * hw_sup mode enabled. */
507 int set_pwrdm_state(struct powerdomain
*pwrdm
, u32 state
)
510 int sleep_switch
= 0;
513 if (pwrdm
== NULL
|| IS_ERR(pwrdm
))
516 while (!(pwrdm
->pwrsts
& (1 << state
))) {
517 if (state
== PWRDM_POWER_OFF
)
522 cur_state
= pwrdm_read_next_pwrst(pwrdm
);
523 if (cur_state
== state
)
526 if (pwrdm_read_pwrst(pwrdm
) < PWRDM_POWER_ON
) {
527 omap2_clkdm_wakeup(pwrdm
->pwrdm_clkdms
[0]);
529 pwrdm_wait_transition(pwrdm
);
532 ret
= pwrdm_set_next_pwrst(pwrdm
, state
);
534 printk(KERN_ERR
"Unable to set state of powerdomain: %s\n",
540 omap2_clkdm_allow_idle(pwrdm
->pwrdm_clkdms
[0]);
541 pwrdm_wait_transition(pwrdm
);
542 pwrdm_state_switch(pwrdm
);
549 static void omap3_pm_idle(void)
554 if (!omap3_can_sleep())
557 if (omap_irq_pending() || need_resched())
567 #ifdef CONFIG_SUSPEND
568 static suspend_state_t suspend_state
;
570 static void omap2_pm_wakeup_on_timer(u32 seconds
, u32 milliseconds
)
572 u32 tick_rate
, cycles
;
574 if (!seconds
&& !milliseconds
)
577 tick_rate
= clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup
));
578 cycles
= tick_rate
* seconds
+ tick_rate
* milliseconds
/ 1000;
579 omap_dm_timer_stop(gptimer_wakeup
);
580 omap_dm_timer_set_load_start(gptimer_wakeup
, 0, 0xffffffff - cycles
);
582 pr_info("PM: Resume timer in %u.%03u secs"
583 " (%d ticks at %d ticks/sec.)\n",
584 seconds
, milliseconds
, cycles
, tick_rate
);
587 static int omap3_pm_prepare(void)
593 static int omap3_pm_suspend(void)
595 struct power_state
*pwrst
;
598 if (wakeup_timer_seconds
|| wakeup_timer_milliseconds
)
599 omap2_pm_wakeup_on_timer(wakeup_timer_seconds
,
600 wakeup_timer_milliseconds
);
602 /* Read current next_pwrsts */
603 list_for_each_entry(pwrst
, &pwrst_list
, node
)
604 pwrst
->saved_state
= pwrdm_read_next_pwrst(pwrst
->pwrdm
);
605 /* Set ones wanted by suspend */
606 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
607 if (set_pwrdm_state(pwrst
->pwrdm
, pwrst
->next_state
))
609 if (pwrdm_clear_all_prev_pwrst(pwrst
->pwrdm
))
613 omap_uart_prepare_suspend();
614 omap3_intc_suspend();
619 /* Restore next_pwrsts */
620 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
621 state
= pwrdm_read_prev_pwrst(pwrst
->pwrdm
);
622 if (state
> pwrst
->next_state
) {
623 printk(KERN_INFO
"Powerdomain (%s) didn't enter "
625 pwrst
->pwrdm
->name
, pwrst
->next_state
);
628 set_pwrdm_state(pwrst
->pwrdm
, pwrst
->saved_state
);
631 printk(KERN_ERR
"Could not enter target state in pm_suspend\n");
633 printk(KERN_INFO
"Successfully put all powerdomains "
634 "to target state\n");
639 static int omap3_pm_enter(suspend_state_t unused
)
643 switch (suspend_state
) {
644 case PM_SUSPEND_STANDBY
:
646 ret
= omap3_pm_suspend();
655 static void omap3_pm_finish(void)
660 /* Hooks to enable / disable UART interrupts during suspend */
661 static int omap3_pm_begin(suspend_state_t state
)
663 suspend_state
= state
;
664 omap_uart_enable_irqs(0);
668 static void omap3_pm_end(void)
670 suspend_state
= PM_SUSPEND_ON
;
671 omap_uart_enable_irqs(1);
675 static struct platform_suspend_ops omap_pm_ops
= {
676 .begin
= omap3_pm_begin
,
678 .prepare
= omap3_pm_prepare
,
679 .enter
= omap3_pm_enter
,
680 .finish
= omap3_pm_finish
,
681 .valid
= suspend_valid_only_mem
,
683 #endif /* CONFIG_SUSPEND */
687 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
690 * In cases where IVA2 is activated by bootcode, it may prevent
691 * full-chip retention or off-mode because it is not idle. This
692 * function forces the IVA2 into idle state so it can go
693 * into retention/off and thus allow full-chip retention/off.
696 static void __init
omap3_iva_idle(void)
698 /* ensure IVA2 clock is disabled */
699 cm_write_mod_reg(0, OMAP3430_IVA2_MOD
, CM_FCLKEN
);
701 /* if no clock activity, nothing else to do */
702 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKSTST
) &
703 OMAP3430_CLKACTIVITY_IVA2_MASK
))
707 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK
|
708 OMAP3430_RST2_IVA2_MASK
|
709 OMAP3430_RST3_IVA2_MASK
,
710 OMAP3430_IVA2_MOD
, OMAP2_RM_RSTCTRL
);
712 /* Enable IVA2 clock */
713 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK
,
714 OMAP3430_IVA2_MOD
, CM_FCLKEN
);
716 /* Set IVA2 boot mode to 'idle' */
717 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE
,
718 OMAP343X_CONTROL_IVA2_BOOTMOD
);
721 prm_write_mod_reg(0, OMAP3430_IVA2_MOD
, OMAP2_RM_RSTCTRL
);
723 /* Disable IVA2 clock */
724 cm_write_mod_reg(0, OMAP3430_IVA2_MOD
, CM_FCLKEN
);
727 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK
|
728 OMAP3430_RST2_IVA2_MASK
|
729 OMAP3430_RST3_IVA2_MASK
,
730 OMAP3430_IVA2_MOD
, OMAP2_RM_RSTCTRL
);
733 static void __init
omap3_d2d_idle(void)
737 /* In a stand alone OMAP3430 where there is not a stacked
738 * modem for the D2D Idle Ack and D2D MStandby must be pulled
739 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
740 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
741 mask
= (1 << 4) | (1 << 3); /* pull-up, enabled */
742 padconf
= omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY
);
744 omap_ctrl_writew(padconf
, OMAP3_PADCONF_SAD2D_MSTANDBY
);
746 padconf
= omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK
);
748 omap_ctrl_writew(padconf
, OMAP3_PADCONF_SAD2D_IDLEACK
);
751 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK
|
752 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK
,
753 CORE_MOD
, OMAP2_RM_RSTCTRL
);
754 prm_write_mod_reg(0, CORE_MOD
, OMAP2_RM_RSTCTRL
);
757 static void __init
prcm_setup_regs(void)
759 /* XXX Reset all wkdeps. This should be done when initializing
761 prm_write_mod_reg(0, OMAP3430_IVA2_MOD
, PM_WKDEP
);
762 prm_write_mod_reg(0, MPU_MOD
, PM_WKDEP
);
763 prm_write_mod_reg(0, OMAP3430_DSS_MOD
, PM_WKDEP
);
764 prm_write_mod_reg(0, OMAP3430_NEON_MOD
, PM_WKDEP
);
765 prm_write_mod_reg(0, OMAP3430_CAM_MOD
, PM_WKDEP
);
766 prm_write_mod_reg(0, OMAP3430_PER_MOD
, PM_WKDEP
);
767 if (omap_rev() > OMAP3430_REV_ES1_0
) {
768 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD
, PM_WKDEP
);
769 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD
, PM_WKDEP
);
771 prm_write_mod_reg(0, GFX_MOD
, PM_WKDEP
);
774 * Enable interface clock autoidle for all modules.
775 * Note that in the long run this should be done by clockfw
778 OMAP3430_AUTO_MODEM_MASK
|
779 OMAP3430ES2_AUTO_MMC3_MASK
|
780 OMAP3430ES2_AUTO_ICR_MASK
|
781 OMAP3430_AUTO_AES2_MASK
|
782 OMAP3430_AUTO_SHA12_MASK
|
783 OMAP3430_AUTO_DES2_MASK
|
784 OMAP3430_AUTO_MMC2_MASK
|
785 OMAP3430_AUTO_MMC1_MASK
|
786 OMAP3430_AUTO_MSPRO_MASK
|
787 OMAP3430_AUTO_HDQ_MASK
|
788 OMAP3430_AUTO_MCSPI4_MASK
|
789 OMAP3430_AUTO_MCSPI3_MASK
|
790 OMAP3430_AUTO_MCSPI2_MASK
|
791 OMAP3430_AUTO_MCSPI1_MASK
|
792 OMAP3430_AUTO_I2C3_MASK
|
793 OMAP3430_AUTO_I2C2_MASK
|
794 OMAP3430_AUTO_I2C1_MASK
|
795 OMAP3430_AUTO_UART2_MASK
|
796 OMAP3430_AUTO_UART1_MASK
|
797 OMAP3430_AUTO_GPT11_MASK
|
798 OMAP3430_AUTO_GPT10_MASK
|
799 OMAP3430_AUTO_MCBSP5_MASK
|
800 OMAP3430_AUTO_MCBSP1_MASK
|
801 OMAP3430ES1_AUTO_FAC_MASK
| /* This is es1 only */
802 OMAP3430_AUTO_MAILBOXES_MASK
|
803 OMAP3430_AUTO_OMAPCTRL_MASK
|
804 OMAP3430ES1_AUTO_FSHOSTUSB_MASK
|
805 OMAP3430_AUTO_HSOTGUSB_MASK
|
806 OMAP3430_AUTO_SAD2D_MASK
|
807 OMAP3430_AUTO_SSI_MASK
,
808 CORE_MOD
, CM_AUTOIDLE1
);
811 OMAP3430_AUTO_PKA_MASK
|
812 OMAP3430_AUTO_AES1_MASK
|
813 OMAP3430_AUTO_RNG_MASK
|
814 OMAP3430_AUTO_SHA11_MASK
|
815 OMAP3430_AUTO_DES1_MASK
,
816 CORE_MOD
, CM_AUTOIDLE2
);
818 if (omap_rev() > OMAP3430_REV_ES1_0
) {
820 OMAP3430_AUTO_MAD2D_MASK
|
821 OMAP3430ES2_AUTO_USBTLL_MASK
,
822 CORE_MOD
, CM_AUTOIDLE3
);
826 OMAP3430_AUTO_WDT2_MASK
|
827 OMAP3430_AUTO_WDT1_MASK
|
828 OMAP3430_AUTO_GPIO1_MASK
|
829 OMAP3430_AUTO_32KSYNC_MASK
|
830 OMAP3430_AUTO_GPT12_MASK
|
831 OMAP3430_AUTO_GPT1_MASK
,
832 WKUP_MOD
, CM_AUTOIDLE
);
835 OMAP3430_AUTO_DSS_MASK
,
840 OMAP3430_AUTO_CAM_MASK
,
845 OMAP3430_AUTO_GPIO6_MASK
|
846 OMAP3430_AUTO_GPIO5_MASK
|
847 OMAP3430_AUTO_GPIO4_MASK
|
848 OMAP3430_AUTO_GPIO3_MASK
|
849 OMAP3430_AUTO_GPIO2_MASK
|
850 OMAP3430_AUTO_WDT3_MASK
|
851 OMAP3430_AUTO_UART3_MASK
|
852 OMAP3430_AUTO_GPT9_MASK
|
853 OMAP3430_AUTO_GPT8_MASK
|
854 OMAP3430_AUTO_GPT7_MASK
|
855 OMAP3430_AUTO_GPT6_MASK
|
856 OMAP3430_AUTO_GPT5_MASK
|
857 OMAP3430_AUTO_GPT4_MASK
|
858 OMAP3430_AUTO_GPT3_MASK
|
859 OMAP3430_AUTO_GPT2_MASK
|
860 OMAP3430_AUTO_MCBSP4_MASK
|
861 OMAP3430_AUTO_MCBSP3_MASK
|
862 OMAP3430_AUTO_MCBSP2_MASK
,
866 if (omap_rev() > OMAP3430_REV_ES1_0
) {
868 OMAP3430ES2_AUTO_USBHOST_MASK
,
869 OMAP3430ES2_USBHOST_MOD
,
873 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK
, OMAP2_CONTROL_SYSCONFIG
);
876 * Set all plls to autoidle. This is needed until autoidle is
879 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT
,
880 OMAP3430_IVA2_MOD
, CM_AUTOIDLE2
);
881 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT
,
884 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT
) |
885 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT
),
888 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT
,
893 * Enable control of expternal oscillator through
894 * sys_clkreq. In the long run clock framework should
897 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK
,
898 1 << OMAP_AUTOEXTCLKMODE_SHIFT
,
900 OMAP3_PRM_CLKSRC_CTRL_OFFSET
);
902 /* setup wakup source */
903 prm_write_mod_reg(OMAP3430_EN_IO_MASK
| OMAP3430_EN_GPIO1_MASK
|
904 OMAP3430_EN_GPT1_MASK
| OMAP3430_EN_GPT12_MASK
,
906 /* No need to write EN_IO, that is always enabled */
907 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK
|
908 OMAP3430_GRPSEL_GPT1_MASK
|
909 OMAP3430_GRPSEL_GPT12_MASK
,
910 WKUP_MOD
, OMAP3430_PM_MPUGRPSEL
);
911 /* For some reason IO doesn't generate wakeup event even if
912 * it is selected to mpu wakeup goup */
913 prm_write_mod_reg(OMAP3430_IO_EN_MASK
| OMAP3430_WKUP_EN_MASK
,
914 OCP_MOD
, OMAP3_PRM_IRQENABLE_MPU_OFFSET
);
916 /* Enable PM_WKEN to support DSS LPR */
917 prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK
,
918 OMAP3430_DSS_MOD
, PM_WKEN
);
920 /* Enable wakeups in PER */
921 prm_write_mod_reg(OMAP3430_EN_GPIO2_MASK
| OMAP3430_EN_GPIO3_MASK
|
922 OMAP3430_EN_GPIO4_MASK
| OMAP3430_EN_GPIO5_MASK
|
923 OMAP3430_EN_GPIO6_MASK
| OMAP3430_EN_UART3_MASK
|
924 OMAP3430_EN_MCBSP2_MASK
| OMAP3430_EN_MCBSP3_MASK
|
925 OMAP3430_EN_MCBSP4_MASK
,
926 OMAP3430_PER_MOD
, PM_WKEN
);
927 /* and allow them to wake up MPU */
928 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK
|
929 OMAP3430_GRPSEL_GPIO3_MASK
|
930 OMAP3430_GRPSEL_GPIO4_MASK
|
931 OMAP3430_GRPSEL_GPIO5_MASK
|
932 OMAP3430_GRPSEL_GPIO6_MASK
|
933 OMAP3430_GRPSEL_UART3_MASK
|
934 OMAP3430_GRPSEL_MCBSP2_MASK
|
935 OMAP3430_GRPSEL_MCBSP3_MASK
|
936 OMAP3430_GRPSEL_MCBSP4_MASK
,
937 OMAP3430_PER_MOD
, OMAP3430_PM_MPUGRPSEL
);
939 /* Don't attach IVA interrupts */
940 prm_write_mod_reg(0, WKUP_MOD
, OMAP3430_PM_IVAGRPSEL
);
941 prm_write_mod_reg(0, CORE_MOD
, OMAP3430_PM_IVAGRPSEL1
);
942 prm_write_mod_reg(0, CORE_MOD
, OMAP3430ES2_PM_IVAGRPSEL3
);
943 prm_write_mod_reg(0, OMAP3430_PER_MOD
, OMAP3430_PM_IVAGRPSEL
);
945 /* Clear any pending 'reset' flags */
946 prm_write_mod_reg(0xffffffff, MPU_MOD
, OMAP2_RM_RSTST
);
947 prm_write_mod_reg(0xffffffff, CORE_MOD
, OMAP2_RM_RSTST
);
948 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD
, OMAP2_RM_RSTST
);
949 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD
, OMAP2_RM_RSTST
);
950 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD
, OMAP2_RM_RSTST
);
951 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD
, OMAP2_RM_RSTST
);
952 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD
, OMAP2_RM_RSTST
);
954 /* Clear any pending PRCM interrupts */
955 prm_write_mod_reg(0, OCP_MOD
, OMAP3_PRM_IRQSTATUS_MPU_OFFSET
);
961 void omap3_pm_off_mode_enable(int enable
)
963 struct power_state
*pwrst
;
967 state
= PWRDM_POWER_OFF
;
969 state
= PWRDM_POWER_RET
;
971 #ifdef CONFIG_CPU_IDLE
972 omap3_cpuidle_update_states();
975 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
976 pwrst
->next_state
= state
;
977 set_pwrdm_state(pwrst
->pwrdm
, state
);
981 int omap3_pm_get_suspend_state(struct powerdomain
*pwrdm
)
983 struct power_state
*pwrst
;
985 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
986 if (pwrst
->pwrdm
== pwrdm
)
987 return pwrst
->next_state
;
992 int omap3_pm_set_suspend_state(struct powerdomain
*pwrdm
, int state
)
994 struct power_state
*pwrst
;
996 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
997 if (pwrst
->pwrdm
== pwrdm
) {
998 pwrst
->next_state
= state
;
1005 static int __init
pwrdms_setup(struct powerdomain
*pwrdm
, void *unused
)
1007 struct power_state
*pwrst
;
1012 pwrst
= kmalloc(sizeof(struct power_state
), GFP_ATOMIC
);
1015 pwrst
->pwrdm
= pwrdm
;
1016 pwrst
->next_state
= PWRDM_POWER_RET
;
1017 list_add(&pwrst
->node
, &pwrst_list
);
1019 if (pwrdm_has_hdwr_sar(pwrdm
))
1020 pwrdm_enable_hdwr_sar(pwrdm
);
1022 return set_pwrdm_state(pwrst
->pwrdm
, pwrst
->next_state
);
1026 * Enable hw supervised mode for all clockdomains if it's
1027 * supported. Initiate sleep transition for other clockdomains, if
1030 static int __init
clkdms_setup(struct clockdomain
*clkdm
, void *unused
)
1032 clkdm_clear_all_wkdeps(clkdm
);
1033 clkdm_clear_all_sleepdeps(clkdm
);
1035 if (clkdm
->flags
& CLKDM_CAN_ENABLE_AUTO
)
1036 omap2_clkdm_allow_idle(clkdm
);
1037 else if (clkdm
->flags
& CLKDM_CAN_FORCE_SLEEP
&&
1038 atomic_read(&clkdm
->usecount
) == 0)
1039 omap2_clkdm_sleep(clkdm
);
1043 void omap_push_sram_idle(void)
1045 _omap_sram_idle
= omap_sram_push(omap34xx_cpu_suspend
,
1046 omap34xx_cpu_suspend_sz
);
1047 if (omap_type() != OMAP2_DEVICE_TYPE_GP
)
1048 _omap_save_secure_sram
= omap_sram_push(save_secure_ram_context
,
1049 save_secure_ram_context_sz
);
1052 static int __init
omap3_pm_init(void)
1054 struct power_state
*pwrst
, *tmp
;
1055 struct clockdomain
*neon_clkdm
, *per_clkdm
, *mpu_clkdm
, *core_clkdm
;
1058 if (!cpu_is_omap34xx())
1061 printk(KERN_ERR
"Power Management for TI OMAP3.\n");
1063 /* XXX prcm_setup_regs needs to be before enabling hw
1064 * supervised mode for powerdomains */
1067 ret
= request_irq(INT_34XX_PRCM_MPU_IRQ
,
1068 (irq_handler_t
)prcm_interrupt_handler
,
1069 IRQF_DISABLED
, "prcm", NULL
);
1071 printk(KERN_ERR
"request_irq failed to register for 0x%x\n",
1072 INT_34XX_PRCM_MPU_IRQ
);
1076 ret
= pwrdm_for_each(pwrdms_setup
, NULL
);
1078 printk(KERN_ERR
"Failed to setup powerdomains\n");
1082 (void) clkdm_for_each(clkdms_setup
, NULL
);
1084 mpu_pwrdm
= pwrdm_lookup("mpu_pwrdm");
1085 if (mpu_pwrdm
== NULL
) {
1086 printk(KERN_ERR
"Failed to get mpu_pwrdm\n");
1090 neon_pwrdm
= pwrdm_lookup("neon_pwrdm");
1091 per_pwrdm
= pwrdm_lookup("per_pwrdm");
1092 core_pwrdm
= pwrdm_lookup("core_pwrdm");
1093 cam_pwrdm
= pwrdm_lookup("cam_pwrdm");
1095 neon_clkdm
= clkdm_lookup("neon_clkdm");
1096 mpu_clkdm
= clkdm_lookup("mpu_clkdm");
1097 per_clkdm
= clkdm_lookup("per_clkdm");
1098 core_clkdm
= clkdm_lookup("core_clkdm");
1100 omap_push_sram_idle();
1101 #ifdef CONFIG_SUSPEND
1102 suspend_set_ops(&omap_pm_ops
);
1103 #endif /* CONFIG_SUSPEND */
1105 pm_idle
= omap3_pm_idle
;
1108 clkdm_add_wkdep(neon_clkdm
, mpu_clkdm
);
1109 if (omap_type() != OMAP2_DEVICE_TYPE_GP
) {
1110 omap3_secure_ram_storage
=
1111 kmalloc(0x803F, GFP_KERNEL
);
1112 if (!omap3_secure_ram_storage
)
1113 printk(KERN_ERR
"Memory allocation failed when"
1114 "allocating for secure sram context\n");
1116 local_irq_disable();
1117 local_fiq_disable();
1119 omap_dma_global_context_save();
1120 omap3_save_secure_ram_context(PWRDM_POWER_ON
);
1121 omap_dma_global_context_restore();
1127 omap3_save_scratchpad_contents();
1131 free_irq(INT_34XX_PRCM_MPU_IRQ
, NULL
);
1132 list_for_each_entry_safe(pwrst
, tmp
, &pwrst_list
, node
) {
1133 list_del(&pwrst
->node
);
1139 late_initcall(omap3_pm_init
);