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OMAP3: PM: Enable system control module autoidle
[deliverable/linux.git] / arch / arm / mach-omap2 / pm34xx.c
1 /*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21 #include <linux/pm.h>
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29
30 #include <plat/sram.h>
31 #include <plat/clockdomain.h>
32 #include <plat/powerdomain.h>
33 #include <plat/control.h>
34 #include <plat/serial.h>
35 #include <plat/sdrc.h>
36 #include <plat/prcm.h>
37 #include <plat/gpmc.h>
38 #include <plat/dma.h>
39 #include <plat/dmtimer.h>
40
41 #include <asm/tlbflush.h>
42
43 #include "cm.h"
44 #include "cm-regbits-34xx.h"
45 #include "prm-regbits-34xx.h"
46
47 #include "prm.h"
48 #include "pm.h"
49 #include "sdrc.h"
50
51 /* Scratchpad offsets */
52 #define OMAP343X_TABLE_ADDRESS_OFFSET 0x31
53 #define OMAP343X_TABLE_VALUE_OFFSET 0x30
54 #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
55
56 u32 enable_off_mode;
57 u32 sleep_while_idle;
58 u32 wakeup_timer_seconds;
59
60 struct power_state {
61 struct powerdomain *pwrdm;
62 u32 next_state;
63 #ifdef CONFIG_SUSPEND
64 u32 saved_state;
65 #endif
66 struct list_head node;
67 };
68
69 static LIST_HEAD(pwrst_list);
70
71 static void (*_omap_sram_idle)(u32 *addr, int save_state);
72
73 static int (*_omap_save_secure_sram)(u32 *addr);
74
75 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
76 static struct powerdomain *core_pwrdm, *per_pwrdm;
77 static struct powerdomain *cam_pwrdm;
78
79 static inline void omap3_per_save_context(void)
80 {
81 omap_gpio_save_context();
82 }
83
84 static inline void omap3_per_restore_context(void)
85 {
86 omap_gpio_restore_context();
87 }
88
89 static void omap3_enable_io_chain(void)
90 {
91 int timeout = 0;
92
93 if (omap_rev() >= OMAP3430_REV_ES3_1) {
94 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
95 /* Do a readback to assure write has been done */
96 prm_read_mod_reg(WKUP_MOD, PM_WKEN);
97
98 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) &
99 OMAP3430_ST_IO_CHAIN)) {
100 timeout++;
101 if (timeout > 1000) {
102 printk(KERN_ERR "Wake up daisy chain "
103 "activation failed.\n");
104 return;
105 }
106 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN,
107 WKUP_MOD, PM_WKST);
108 }
109 }
110 }
111
112 static void omap3_disable_io_chain(void)
113 {
114 if (omap_rev() >= OMAP3430_REV_ES3_1)
115 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
116 }
117
118 static void omap3_core_save_context(void)
119 {
120 u32 control_padconf_off;
121
122 /* Save the padconf registers */
123 control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
124 control_padconf_off |= START_PADCONF_SAVE;
125 omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
126 /* wait for the save to complete */
127 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
128 & PADCONF_SAVE_DONE))
129 ;
130 /* Save the Interrupt controller context */
131 omap_intc_save_context();
132 /* Save the GPMC context */
133 omap3_gpmc_save_context();
134 /* Save the system control module context, padconf already save above*/
135 omap3_control_save_context();
136 omap_dma_global_context_save();
137 }
138
139 static void omap3_core_restore_context(void)
140 {
141 /* Restore the control module context, padconf restored by h/w */
142 omap3_control_restore_context();
143 /* Restore the GPMC context */
144 omap3_gpmc_restore_context();
145 /* Restore the interrupt controller context */
146 omap_intc_restore_context();
147 omap_dma_global_context_restore();
148 }
149
150 /*
151 * FIXME: This function should be called before entering off-mode after
152 * OMAP3 secure services have been accessed. Currently it is only called
153 * once during boot sequence, but this works as we are not using secure
154 * services.
155 */
156 static void omap3_save_secure_ram_context(u32 target_mpu_state)
157 {
158 u32 ret;
159
160 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
161 /*
162 * MPU next state must be set to POWER_ON temporarily,
163 * otherwise the WFI executed inside the ROM code
164 * will hang the system.
165 */
166 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
167 ret = _omap_save_secure_sram((u32 *)
168 __pa(omap3_secure_ram_storage));
169 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
170 /* Following is for error tracking, it should not happen */
171 if (ret) {
172 printk(KERN_ERR "save_secure_sram() returns %08x\n",
173 ret);
174 while (1)
175 ;
176 }
177 }
178 }
179
180 /*
181 * PRCM Interrupt Handler Helper Function
182 *
183 * The purpose of this function is to clear any wake-up events latched
184 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
185 * may occur whilst attempting to clear a PM_WKST_x register and thus
186 * set another bit in this register. A while loop is used to ensure
187 * that any peripheral wake-up events occurring while attempting to
188 * clear the PM_WKST_x are detected and cleared.
189 */
190 static int prcm_clear_mod_irqs(s16 module, u8 regs)
191 {
192 u32 wkst, fclk, iclk, clken;
193 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
194 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
195 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
196 u16 grpsel_off = (regs == 3) ?
197 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
198 int c = 0;
199
200 wkst = prm_read_mod_reg(module, wkst_off);
201 wkst &= prm_read_mod_reg(module, grpsel_off);
202 if (wkst) {
203 iclk = cm_read_mod_reg(module, iclk_off);
204 fclk = cm_read_mod_reg(module, fclk_off);
205 while (wkst) {
206 clken = wkst;
207 cm_set_mod_reg_bits(clken, module, iclk_off);
208 /*
209 * For USBHOST, we don't know whether HOST1 or
210 * HOST2 woke us up, so enable both f-clocks
211 */
212 if (module == OMAP3430ES2_USBHOST_MOD)
213 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
214 cm_set_mod_reg_bits(clken, module, fclk_off);
215 prm_write_mod_reg(wkst, module, wkst_off);
216 wkst = prm_read_mod_reg(module, wkst_off);
217 c++;
218 }
219 cm_write_mod_reg(iclk, module, iclk_off);
220 cm_write_mod_reg(fclk, module, fclk_off);
221 }
222
223 return c;
224 }
225
226 static int _prcm_int_handle_wakeup(void)
227 {
228 int c;
229
230 c = prcm_clear_mod_irqs(WKUP_MOD, 1);
231 c += prcm_clear_mod_irqs(CORE_MOD, 1);
232 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
233 if (omap_rev() > OMAP3430_REV_ES1_0) {
234 c += prcm_clear_mod_irqs(CORE_MOD, 3);
235 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
236 }
237
238 return c;
239 }
240
241 /*
242 * PRCM Interrupt Handler
243 *
244 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
245 * interrupts from the PRCM for the MPU. These bits must be cleared in
246 * order to clear the PRCM interrupt. The PRCM interrupt handler is
247 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
248 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
249 * register indicates that a wake-up event is pending for the MPU and
250 * this bit can only be cleared if the all the wake-up events latched
251 * in the various PM_WKST_x registers have been cleared. The interrupt
252 * handler is implemented using a do-while loop so that if a wake-up
253 * event occurred during the processing of the prcm interrupt handler
254 * (setting a bit in the corresponding PM_WKST_x register and thus
255 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
256 * this would be handled.
257 */
258 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
259 {
260 u32 irqstatus_mpu;
261 int c = 0;
262
263 do {
264 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
265 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
266
267 if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) {
268 c = _prcm_int_handle_wakeup();
269
270 /*
271 * Is the MPU PRCM interrupt handler racing with the
272 * IVA2 PRCM interrupt handler ?
273 */
274 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
275 "but no wakeup sources are marked\n");
276 } else {
277 /* XXX we need to expand our PRCM interrupt handler */
278 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
279 "no code to handle it (%08x)\n", irqstatus_mpu);
280 }
281
282 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
283 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
284
285 } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
286
287 return IRQ_HANDLED;
288 }
289
290 static void restore_control_register(u32 val)
291 {
292 __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
293 }
294
295 /* Function to restore the table entry that was modified for enabling MMU */
296 static void restore_table_entry(void)
297 {
298 u32 *scratchpad_address;
299 u32 previous_value, control_reg_value;
300 u32 *address;
301
302 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
303
304 /* Get address of entry that was modified */
305 address = (u32 *)__raw_readl(scratchpad_address +
306 OMAP343X_TABLE_ADDRESS_OFFSET);
307 /* Get the previous value which needs to be restored */
308 previous_value = __raw_readl(scratchpad_address +
309 OMAP343X_TABLE_VALUE_OFFSET);
310 address = __va(address);
311 *address = previous_value;
312 flush_tlb_all();
313 control_reg_value = __raw_readl(scratchpad_address
314 + OMAP343X_CONTROL_REG_VALUE_OFFSET);
315 /* This will enable caches and prediction */
316 restore_control_register(control_reg_value);
317 }
318
319 void omap_sram_idle(void)
320 {
321 /* Variable to tell what needs to be saved and restored
322 * in omap_sram_idle*/
323 /* save_state = 0 => Nothing to save and restored */
324 /* save_state = 1 => Only L1 and logic lost */
325 /* save_state = 2 => Only L2 lost */
326 /* save_state = 3 => L1, L2 and logic lost */
327 int save_state = 0;
328 int mpu_next_state = PWRDM_POWER_ON;
329 int per_next_state = PWRDM_POWER_ON;
330 int core_next_state = PWRDM_POWER_ON;
331 int core_prev_state, per_prev_state;
332 u32 sdrc_pwr = 0;
333 int per_state_modified = 0;
334
335 if (!_omap_sram_idle)
336 return;
337
338 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
339 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
340 pwrdm_clear_all_prev_pwrst(core_pwrdm);
341 pwrdm_clear_all_prev_pwrst(per_pwrdm);
342
343 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
344 switch (mpu_next_state) {
345 case PWRDM_POWER_ON:
346 case PWRDM_POWER_RET:
347 /* No need to save context */
348 save_state = 0;
349 break;
350 case PWRDM_POWER_OFF:
351 save_state = 3;
352 break;
353 default:
354 /* Invalid state */
355 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
356 return;
357 }
358 pwrdm_pre_transition();
359
360 /* NEON control */
361 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
362 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
363
364 /* PER */
365 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
366 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
367 if (per_next_state < PWRDM_POWER_ON) {
368 omap_uart_prepare_idle(2);
369 omap2_gpio_prepare_for_retention();
370 if (per_next_state == PWRDM_POWER_OFF) {
371 if (core_next_state == PWRDM_POWER_ON) {
372 per_next_state = PWRDM_POWER_RET;
373 pwrdm_set_next_pwrst(per_pwrdm, per_next_state);
374 per_state_modified = 1;
375 } else
376 omap3_per_save_context();
377 }
378 }
379
380 if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
381 omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]);
382
383 /* CORE */
384 if (core_next_state < PWRDM_POWER_ON) {
385 omap_uart_prepare_idle(0);
386 omap_uart_prepare_idle(1);
387 if (core_next_state == PWRDM_POWER_OFF) {
388 omap3_core_save_context();
389 omap3_prcm_save_context();
390 }
391 /* Enable IO-PAD and IO-CHAIN wakeups */
392 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
393 omap3_enable_io_chain();
394 }
395
396 /*
397 * On EMU/HS devices ROM code restores a SRDC value
398 * from scratchpad which has automatic self refresh on timeout
399 * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
400 * Hence store/restore the SDRC_POWER register here.
401 */
402 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
403 omap_type() != OMAP2_DEVICE_TYPE_GP &&
404 core_next_state == PWRDM_POWER_OFF)
405 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
406
407 /*
408 * omap3_arm_context is the location where ARM registers
409 * get saved. The restore path then reads from this
410 * location and restores them back.
411 */
412 _omap_sram_idle(omap3_arm_context, save_state);
413 cpu_init();
414
415 /* Restore normal SDRC POWER settings */
416 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
417 omap_type() != OMAP2_DEVICE_TYPE_GP &&
418 core_next_state == PWRDM_POWER_OFF)
419 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
420
421 /* Restore table entry modified during MMU restoration */
422 if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
423 restore_table_entry();
424
425 /* CORE */
426 if (core_next_state < PWRDM_POWER_ON) {
427 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
428 if (core_prev_state == PWRDM_POWER_OFF) {
429 omap3_core_restore_context();
430 omap3_prcm_restore_context();
431 omap3_sram_restore_context();
432 omap2_sms_restore_context();
433 }
434 omap_uart_resume_idle(0);
435 omap_uart_resume_idle(1);
436 if (core_next_state == PWRDM_POWER_OFF)
437 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF,
438 OMAP3430_GR_MOD,
439 OMAP3_PRM_VOLTCTRL_OFFSET);
440 }
441
442 /* PER */
443 if (per_next_state < PWRDM_POWER_ON) {
444 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
445 if (per_prev_state == PWRDM_POWER_OFF)
446 omap3_per_restore_context();
447 omap2_gpio_resume_after_retention();
448 omap_uart_resume_idle(2);
449 if (per_state_modified)
450 pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF);
451 }
452
453 /* Disable IO-PAD and IO-CHAIN wakeup */
454 if (core_next_state < PWRDM_POWER_ON) {
455 prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
456 omap3_disable_io_chain();
457 }
458
459 pwrdm_post_transition();
460
461 omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
462 }
463
464 int omap3_can_sleep(void)
465 {
466 if (!sleep_while_idle)
467 return 0;
468 if (!omap_uart_can_sleep())
469 return 0;
470 return 1;
471 }
472
473 /* This sets pwrdm state (other than mpu & core. Currently only ON &
474 * RET are supported. Function is assuming that clkdm doesn't have
475 * hw_sup mode enabled. */
476 int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
477 {
478 u32 cur_state;
479 int sleep_switch = 0;
480 int ret = 0;
481
482 if (pwrdm == NULL || IS_ERR(pwrdm))
483 return -EINVAL;
484
485 while (!(pwrdm->pwrsts & (1 << state))) {
486 if (state == PWRDM_POWER_OFF)
487 return ret;
488 state--;
489 }
490
491 cur_state = pwrdm_read_next_pwrst(pwrdm);
492 if (cur_state == state)
493 return ret;
494
495 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
496 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
497 sleep_switch = 1;
498 pwrdm_wait_transition(pwrdm);
499 }
500
501 ret = pwrdm_set_next_pwrst(pwrdm, state);
502 if (ret) {
503 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
504 pwrdm->name);
505 goto err;
506 }
507
508 if (sleep_switch) {
509 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
510 pwrdm_wait_transition(pwrdm);
511 pwrdm_state_switch(pwrdm);
512 }
513
514 err:
515 return ret;
516 }
517
518 static void omap3_pm_idle(void)
519 {
520 local_irq_disable();
521 local_fiq_disable();
522
523 if (!omap3_can_sleep())
524 goto out;
525
526 if (omap_irq_pending() || need_resched())
527 goto out;
528
529 omap_sram_idle();
530
531 out:
532 local_fiq_enable();
533 local_irq_enable();
534 }
535
536 #ifdef CONFIG_SUSPEND
537 static suspend_state_t suspend_state;
538
539 static void omap2_pm_wakeup_on_timer(u32 seconds)
540 {
541 u32 tick_rate, cycles;
542
543 if (!seconds)
544 return;
545
546 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
547 cycles = tick_rate * seconds;
548 omap_dm_timer_stop(gptimer_wakeup);
549 omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
550
551 pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n",
552 seconds, cycles, tick_rate);
553 }
554
555 static int omap3_pm_prepare(void)
556 {
557 disable_hlt();
558 return 0;
559 }
560
561 static int omap3_pm_suspend(void)
562 {
563 struct power_state *pwrst;
564 int state, ret = 0;
565
566 if (wakeup_timer_seconds)
567 omap2_pm_wakeup_on_timer(wakeup_timer_seconds);
568
569 /* Read current next_pwrsts */
570 list_for_each_entry(pwrst, &pwrst_list, node)
571 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
572 /* Set ones wanted by suspend */
573 list_for_each_entry(pwrst, &pwrst_list, node) {
574 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
575 goto restore;
576 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
577 goto restore;
578 }
579
580 omap_uart_prepare_suspend();
581 omap3_intc_suspend();
582
583 omap_sram_idle();
584
585 restore:
586 /* Restore next_pwrsts */
587 list_for_each_entry(pwrst, &pwrst_list, node) {
588 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
589 if (state > pwrst->next_state) {
590 printk(KERN_INFO "Powerdomain (%s) didn't enter "
591 "target state %d\n",
592 pwrst->pwrdm->name, pwrst->next_state);
593 ret = -1;
594 }
595 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
596 }
597 if (ret)
598 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
599 else
600 printk(KERN_INFO "Successfully put all powerdomains "
601 "to target state\n");
602
603 return ret;
604 }
605
606 static int omap3_pm_enter(suspend_state_t unused)
607 {
608 int ret = 0;
609
610 switch (suspend_state) {
611 case PM_SUSPEND_STANDBY:
612 case PM_SUSPEND_MEM:
613 ret = omap3_pm_suspend();
614 break;
615 default:
616 ret = -EINVAL;
617 }
618
619 return ret;
620 }
621
622 static void omap3_pm_finish(void)
623 {
624 enable_hlt();
625 }
626
627 /* Hooks to enable / disable UART interrupts during suspend */
628 static int omap3_pm_begin(suspend_state_t state)
629 {
630 suspend_state = state;
631 omap_uart_enable_irqs(0);
632 return 0;
633 }
634
635 static void omap3_pm_end(void)
636 {
637 suspend_state = PM_SUSPEND_ON;
638 omap_uart_enable_irqs(1);
639 return;
640 }
641
642 static struct platform_suspend_ops omap_pm_ops = {
643 .begin = omap3_pm_begin,
644 .end = omap3_pm_end,
645 .prepare = omap3_pm_prepare,
646 .enter = omap3_pm_enter,
647 .finish = omap3_pm_finish,
648 .valid = suspend_valid_only_mem,
649 };
650 #endif /* CONFIG_SUSPEND */
651
652
653 /**
654 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
655 * retention
656 *
657 * In cases where IVA2 is activated by bootcode, it may prevent
658 * full-chip retention or off-mode because it is not idle. This
659 * function forces the IVA2 into idle state so it can go
660 * into retention/off and thus allow full-chip retention/off.
661 *
662 **/
663 static void __init omap3_iva_idle(void)
664 {
665 /* ensure IVA2 clock is disabled */
666 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
667
668 /* if no clock activity, nothing else to do */
669 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
670 OMAP3430_CLKACTIVITY_IVA2_MASK))
671 return;
672
673 /* Reset IVA2 */
674 prm_write_mod_reg(OMAP3430_RST1_IVA2 |
675 OMAP3430_RST2_IVA2 |
676 OMAP3430_RST3_IVA2,
677 OMAP3430_IVA2_MOD, RM_RSTCTRL);
678
679 /* Enable IVA2 clock */
680 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
681 OMAP3430_IVA2_MOD, CM_FCLKEN);
682
683 /* Set IVA2 boot mode to 'idle' */
684 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
685 OMAP343X_CONTROL_IVA2_BOOTMOD);
686
687 /* Un-reset IVA2 */
688 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
689
690 /* Disable IVA2 clock */
691 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
692
693 /* Reset IVA2 */
694 prm_write_mod_reg(OMAP3430_RST1_IVA2 |
695 OMAP3430_RST2_IVA2 |
696 OMAP3430_RST3_IVA2,
697 OMAP3430_IVA2_MOD, RM_RSTCTRL);
698 }
699
700 static void __init omap3_d2d_idle(void)
701 {
702 u16 mask, padconf;
703
704 /* In a stand alone OMAP3430 where there is not a stacked
705 * modem for the D2D Idle Ack and D2D MStandby must be pulled
706 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
707 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
708 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
709 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
710 padconf |= mask;
711 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
712
713 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
714 padconf |= mask;
715 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
716
717 /* reset modem */
718 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
719 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
720 CORE_MOD, RM_RSTCTRL);
721 prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
722 }
723
724 static void __init prcm_setup_regs(void)
725 {
726 /* XXX Reset all wkdeps. This should be done when initializing
727 * powerdomains */
728 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
729 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
730 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
731 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
732 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
733 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
734 if (omap_rev() > OMAP3430_REV_ES1_0) {
735 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
736 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
737 } else
738 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
739
740 /*
741 * Enable interface clock autoidle for all modules.
742 * Note that in the long run this should be done by clockfw
743 */
744 cm_write_mod_reg(
745 OMAP3430_AUTO_MODEM |
746 OMAP3430ES2_AUTO_MMC3 |
747 OMAP3430ES2_AUTO_ICR |
748 OMAP3430_AUTO_AES2 |
749 OMAP3430_AUTO_SHA12 |
750 OMAP3430_AUTO_DES2 |
751 OMAP3430_AUTO_MMC2 |
752 OMAP3430_AUTO_MMC1 |
753 OMAP3430_AUTO_MSPRO |
754 OMAP3430_AUTO_HDQ |
755 OMAP3430_AUTO_MCSPI4 |
756 OMAP3430_AUTO_MCSPI3 |
757 OMAP3430_AUTO_MCSPI2 |
758 OMAP3430_AUTO_MCSPI1 |
759 OMAP3430_AUTO_I2C3 |
760 OMAP3430_AUTO_I2C2 |
761 OMAP3430_AUTO_I2C1 |
762 OMAP3430_AUTO_UART2 |
763 OMAP3430_AUTO_UART1 |
764 OMAP3430_AUTO_GPT11 |
765 OMAP3430_AUTO_GPT10 |
766 OMAP3430_AUTO_MCBSP5 |
767 OMAP3430_AUTO_MCBSP1 |
768 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
769 OMAP3430_AUTO_MAILBOXES |
770 OMAP3430_AUTO_OMAPCTRL |
771 OMAP3430ES1_AUTO_FSHOSTUSB |
772 OMAP3430_AUTO_HSOTGUSB |
773 OMAP3430_AUTO_SAD2D |
774 OMAP3430_AUTO_SSI,
775 CORE_MOD, CM_AUTOIDLE1);
776
777 cm_write_mod_reg(
778 OMAP3430_AUTO_PKA |
779 OMAP3430_AUTO_AES1 |
780 OMAP3430_AUTO_RNG |
781 OMAP3430_AUTO_SHA11 |
782 OMAP3430_AUTO_DES1,
783 CORE_MOD, CM_AUTOIDLE2);
784
785 if (omap_rev() > OMAP3430_REV_ES1_0) {
786 cm_write_mod_reg(
787 OMAP3430_AUTO_MAD2D |
788 OMAP3430ES2_AUTO_USBTLL,
789 CORE_MOD, CM_AUTOIDLE3);
790 }
791
792 cm_write_mod_reg(
793 OMAP3430_AUTO_WDT2 |
794 OMAP3430_AUTO_WDT1 |
795 OMAP3430_AUTO_GPIO1 |
796 OMAP3430_AUTO_32KSYNC |
797 OMAP3430_AUTO_GPT12 |
798 OMAP3430_AUTO_GPT1 ,
799 WKUP_MOD, CM_AUTOIDLE);
800
801 cm_write_mod_reg(
802 OMAP3430_AUTO_DSS,
803 OMAP3430_DSS_MOD,
804 CM_AUTOIDLE);
805
806 cm_write_mod_reg(
807 OMAP3430_AUTO_CAM,
808 OMAP3430_CAM_MOD,
809 CM_AUTOIDLE);
810
811 cm_write_mod_reg(
812 OMAP3430_AUTO_GPIO6 |
813 OMAP3430_AUTO_GPIO5 |
814 OMAP3430_AUTO_GPIO4 |
815 OMAP3430_AUTO_GPIO3 |
816 OMAP3430_AUTO_GPIO2 |
817 OMAP3430_AUTO_WDT3 |
818 OMAP3430_AUTO_UART3 |
819 OMAP3430_AUTO_GPT9 |
820 OMAP3430_AUTO_GPT8 |
821 OMAP3430_AUTO_GPT7 |
822 OMAP3430_AUTO_GPT6 |
823 OMAP3430_AUTO_GPT5 |
824 OMAP3430_AUTO_GPT4 |
825 OMAP3430_AUTO_GPT3 |
826 OMAP3430_AUTO_GPT2 |
827 OMAP3430_AUTO_MCBSP4 |
828 OMAP3430_AUTO_MCBSP3 |
829 OMAP3430_AUTO_MCBSP2,
830 OMAP3430_PER_MOD,
831 CM_AUTOIDLE);
832
833 if (omap_rev() > OMAP3430_REV_ES1_0) {
834 cm_write_mod_reg(
835 OMAP3430ES2_AUTO_USBHOST,
836 OMAP3430ES2_USBHOST_MOD,
837 CM_AUTOIDLE);
838 }
839
840 omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG);
841
842 /*
843 * Set all plls to autoidle. This is needed until autoidle is
844 * enabled by clockfw
845 */
846 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
847 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
848 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
849 MPU_MOD,
850 CM_AUTOIDLE2);
851 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
852 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
853 PLL_MOD,
854 CM_AUTOIDLE);
855 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
856 PLL_MOD,
857 CM_AUTOIDLE2);
858
859 /*
860 * Enable control of expternal oscillator through
861 * sys_clkreq. In the long run clock framework should
862 * take care of this.
863 */
864 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
865 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
866 OMAP3430_GR_MOD,
867 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
868
869 /* setup wakup source */
870 prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
871 OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
872 WKUP_MOD, PM_WKEN);
873 /* No need to write EN_IO, that is always enabled */
874 prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
875 OMAP3430_EN_GPT12,
876 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
877 /* For some reason IO doesn't generate wakeup event even if
878 * it is selected to mpu wakeup goup */
879 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
880 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
881
882 /* Enable wakeups in PER */
883 prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
884 OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
885 OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3,
886 OMAP3430_PER_MOD, PM_WKEN);
887 /* and allow them to wake up MPU */
888 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
889 OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
890 OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3,
891 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
892
893 /* Don't attach IVA interrupts */
894 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
895 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
896 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
897 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
898
899 /* Clear any pending 'reset' flags */
900 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
901 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
902 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
903 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
904 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
905 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
906 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
907
908 /* Clear any pending PRCM interrupts */
909 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
910
911 /* Don't attach IVA interrupts */
912 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
913 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
914 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
915 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
916
917 /* Clear any pending 'reset' flags */
918 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
919 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
920 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
921 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
922 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
923 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
924 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
925
926 /* Clear any pending PRCM interrupts */
927 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
928
929 omap3_iva_idle();
930 omap3_d2d_idle();
931 }
932
933 void omap3_pm_off_mode_enable(int enable)
934 {
935 struct power_state *pwrst;
936 u32 state;
937
938 if (enable)
939 state = PWRDM_POWER_OFF;
940 else
941 state = PWRDM_POWER_RET;
942
943 list_for_each_entry(pwrst, &pwrst_list, node) {
944 pwrst->next_state = state;
945 set_pwrdm_state(pwrst->pwrdm, state);
946 }
947 }
948
949 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
950 {
951 struct power_state *pwrst;
952
953 list_for_each_entry(pwrst, &pwrst_list, node) {
954 if (pwrst->pwrdm == pwrdm)
955 return pwrst->next_state;
956 }
957 return -EINVAL;
958 }
959
960 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
961 {
962 struct power_state *pwrst;
963
964 list_for_each_entry(pwrst, &pwrst_list, node) {
965 if (pwrst->pwrdm == pwrdm) {
966 pwrst->next_state = state;
967 return 0;
968 }
969 }
970 return -EINVAL;
971 }
972
973 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
974 {
975 struct power_state *pwrst;
976
977 if (!pwrdm->pwrsts)
978 return 0;
979
980 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
981 if (!pwrst)
982 return -ENOMEM;
983 pwrst->pwrdm = pwrdm;
984 pwrst->next_state = PWRDM_POWER_RET;
985 list_add(&pwrst->node, &pwrst_list);
986
987 if (pwrdm_has_hdwr_sar(pwrdm))
988 pwrdm_enable_hdwr_sar(pwrdm);
989
990 return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
991 }
992
993 /*
994 * Enable hw supervised mode for all clockdomains if it's
995 * supported. Initiate sleep transition for other clockdomains, if
996 * they are not used
997 */
998 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
999 {
1000 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
1001 omap2_clkdm_allow_idle(clkdm);
1002 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
1003 atomic_read(&clkdm->usecount) == 0)
1004 omap2_clkdm_sleep(clkdm);
1005 return 0;
1006 }
1007
1008 void omap_push_sram_idle(void)
1009 {
1010 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
1011 omap34xx_cpu_suspend_sz);
1012 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
1013 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
1014 save_secure_ram_context_sz);
1015 }
1016
1017 static int __init omap3_pm_init(void)
1018 {
1019 struct power_state *pwrst, *tmp;
1020 int ret;
1021
1022 if (!cpu_is_omap34xx())
1023 return -ENODEV;
1024
1025 printk(KERN_ERR "Power Management for TI OMAP3.\n");
1026
1027 /* XXX prcm_setup_regs needs to be before enabling hw
1028 * supervised mode for powerdomains */
1029 prcm_setup_regs();
1030
1031 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
1032 (irq_handler_t)prcm_interrupt_handler,
1033 IRQF_DISABLED, "prcm", NULL);
1034 if (ret) {
1035 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
1036 INT_34XX_PRCM_MPU_IRQ);
1037 goto err1;
1038 }
1039
1040 ret = pwrdm_for_each(pwrdms_setup, NULL);
1041 if (ret) {
1042 printk(KERN_ERR "Failed to setup powerdomains\n");
1043 goto err2;
1044 }
1045
1046 (void) clkdm_for_each(clkdms_setup, NULL);
1047
1048 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
1049 if (mpu_pwrdm == NULL) {
1050 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
1051 goto err2;
1052 }
1053
1054 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
1055 per_pwrdm = pwrdm_lookup("per_pwrdm");
1056 core_pwrdm = pwrdm_lookup("core_pwrdm");
1057 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
1058
1059 omap_push_sram_idle();
1060 #ifdef CONFIG_SUSPEND
1061 suspend_set_ops(&omap_pm_ops);
1062 #endif /* CONFIG_SUSPEND */
1063
1064 pm_idle = omap3_pm_idle;
1065 omap3_idle_init();
1066
1067 pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
1068 /*
1069 * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
1070 * IO-pad wakeup. Otherwise it will unnecessarily waste power
1071 * waking up PER with every CORE wakeup - see
1072 * http://marc.info/?l=linux-omap&m=121852150710062&w=2
1073 */
1074 pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
1075
1076 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1077 omap3_secure_ram_storage =
1078 kmalloc(0x803F, GFP_KERNEL);
1079 if (!omap3_secure_ram_storage)
1080 printk(KERN_ERR "Memory allocation failed when"
1081 "allocating for secure sram context\n");
1082
1083 local_irq_disable();
1084 local_fiq_disable();
1085
1086 omap_dma_global_context_save();
1087 omap3_save_secure_ram_context(PWRDM_POWER_ON);
1088 omap_dma_global_context_restore();
1089
1090 local_irq_enable();
1091 local_fiq_enable();
1092 }
1093
1094 omap3_save_scratchpad_contents();
1095 err1:
1096 return ret;
1097 err2:
1098 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
1099 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
1100 list_del(&pwrst->node);
1101 kfree(pwrst);
1102 }
1103 return ret;
1104 }
1105
1106 late_initcall(omap3_pm_init);
Linux kernel - Deliverables
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