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Merge branch 'for-2.6.36' of git://linux-nfs.org/~bfields/linux
[deliverable/linux.git] / arch / arm / mach-omap2 / pm34xx.c
1 /*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21 #include <linux/pm.h>
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
31
32 #include <plat/sram.h>
33 #include <plat/clockdomain.h>
34 #include <plat/powerdomain.h>
35 #include <plat/control.h>
36 #include <plat/serial.h>
37 #include <plat/sdrc.h>
38 #include <plat/prcm.h>
39 #include <plat/gpmc.h>
40 #include <plat/dma.h>
41 #include <plat/dmtimer.h>
42
43 #include <asm/tlbflush.h>
44
45 #include "cm.h"
46 #include "cm-regbits-34xx.h"
47 #include "prm-regbits-34xx.h"
48
49 #include "prm.h"
50 #include "pm.h"
51 #include "sdrc.h"
52
53 /* Scratchpad offsets */
54 #define OMAP343X_TABLE_ADDRESS_OFFSET 0x31
55 #define OMAP343X_TABLE_VALUE_OFFSET 0x30
56 #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
57
58 u32 enable_off_mode;
59 u32 sleep_while_idle;
60 u32 wakeup_timer_seconds;
61 u32 wakeup_timer_milliseconds;
62
63 struct power_state {
64 struct powerdomain *pwrdm;
65 u32 next_state;
66 #ifdef CONFIG_SUSPEND
67 u32 saved_state;
68 #endif
69 struct list_head node;
70 };
71
72 static LIST_HEAD(pwrst_list);
73
74 static void (*_omap_sram_idle)(u32 *addr, int save_state);
75
76 static int (*_omap_save_secure_sram)(u32 *addr);
77
78 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
79 static struct powerdomain *core_pwrdm, *per_pwrdm;
80 static struct powerdomain *cam_pwrdm;
81
82 static inline void omap3_per_save_context(void)
83 {
84 omap_gpio_save_context();
85 }
86
87 static inline void omap3_per_restore_context(void)
88 {
89 omap_gpio_restore_context();
90 }
91
92 static void omap3_enable_io_chain(void)
93 {
94 int timeout = 0;
95
96 if (omap_rev() >= OMAP3430_REV_ES3_1) {
97 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
98 PM_WKEN);
99 /* Do a readback to assure write has been done */
100 prm_read_mod_reg(WKUP_MOD, PM_WKEN);
101
102 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
103 OMAP3430_ST_IO_CHAIN_MASK)) {
104 timeout++;
105 if (timeout > 1000) {
106 printk(KERN_ERR "Wake up daisy chain "
107 "activation failed.\n");
108 return;
109 }
110 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
111 WKUP_MOD, PM_WKEN);
112 }
113 }
114 }
115
116 static void omap3_disable_io_chain(void)
117 {
118 if (omap_rev() >= OMAP3430_REV_ES3_1)
119 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
120 PM_WKEN);
121 }
122
123 static void omap3_core_save_context(void)
124 {
125 u32 control_padconf_off;
126
127 /* Save the padconf registers */
128 control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
129 control_padconf_off |= START_PADCONF_SAVE;
130 omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
131 /* wait for the save to complete */
132 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
133 & PADCONF_SAVE_DONE))
134 udelay(1);
135
136 /*
137 * Force write last pad into memory, as this can fail in some
138 * cases according to erratas 1.157, 1.185
139 */
140 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
141 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
142
143 /* Save the Interrupt controller context */
144 omap_intc_save_context();
145 /* Save the GPMC context */
146 omap3_gpmc_save_context();
147 /* Save the system control module context, padconf already save above*/
148 omap3_control_save_context();
149 omap_dma_global_context_save();
150 }
151
152 static void omap3_core_restore_context(void)
153 {
154 /* Restore the control module context, padconf restored by h/w */
155 omap3_control_restore_context();
156 /* Restore the GPMC context */
157 omap3_gpmc_restore_context();
158 /* Restore the interrupt controller context */
159 omap_intc_restore_context();
160 omap_dma_global_context_restore();
161 }
162
163 /*
164 * FIXME: This function should be called before entering off-mode after
165 * OMAP3 secure services have been accessed. Currently it is only called
166 * once during boot sequence, but this works as we are not using secure
167 * services.
168 */
169 static void omap3_save_secure_ram_context(u32 target_mpu_state)
170 {
171 u32 ret;
172
173 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
174 /*
175 * MPU next state must be set to POWER_ON temporarily,
176 * otherwise the WFI executed inside the ROM code
177 * will hang the system.
178 */
179 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
180 ret = _omap_save_secure_sram((u32 *)
181 __pa(omap3_secure_ram_storage));
182 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
183 /* Following is for error tracking, it should not happen */
184 if (ret) {
185 printk(KERN_ERR "save_secure_sram() returns %08x\n",
186 ret);
187 while (1)
188 ;
189 }
190 }
191 }
192
193 /*
194 * PRCM Interrupt Handler Helper Function
195 *
196 * The purpose of this function is to clear any wake-up events latched
197 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
198 * may occur whilst attempting to clear a PM_WKST_x register and thus
199 * set another bit in this register. A while loop is used to ensure
200 * that any peripheral wake-up events occurring while attempting to
201 * clear the PM_WKST_x are detected and cleared.
202 */
203 static int prcm_clear_mod_irqs(s16 module, u8 regs)
204 {
205 u32 wkst, fclk, iclk, clken;
206 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
207 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
208 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
209 u16 grpsel_off = (regs == 3) ?
210 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
211 int c = 0;
212
213 wkst = prm_read_mod_reg(module, wkst_off);
214 wkst &= prm_read_mod_reg(module, grpsel_off);
215 if (wkst) {
216 iclk = cm_read_mod_reg(module, iclk_off);
217 fclk = cm_read_mod_reg(module, fclk_off);
218 while (wkst) {
219 clken = wkst;
220 cm_set_mod_reg_bits(clken, module, iclk_off);
221 /*
222 * For USBHOST, we don't know whether HOST1 or
223 * HOST2 woke us up, so enable both f-clocks
224 */
225 if (module == OMAP3430ES2_USBHOST_MOD)
226 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
227 cm_set_mod_reg_bits(clken, module, fclk_off);
228 prm_write_mod_reg(wkst, module, wkst_off);
229 wkst = prm_read_mod_reg(module, wkst_off);
230 c++;
231 }
232 cm_write_mod_reg(iclk, module, iclk_off);
233 cm_write_mod_reg(fclk, module, fclk_off);
234 }
235
236 return c;
237 }
238
239 static int _prcm_int_handle_wakeup(void)
240 {
241 int c;
242
243 c = prcm_clear_mod_irqs(WKUP_MOD, 1);
244 c += prcm_clear_mod_irqs(CORE_MOD, 1);
245 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
246 if (omap_rev() > OMAP3430_REV_ES1_0) {
247 c += prcm_clear_mod_irqs(CORE_MOD, 3);
248 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
249 }
250
251 return c;
252 }
253
254 /*
255 * PRCM Interrupt Handler
256 *
257 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
258 * interrupts from the PRCM for the MPU. These bits must be cleared in
259 * order to clear the PRCM interrupt. The PRCM interrupt handler is
260 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
261 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
262 * register indicates that a wake-up event is pending for the MPU and
263 * this bit can only be cleared if the all the wake-up events latched
264 * in the various PM_WKST_x registers have been cleared. The interrupt
265 * handler is implemented using a do-while loop so that if a wake-up
266 * event occurred during the processing of the prcm interrupt handler
267 * (setting a bit in the corresponding PM_WKST_x register and thus
268 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
269 * this would be handled.
270 */
271 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
272 {
273 u32 irqenable_mpu, irqstatus_mpu;
274 int c = 0;
275
276 irqenable_mpu = prm_read_mod_reg(OCP_MOD,
277 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
278 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
279 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
280 irqstatus_mpu &= irqenable_mpu;
281
282 do {
283 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
284 OMAP3430_IO_ST_MASK)) {
285 c = _prcm_int_handle_wakeup();
286
287 /*
288 * Is the MPU PRCM interrupt handler racing with the
289 * IVA2 PRCM interrupt handler ?
290 */
291 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
292 "but no wakeup sources are marked\n");
293 } else {
294 /* XXX we need to expand our PRCM interrupt handler */
295 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
296 "no code to handle it (%08x)\n", irqstatus_mpu);
297 }
298
299 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
300 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
301
302 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
303 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
304 irqstatus_mpu &= irqenable_mpu;
305
306 } while (irqstatus_mpu);
307
308 return IRQ_HANDLED;
309 }
310
311 static void restore_control_register(u32 val)
312 {
313 __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
314 }
315
316 /* Function to restore the table entry that was modified for enabling MMU */
317 static void restore_table_entry(void)
318 {
319 u32 *scratchpad_address;
320 u32 previous_value, control_reg_value;
321 u32 *address;
322
323 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
324
325 /* Get address of entry that was modified */
326 address = (u32 *)__raw_readl(scratchpad_address +
327 OMAP343X_TABLE_ADDRESS_OFFSET);
328 /* Get the previous value which needs to be restored */
329 previous_value = __raw_readl(scratchpad_address +
330 OMAP343X_TABLE_VALUE_OFFSET);
331 address = __va(address);
332 *address = previous_value;
333 flush_tlb_all();
334 control_reg_value = __raw_readl(scratchpad_address
335 + OMAP343X_CONTROL_REG_VALUE_OFFSET);
336 /* This will enable caches and prediction */
337 restore_control_register(control_reg_value);
338 }
339
340 void omap_sram_idle(void)
341 {
342 /* Variable to tell what needs to be saved and restored
343 * in omap_sram_idle*/
344 /* save_state = 0 => Nothing to save and restored */
345 /* save_state = 1 => Only L1 and logic lost */
346 /* save_state = 2 => Only L2 lost */
347 /* save_state = 3 => L1, L2 and logic lost */
348 int save_state = 0;
349 int mpu_next_state = PWRDM_POWER_ON;
350 int per_next_state = PWRDM_POWER_ON;
351 int core_next_state = PWRDM_POWER_ON;
352 int core_prev_state, per_prev_state;
353 u32 sdrc_pwr = 0;
354 int per_state_modified = 0;
355
356 if (!_omap_sram_idle)
357 return;
358
359 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
360 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
361 pwrdm_clear_all_prev_pwrst(core_pwrdm);
362 pwrdm_clear_all_prev_pwrst(per_pwrdm);
363
364 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
365 switch (mpu_next_state) {
366 case PWRDM_POWER_ON:
367 case PWRDM_POWER_RET:
368 /* No need to save context */
369 save_state = 0;
370 break;
371 case PWRDM_POWER_OFF:
372 save_state = 3;
373 break;
374 default:
375 /* Invalid state */
376 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
377 return;
378 }
379 pwrdm_pre_transition();
380
381 /* NEON control */
382 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
383 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
384
385 /* Enable IO-PAD and IO-CHAIN wakeups */
386 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
387 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
388 if (per_next_state < PWRDM_POWER_ON ||
389 core_next_state < PWRDM_POWER_ON) {
390 prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
391 omap3_enable_io_chain();
392 }
393
394 /* PER */
395 if (per_next_state < PWRDM_POWER_ON) {
396 omap_uart_prepare_idle(2);
397 omap2_gpio_prepare_for_idle(per_next_state);
398 if (per_next_state == PWRDM_POWER_OFF) {
399 if (core_next_state == PWRDM_POWER_ON) {
400 per_next_state = PWRDM_POWER_RET;
401 pwrdm_set_next_pwrst(per_pwrdm, per_next_state);
402 per_state_modified = 1;
403 } else
404 omap3_per_save_context();
405 }
406 }
407
408 if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
409 omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]);
410
411 /* CORE */
412 if (core_next_state < PWRDM_POWER_ON) {
413 omap_uart_prepare_idle(0);
414 omap_uart_prepare_idle(1);
415 if (core_next_state == PWRDM_POWER_OFF) {
416 omap3_core_save_context();
417 omap3_prcm_save_context();
418 }
419 }
420
421 omap3_intc_prepare_idle();
422
423 /*
424 * On EMU/HS devices ROM code restores a SRDC value
425 * from scratchpad which has automatic self refresh on timeout
426 * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
427 * Hence store/restore the SDRC_POWER register here.
428 */
429 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
430 omap_type() != OMAP2_DEVICE_TYPE_GP &&
431 core_next_state == PWRDM_POWER_OFF)
432 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
433
434 /*
435 * omap3_arm_context is the location where ARM registers
436 * get saved. The restore path then reads from this
437 * location and restores them back.
438 */
439 _omap_sram_idle(omap3_arm_context, save_state);
440 cpu_init();
441
442 /* Restore normal SDRC POWER settings */
443 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
444 omap_type() != OMAP2_DEVICE_TYPE_GP &&
445 core_next_state == PWRDM_POWER_OFF)
446 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
447
448 /* Restore table entry modified during MMU restoration */
449 if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
450 restore_table_entry();
451
452 /* CORE */
453 if (core_next_state < PWRDM_POWER_ON) {
454 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
455 if (core_prev_state == PWRDM_POWER_OFF) {
456 omap3_core_restore_context();
457 omap3_prcm_restore_context();
458 omap3_sram_restore_context();
459 omap2_sms_restore_context();
460 }
461 omap_uart_resume_idle(0);
462 omap_uart_resume_idle(1);
463 if (core_next_state == PWRDM_POWER_OFF)
464 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
465 OMAP3430_GR_MOD,
466 OMAP3_PRM_VOLTCTRL_OFFSET);
467 }
468 omap3_intc_resume_idle();
469
470 /* PER */
471 if (per_next_state < PWRDM_POWER_ON) {
472 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
473 omap2_gpio_resume_after_idle();
474 if (per_prev_state == PWRDM_POWER_OFF)
475 omap3_per_restore_context();
476 omap_uart_resume_idle(2);
477 if (per_state_modified)
478 pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF);
479 }
480
481 /* Disable IO-PAD and IO-CHAIN wakeup */
482 if (core_next_state < PWRDM_POWER_ON) {
483 prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
484 omap3_disable_io_chain();
485 }
486
487 pwrdm_post_transition();
488
489 omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
490 }
491
492 int omap3_can_sleep(void)
493 {
494 if (!sleep_while_idle)
495 return 0;
496 if (!omap_uart_can_sleep())
497 return 0;
498 return 1;
499 }
500
501 /* This sets pwrdm state (other than mpu & core. Currently only ON &
502 * RET are supported. Function is assuming that clkdm doesn't have
503 * hw_sup mode enabled. */
504 int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
505 {
506 u32 cur_state;
507 int sleep_switch = 0;
508 int ret = 0;
509
510 if (pwrdm == NULL || IS_ERR(pwrdm))
511 return -EINVAL;
512
513 while (!(pwrdm->pwrsts & (1 << state))) {
514 if (state == PWRDM_POWER_OFF)
515 return ret;
516 state--;
517 }
518
519 cur_state = pwrdm_read_next_pwrst(pwrdm);
520 if (cur_state == state)
521 return ret;
522
523 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
524 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
525 sleep_switch = 1;
526 pwrdm_wait_transition(pwrdm);
527 }
528
529 ret = pwrdm_set_next_pwrst(pwrdm, state);
530 if (ret) {
531 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
532 pwrdm->name);
533 goto err;
534 }
535
536 if (sleep_switch) {
537 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
538 pwrdm_wait_transition(pwrdm);
539 pwrdm_state_switch(pwrdm);
540 }
541
542 err:
543 return ret;
544 }
545
546 static void omap3_pm_idle(void)
547 {
548 local_irq_disable();
549 local_fiq_disable();
550
551 if (!omap3_can_sleep())
552 goto out;
553
554 if (omap_irq_pending() || need_resched())
555 goto out;
556
557 omap_sram_idle();
558
559 out:
560 local_fiq_enable();
561 local_irq_enable();
562 }
563
564 #ifdef CONFIG_SUSPEND
565 static suspend_state_t suspend_state;
566
567 static void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
568 {
569 u32 tick_rate, cycles;
570
571 if (!seconds && !milliseconds)
572 return;
573
574 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
575 cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
576 omap_dm_timer_stop(gptimer_wakeup);
577 omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
578
579 pr_info("PM: Resume timer in %u.%03u secs"
580 " (%d ticks at %d ticks/sec.)\n",
581 seconds, milliseconds, cycles, tick_rate);
582 }
583
584 static int omap3_pm_prepare(void)
585 {
586 disable_hlt();
587 return 0;
588 }
589
590 static int omap3_pm_suspend(void)
591 {
592 struct power_state *pwrst;
593 int state, ret = 0;
594
595 if (wakeup_timer_seconds || wakeup_timer_milliseconds)
596 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
597 wakeup_timer_milliseconds);
598
599 /* Read current next_pwrsts */
600 list_for_each_entry(pwrst, &pwrst_list, node)
601 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
602 /* Set ones wanted by suspend */
603 list_for_each_entry(pwrst, &pwrst_list, node) {
604 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
605 goto restore;
606 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
607 goto restore;
608 }
609
610 omap_uart_prepare_suspend();
611 omap3_intc_suspend();
612
613 omap_sram_idle();
614
615 restore:
616 /* Restore next_pwrsts */
617 list_for_each_entry(pwrst, &pwrst_list, node) {
618 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
619 if (state > pwrst->next_state) {
620 printk(KERN_INFO "Powerdomain (%s) didn't enter "
621 "target state %d\n",
622 pwrst->pwrdm->name, pwrst->next_state);
623 ret = -1;
624 }
625 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
626 }
627 if (ret)
628 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
629 else
630 printk(KERN_INFO "Successfully put all powerdomains "
631 "to target state\n");
632
633 return ret;
634 }
635
636 static int omap3_pm_enter(suspend_state_t unused)
637 {
638 int ret = 0;
639
640 switch (suspend_state) {
641 case PM_SUSPEND_STANDBY:
642 case PM_SUSPEND_MEM:
643 ret = omap3_pm_suspend();
644 break;
645 default:
646 ret = -EINVAL;
647 }
648
649 return ret;
650 }
651
652 static void omap3_pm_finish(void)
653 {
654 enable_hlt();
655 }
656
657 /* Hooks to enable / disable UART interrupts during suspend */
658 static int omap3_pm_begin(suspend_state_t state)
659 {
660 suspend_state = state;
661 omap_uart_enable_irqs(0);
662 return 0;
663 }
664
665 static void omap3_pm_end(void)
666 {
667 suspend_state = PM_SUSPEND_ON;
668 omap_uart_enable_irqs(1);
669 return;
670 }
671
672 static struct platform_suspend_ops omap_pm_ops = {
673 .begin = omap3_pm_begin,
674 .end = omap3_pm_end,
675 .prepare = omap3_pm_prepare,
676 .enter = omap3_pm_enter,
677 .finish = omap3_pm_finish,
678 .valid = suspend_valid_only_mem,
679 };
680 #endif /* CONFIG_SUSPEND */
681
682
683 /**
684 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
685 * retention
686 *
687 * In cases where IVA2 is activated by bootcode, it may prevent
688 * full-chip retention or off-mode because it is not idle. This
689 * function forces the IVA2 into idle state so it can go
690 * into retention/off and thus allow full-chip retention/off.
691 *
692 **/
693 static void __init omap3_iva_idle(void)
694 {
695 /* ensure IVA2 clock is disabled */
696 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
697
698 /* if no clock activity, nothing else to do */
699 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
700 OMAP3430_CLKACTIVITY_IVA2_MASK))
701 return;
702
703 /* Reset IVA2 */
704 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
705 OMAP3430_RST2_IVA2_MASK |
706 OMAP3430_RST3_IVA2_MASK,
707 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
708
709 /* Enable IVA2 clock */
710 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
711 OMAP3430_IVA2_MOD, CM_FCLKEN);
712
713 /* Set IVA2 boot mode to 'idle' */
714 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
715 OMAP343X_CONTROL_IVA2_BOOTMOD);
716
717 /* Un-reset IVA2 */
718 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
719
720 /* Disable IVA2 clock */
721 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
722
723 /* Reset IVA2 */
724 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
725 OMAP3430_RST2_IVA2_MASK |
726 OMAP3430_RST3_IVA2_MASK,
727 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
728 }
729
730 static void __init omap3_d2d_idle(void)
731 {
732 u16 mask, padconf;
733
734 /* In a stand alone OMAP3430 where there is not a stacked
735 * modem for the D2D Idle Ack and D2D MStandby must be pulled
736 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
737 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
738 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
739 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
740 padconf |= mask;
741 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
742
743 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
744 padconf |= mask;
745 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
746
747 /* reset modem */
748 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
749 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
750 CORE_MOD, OMAP2_RM_RSTCTRL);
751 prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
752 }
753
754 static void __init prcm_setup_regs(void)
755 {
756 /* XXX Reset all wkdeps. This should be done when initializing
757 * powerdomains */
758 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
759 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
760 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
761 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
762 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
763 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
764 if (omap_rev() > OMAP3430_REV_ES1_0) {
765 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
766 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
767 } else
768 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
769
770 /*
771 * Enable interface clock autoidle for all modules.
772 * Note that in the long run this should be done by clockfw
773 */
774 cm_write_mod_reg(
775 OMAP3430_AUTO_MODEM_MASK |
776 OMAP3430ES2_AUTO_MMC3_MASK |
777 OMAP3430ES2_AUTO_ICR_MASK |
778 OMAP3430_AUTO_AES2_MASK |
779 OMAP3430_AUTO_SHA12_MASK |
780 OMAP3430_AUTO_DES2_MASK |
781 OMAP3430_AUTO_MMC2_MASK |
782 OMAP3430_AUTO_MMC1_MASK |
783 OMAP3430_AUTO_MSPRO_MASK |
784 OMAP3430_AUTO_HDQ_MASK |
785 OMAP3430_AUTO_MCSPI4_MASK |
786 OMAP3430_AUTO_MCSPI3_MASK |
787 OMAP3430_AUTO_MCSPI2_MASK |
788 OMAP3430_AUTO_MCSPI1_MASK |
789 OMAP3430_AUTO_I2C3_MASK |
790 OMAP3430_AUTO_I2C2_MASK |
791 OMAP3430_AUTO_I2C1_MASK |
792 OMAP3430_AUTO_UART2_MASK |
793 OMAP3430_AUTO_UART1_MASK |
794 OMAP3430_AUTO_GPT11_MASK |
795 OMAP3430_AUTO_GPT10_MASK |
796 OMAP3430_AUTO_MCBSP5_MASK |
797 OMAP3430_AUTO_MCBSP1_MASK |
798 OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
799 OMAP3430_AUTO_MAILBOXES_MASK |
800 OMAP3430_AUTO_OMAPCTRL_MASK |
801 OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
802 OMAP3430_AUTO_HSOTGUSB_MASK |
803 OMAP3430_AUTO_SAD2D_MASK |
804 OMAP3430_AUTO_SSI_MASK,
805 CORE_MOD, CM_AUTOIDLE1);
806
807 cm_write_mod_reg(
808 OMAP3430_AUTO_PKA_MASK |
809 OMAP3430_AUTO_AES1_MASK |
810 OMAP3430_AUTO_RNG_MASK |
811 OMAP3430_AUTO_SHA11_MASK |
812 OMAP3430_AUTO_DES1_MASK,
813 CORE_MOD, CM_AUTOIDLE2);
814
815 if (omap_rev() > OMAP3430_REV_ES1_0) {
816 cm_write_mod_reg(
817 OMAP3430_AUTO_MAD2D_MASK |
818 OMAP3430ES2_AUTO_USBTLL_MASK,
819 CORE_MOD, CM_AUTOIDLE3);
820 }
821
822 cm_write_mod_reg(
823 OMAP3430_AUTO_WDT2_MASK |
824 OMAP3430_AUTO_WDT1_MASK |
825 OMAP3430_AUTO_GPIO1_MASK |
826 OMAP3430_AUTO_32KSYNC_MASK |
827 OMAP3430_AUTO_GPT12_MASK |
828 OMAP3430_AUTO_GPT1_MASK,
829 WKUP_MOD, CM_AUTOIDLE);
830
831 cm_write_mod_reg(
832 OMAP3430_AUTO_DSS_MASK,
833 OMAP3430_DSS_MOD,
834 CM_AUTOIDLE);
835
836 cm_write_mod_reg(
837 OMAP3430_AUTO_CAM_MASK,
838 OMAP3430_CAM_MOD,
839 CM_AUTOIDLE);
840
841 cm_write_mod_reg(
842 OMAP3430_AUTO_GPIO6_MASK |
843 OMAP3430_AUTO_GPIO5_MASK |
844 OMAP3430_AUTO_GPIO4_MASK |
845 OMAP3430_AUTO_GPIO3_MASK |
846 OMAP3430_AUTO_GPIO2_MASK |
847 OMAP3430_AUTO_WDT3_MASK |
848 OMAP3430_AUTO_UART3_MASK |
849 OMAP3430_AUTO_GPT9_MASK |
850 OMAP3430_AUTO_GPT8_MASK |
851 OMAP3430_AUTO_GPT7_MASK |
852 OMAP3430_AUTO_GPT6_MASK |
853 OMAP3430_AUTO_GPT5_MASK |
854 OMAP3430_AUTO_GPT4_MASK |
855 OMAP3430_AUTO_GPT3_MASK |
856 OMAP3430_AUTO_GPT2_MASK |
857 OMAP3430_AUTO_MCBSP4_MASK |
858 OMAP3430_AUTO_MCBSP3_MASK |
859 OMAP3430_AUTO_MCBSP2_MASK,
860 OMAP3430_PER_MOD,
861 CM_AUTOIDLE);
862
863 if (omap_rev() > OMAP3430_REV_ES1_0) {
864 cm_write_mod_reg(
865 OMAP3430ES2_AUTO_USBHOST_MASK,
866 OMAP3430ES2_USBHOST_MOD,
867 CM_AUTOIDLE);
868 }
869
870 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
871
872 /*
873 * Set all plls to autoidle. This is needed until autoidle is
874 * enabled by clockfw
875 */
876 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
877 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
878 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
879 MPU_MOD,
880 CM_AUTOIDLE2);
881 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
882 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
883 PLL_MOD,
884 CM_AUTOIDLE);
885 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
886 PLL_MOD,
887 CM_AUTOIDLE2);
888
889 /*
890 * Enable control of expternal oscillator through
891 * sys_clkreq. In the long run clock framework should
892 * take care of this.
893 */
894 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
895 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
896 OMAP3430_GR_MOD,
897 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
898
899 /* setup wakup source */
900 prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
901 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
902 WKUP_MOD, PM_WKEN);
903 /* No need to write EN_IO, that is always enabled */
904 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
905 OMAP3430_GRPSEL_GPT1_MASK |
906 OMAP3430_GRPSEL_GPT12_MASK,
907 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
908 /* For some reason IO doesn't generate wakeup event even if
909 * it is selected to mpu wakeup goup */
910 prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
911 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
912
913 /* Enable PM_WKEN to support DSS LPR */
914 prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
915 OMAP3430_DSS_MOD, PM_WKEN);
916
917 /* Enable wakeups in PER */
918 prm_write_mod_reg(OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
919 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
920 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
921 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
922 OMAP3430_EN_MCBSP4_MASK,
923 OMAP3430_PER_MOD, PM_WKEN);
924 /* and allow them to wake up MPU */
925 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK |
926 OMAP3430_GRPSEL_GPIO3_MASK |
927 OMAP3430_GRPSEL_GPIO4_MASK |
928 OMAP3430_GRPSEL_GPIO5_MASK |
929 OMAP3430_GRPSEL_GPIO6_MASK |
930 OMAP3430_GRPSEL_UART3_MASK |
931 OMAP3430_GRPSEL_MCBSP2_MASK |
932 OMAP3430_GRPSEL_MCBSP3_MASK |
933 OMAP3430_GRPSEL_MCBSP4_MASK,
934 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
935
936 /* Don't attach IVA interrupts */
937 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
938 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
939 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
940 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
941
942 /* Clear any pending 'reset' flags */
943 prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
944 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
945 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
946 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
947 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
948 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
949 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
950
951 /* Clear any pending PRCM interrupts */
952 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
953
954 omap3_iva_idle();
955 omap3_d2d_idle();
956 }
957
958 void omap3_pm_off_mode_enable(int enable)
959 {
960 struct power_state *pwrst;
961 u32 state;
962
963 if (enable)
964 state = PWRDM_POWER_OFF;
965 else
966 state = PWRDM_POWER_RET;
967
968 #ifdef CONFIG_CPU_IDLE
969 omap3_cpuidle_update_states();
970 #endif
971
972 list_for_each_entry(pwrst, &pwrst_list, node) {
973 pwrst->next_state = state;
974 set_pwrdm_state(pwrst->pwrdm, state);
975 }
976 }
977
978 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
979 {
980 struct power_state *pwrst;
981
982 list_for_each_entry(pwrst, &pwrst_list, node) {
983 if (pwrst->pwrdm == pwrdm)
984 return pwrst->next_state;
985 }
986 return -EINVAL;
987 }
988
989 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
990 {
991 struct power_state *pwrst;
992
993 list_for_each_entry(pwrst, &pwrst_list, node) {
994 if (pwrst->pwrdm == pwrdm) {
995 pwrst->next_state = state;
996 return 0;
997 }
998 }
999 return -EINVAL;
1000 }
1001
1002 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
1003 {
1004 struct power_state *pwrst;
1005
1006 if (!pwrdm->pwrsts)
1007 return 0;
1008
1009 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
1010 if (!pwrst)
1011 return -ENOMEM;
1012 pwrst->pwrdm = pwrdm;
1013 pwrst->next_state = PWRDM_POWER_RET;
1014 list_add(&pwrst->node, &pwrst_list);
1015
1016 if (pwrdm_has_hdwr_sar(pwrdm))
1017 pwrdm_enable_hdwr_sar(pwrdm);
1018
1019 return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
1020 }
1021
1022 /*
1023 * Enable hw supervised mode for all clockdomains if it's
1024 * supported. Initiate sleep transition for other clockdomains, if
1025 * they are not used
1026 */
1027 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
1028 {
1029 clkdm_clear_all_wkdeps(clkdm);
1030 clkdm_clear_all_sleepdeps(clkdm);
1031
1032 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
1033 omap2_clkdm_allow_idle(clkdm);
1034 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
1035 atomic_read(&clkdm->usecount) == 0)
1036 omap2_clkdm_sleep(clkdm);
1037 return 0;
1038 }
1039
1040 void omap_push_sram_idle(void)
1041 {
1042 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
1043 omap34xx_cpu_suspend_sz);
1044 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
1045 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
1046 save_secure_ram_context_sz);
1047 }
1048
1049 static int __init omap3_pm_init(void)
1050 {
1051 struct power_state *pwrst, *tmp;
1052 struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
1053 int ret;
1054
1055 if (!cpu_is_omap34xx())
1056 return -ENODEV;
1057
1058 printk(KERN_ERR "Power Management for TI OMAP3.\n");
1059
1060 /* XXX prcm_setup_regs needs to be before enabling hw
1061 * supervised mode for powerdomains */
1062 prcm_setup_regs();
1063
1064 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
1065 (irq_handler_t)prcm_interrupt_handler,
1066 IRQF_DISABLED, "prcm", NULL);
1067 if (ret) {
1068 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
1069 INT_34XX_PRCM_MPU_IRQ);
1070 goto err1;
1071 }
1072
1073 ret = pwrdm_for_each(pwrdms_setup, NULL);
1074 if (ret) {
1075 printk(KERN_ERR "Failed to setup powerdomains\n");
1076 goto err2;
1077 }
1078
1079 (void) clkdm_for_each(clkdms_setup, NULL);
1080
1081 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
1082 if (mpu_pwrdm == NULL) {
1083 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
1084 goto err2;
1085 }
1086
1087 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
1088 per_pwrdm = pwrdm_lookup("per_pwrdm");
1089 core_pwrdm = pwrdm_lookup("core_pwrdm");
1090 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
1091
1092 neon_clkdm = clkdm_lookup("neon_clkdm");
1093 mpu_clkdm = clkdm_lookup("mpu_clkdm");
1094 per_clkdm = clkdm_lookup("per_clkdm");
1095 core_clkdm = clkdm_lookup("core_clkdm");
1096
1097 omap_push_sram_idle();
1098 #ifdef CONFIG_SUSPEND
1099 suspend_set_ops(&omap_pm_ops);
1100 #endif /* CONFIG_SUSPEND */
1101
1102 pm_idle = omap3_pm_idle;
1103 omap3_idle_init();
1104
1105 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
1106 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1107 omap3_secure_ram_storage =
1108 kmalloc(0x803F, GFP_KERNEL);
1109 if (!omap3_secure_ram_storage)
1110 printk(KERN_ERR "Memory allocation failed when"
1111 "allocating for secure sram context\n");
1112
1113 local_irq_disable();
1114 local_fiq_disable();
1115
1116 omap_dma_global_context_save();
1117 omap3_save_secure_ram_context(PWRDM_POWER_ON);
1118 omap_dma_global_context_restore();
1119
1120 local_irq_enable();
1121 local_fiq_enable();
1122 }
1123
1124 omap3_save_scratchpad_contents();
1125 err1:
1126 return ret;
1127 err2:
1128 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
1129 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
1130 list_del(&pwrst->node);
1131 kfree(pwrst);
1132 }
1133 return ret;
1134 }
1135
1136 late_initcall(omap3_pm_init);
Linux kernel - Deliverables
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