arch/arm/mach-omap2/pm44xx.c

   1 /*
   2  * OMAP4+ Power Management Routines
   3  *
   4  * Copyright (C) 2010-2013 Texas Instruments, Inc.
   5  * Rajendra Nayak <rnayak@ti.com>
   6  * Santosh Shilimkar <santosh.shilimkar@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/pm.h>
  14 #include <linux/suspend.h>
  15 #include <linux/module.h>
  16 #include <linux/list.h>
  17 #include <linux/err.h>
  18 #include <linux/slab.h>
  19 #include <asm/system_misc.h>
  20
  21 #include "soc.h"
  22 #include "common.h"
  23 #include "clockdomain.h"
  24 #include "powerdomain.h"
  25 #include "pm.h"
  26
  27 u16 pm44xx_errata;
  28
  29 struct power_state {
  30         struct powerdomain *pwrdm;
  31         u32 next_state;
  32         u32 next_logic_state;
  33 #ifdef CONFIG_SUSPEND
  34         u32 saved_state;
  35         u32 saved_logic_state;
  36 #endif
  37         struct list_head node;
  38 };
  39
  40 static LIST_HEAD(pwrst_list);
  41
  42 #ifdef CONFIG_SUSPEND
  43 static int omap4_pm_suspend(void)
  44 {
  45         struct power_state *pwrst;
  46         int state, ret = 0;
  47         u32 cpu_id = smp_processor_id();
  48
  49         /* Save current powerdomain state */
  50         list_for_each_entry(pwrst, &pwrst_list, node) {
  51                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
  52                 pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
  53         }
  54
  55         /* Set targeted power domain states by suspend */
  56         list_for_each_entry(pwrst, &pwrst_list, node) {
  57                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
  58                 pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->next_logic_state);
  59         }
  60
  61         /*
  62          * For MPUSS to hit power domain retention(CSWR or OSWR),
  63          * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
  64          * since CPU power domain CSWR is not supported by hardware
  65          * Only master CPU follows suspend path. All other CPUs follow
  66          * CPU hotplug path in system wide suspend. On OMAP4, CPU power
  67          * domain CSWR is not supported by hardware.
  68          * More details can be found in OMAP4430 TRM section 4.3.4.2.
  69          */
  70         omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
  71
  72         /* Restore next powerdomain state */
  73         list_for_each_entry(pwrst, &pwrst_list, node) {
  74                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
  75                 if (state > pwrst->next_state) {
  76                         pr_info("Powerdomain (%s) didn't enter target state %d\n",
  77                                 pwrst->pwrdm->name, pwrst->next_state);
  78                         ret = -1;
  79                 }
  80                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
  81                 pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
  82         }
  83         if (ret) {
  84                 pr_crit("Could not enter target state in pm_suspend\n");
  85                 /*
  86                  * OMAP4 chip PM currently works only with certain (newer)
  87                  * versions of bootloaders. This is due to missing code in the
  88                  * kernel to properly reset and initialize some devices.
  89                  * Warn the user about the bootloader version being one of the
  90                  * possible causes.
  91                  * http://www.spinics.net/lists/arm-kernel/msg218641.html
  92                  */
  93                 pr_warn("A possible cause could be an old bootloader - try u-boot >= v2012.07\n");
  94         } else {
  95                 pr_info("Successfully put all powerdomains to target state\n");
  96         }
  97
  98         return 0;
  99 }
 100 #else
 101 #define omap4_pm_suspend NULL
 102 #endif /* CONFIG_SUSPEND */
 103
 104 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 105 {
 106         struct power_state *pwrst;
 107
 108         if (!pwrdm->pwrsts)
 109                 return 0;
 110
 111         /*
 112          * Skip CPU0 and CPU1 power domains. CPU1 is programmed
 113          * through hotplug path and CPU0 explicitly programmed
 114          * further down in the code path
 115          */
 116         if (!strncmp(pwrdm->name, "cpu", 3))
 117                 return 0;
 118
 119         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 120         if (!pwrst)
 121                 return -ENOMEM;
 122
 123         pwrst->pwrdm = pwrdm;
 124         pwrst->next_state = PWRDM_POWER_RET;
 125         pwrst->next_logic_state = PWRDM_POWER_OFF;
 126
 127         list_add(&pwrst->node, &pwrst_list);
 128
 129         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 130 }
 131
 132 /**
 133  * omap_default_idle - OMAP4 default ilde routine.'
 134  *
 135  * Implements OMAP4 memory, IO ordering requirements which can't be addressed
 136  * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and
 137  * by secondary CPU with CONFIG_CPU_IDLE.
 138  */
 139 static void omap_default_idle(void)
 140 {
 141         omap_do_wfi();
 142 }
 143
 144 /**
 145  * omap4_init_static_deps - Add OMAP4 static dependencies
 146  *
 147  * Add needed static clockdomain dependencies on OMAP4 devices.
 148  * Return: 0 on success or 'err' on failures
 149  */
 150 static inline int omap4_init_static_deps(void)
 151 {
 152         struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
 153         struct clockdomain *ducati_clkdm, *l3_2_clkdm;
 154         int ret = 0;
 155
 156         if (omap_rev() == OMAP4430_REV_ES1_0) {
 157                 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
 158                 return -ENODEV;
 159         }
 160
 161         pr_err("Power Management for TI OMAP4.\n");
 162         /*
 163          * OMAP4 chip PM currently works only with certain (newer)
 164          * versions of bootloaders. This is due to missing code in the
 165          * kernel to properly reset and initialize some devices.
 166          * http://www.spinics.net/lists/arm-kernel/msg218641.html
 167          */
 168         pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");
 169
 170         ret = pwrdm_for_each(pwrdms_setup, NULL);
 171         if (ret) {
 172                 pr_err("Failed to setup powerdomains\n");
 173                 return ret;
 174         }
 175
 176         /*
 177          * The dynamic dependency between MPUSS -> MEMIF and
 178          * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
 179          * expected. The hardware recommendation is to enable static
 180          * dependencies for these to avoid system lock ups or random crashes.
 181          * The L4 wakeup depedency is added to workaround the OCP sync hardware
 182          * BUG with 32K synctimer which lead to incorrect timer value read
 183          * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
 184          * are part of L4 wakeup clockdomain.
 185          */
 186         mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
 187         emif_clkdm = clkdm_lookup("l3_emif_clkdm");
 188         l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
 189         l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
 190         ducati_clkdm = clkdm_lookup("ducati_clkdm");
 191         if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
 192                 (!l3_2_clkdm) || (!ducati_clkdm))
 193                 return -EINVAL;
 194
 195         ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
 196         ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
 197         ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
 198         ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
 199         ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
 200         if (ret) {
 201                 pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
 202                 return -EINVAL;
 203         }
 204
 205         return ret;
 206 }
 207
 208 /**
 209  * omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
 210  *
 211  * Initializes basic stuff for power management functionality.
 212  */
 213 int __init omap4_pm_init_early(void)
 214 {
 215         if (cpu_is_omap446x())
 216                 pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
 217
 218         return 0;
 219 }
 220
 221 /**
 222  * omap4_pm_init - Init routine for OMAP4+ devices
 223  *
 224  * Initializes all powerdomain and clockdomain target states
 225  * and all PRCM settings.
 226  * Return: Returns the error code returned by called functions.
 227  */
 228 int __init omap4_pm_init(void)
 229 {
 230         int ret = 0;
 231
 232         if (omap_rev() == OMAP4430_REV_ES1_0) {
 233                 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
 234                 return -ENODEV;
 235         }
 236
 237         pr_info("Power Management for TI OMAP4+ devices.\n");
 238
 239         ret = pwrdm_for_each(pwrdms_setup, NULL);
 240         if (ret) {
 241                 pr_err("Failed to setup powerdomains.\n");
 242                 goto err2;
 243         }
 244
 245         if (cpu_is_omap44xx()) {
 246                 ret = omap4_init_static_deps();
 247                 if (ret)
 248                         goto err2;
 249         }
 250
 251         ret = omap4_mpuss_init();
 252         if (ret) {
 253                 pr_err("Failed to initialise OMAP4 MPUSS\n");
 254                 goto err2;
 255         }
 256
 257         (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
 258
 259         omap_common_suspend_init(omap4_pm_suspend);
 260
 261         /* Overwrite the default cpu_do_idle() */
 262         arm_pm_idle = omap_default_idle;
 263
 264         if (cpu_is_omap44xx())
 265                 omap4_idle_init();
 266
 267 err2:
 268         return ret;
 269 }