2 * OMAP4 Power Management Routines
4 * Copyright (C) 2010-2011 Texas Instruments, Inc.
5 * Rajendra Nayak <rnayak@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/suspend.h>
15 #include <linux/module.h>
16 #include <linux/list.h>
17 #include <linux/err.h>
18 #include <linux/slab.h>
19 #include <asm/system_misc.h>
23 #include "clockdomain.h"
24 #include "powerdomain.h"
28 struct powerdomain
*pwrdm
;
32 u32 saved_logic_state
;
34 struct list_head node
;
37 static LIST_HEAD(pwrst_list
);
40 static int omap4_pm_suspend(void)
42 struct power_state
*pwrst
;
44 u32 cpu_id
= smp_processor_id();
46 /* Save current powerdomain state */
47 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
48 pwrst
->saved_state
= pwrdm_read_next_pwrst(pwrst
->pwrdm
);
49 pwrst
->saved_logic_state
= pwrdm_read_logic_retst(pwrst
->pwrdm
);
52 /* Set targeted power domain states by suspend */
53 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
54 omap_set_pwrdm_state(pwrst
->pwrdm
, pwrst
->next_state
);
55 pwrdm_set_logic_retst(pwrst
->pwrdm
, PWRDM_POWER_OFF
);
59 * For MPUSS to hit power domain retention(CSWR or OSWR),
60 * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
61 * since CPU power domain CSWR is not supported by hardware
62 * Only master CPU follows suspend path. All other CPUs follow
63 * CPU hotplug path in system wide suspend. On OMAP4, CPU power
64 * domain CSWR is not supported by hardware.
65 * More details can be found in OMAP4430 TRM section 4.3.4.2.
67 omap4_enter_lowpower(cpu_id
, PWRDM_POWER_OFF
);
69 /* Restore next powerdomain state */
70 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
71 state
= pwrdm_read_prev_pwrst(pwrst
->pwrdm
);
72 if (state
> pwrst
->next_state
) {
73 pr_info("Powerdomain (%s) didn't enter target state %d\n",
74 pwrst
->pwrdm
->name
, pwrst
->next_state
);
77 omap_set_pwrdm_state(pwrst
->pwrdm
, pwrst
->saved_state
);
78 pwrdm_set_logic_retst(pwrst
->pwrdm
, pwrst
->saved_logic_state
);
81 pr_crit("Could not enter target state in pm_suspend\n");
83 pr_info("Successfully put all powerdomains to target state\n");
87 #endif /* CONFIG_SUSPEND */
89 static int __init
pwrdms_setup(struct powerdomain
*pwrdm
, void *unused
)
91 struct power_state
*pwrst
;
97 * Skip CPU0 and CPU1 power domains. CPU1 is programmed
98 * through hotplug path and CPU0 explicitly programmed
99 * further down in the code path
101 if (!strncmp(pwrdm
->name
, "cpu", 3))
104 pwrst
= kmalloc(sizeof(struct power_state
), GFP_ATOMIC
);
108 pwrst
->pwrdm
= pwrdm
;
109 pwrst
->next_state
= PWRDM_POWER_RET
;
110 list_add(&pwrst
->node
, &pwrst_list
);
112 return omap_set_pwrdm_state(pwrst
->pwrdm
, pwrst
->next_state
);
116 * omap_default_idle - OMAP4 default ilde routine.'
118 * Implements OMAP4 memory, IO ordering requirements which can't be addressed
119 * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
120 * by secondary CPU with CONFIG_CPUIDLE.
122 static void omap_default_idle(void)
132 * omap4_pm_init - Init routine for OMAP4 PM
134 * Initializes all powerdomain and clockdomain target states
135 * and all PRCM settings.
137 int __init
omap4_pm_init(void)
140 struct clockdomain
*emif_clkdm
, *mpuss_clkdm
, *l3_1_clkdm
, *l4wkup
;
141 struct clockdomain
*ducati_clkdm
, *l3_2_clkdm
, *l4_per_clkdm
;
143 if (omap_rev() == OMAP4430_REV_ES1_0
) {
144 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
148 pr_err("Power Management for TI OMAP4.\n");
150 ret
= pwrdm_for_each(pwrdms_setup
, NULL
);
152 pr_err("Failed to setup powerdomains\n");
157 * The dynamic dependency between MPUSS -> MEMIF and
158 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
159 * expected. The hardware recommendation is to enable static
160 * dependencies for these to avoid system lock ups or random crashes.
161 * The L4 wakeup depedency is added to workaround the OCP sync hardware
162 * BUG with 32K synctimer which lead to incorrect timer value read
163 * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
164 * are part of L4 wakeup clockdomain.
166 mpuss_clkdm
= clkdm_lookup("mpuss_clkdm");
167 emif_clkdm
= clkdm_lookup("l3_emif_clkdm");
168 l3_1_clkdm
= clkdm_lookup("l3_1_clkdm");
169 l3_2_clkdm
= clkdm_lookup("l3_2_clkdm");
170 l4_per_clkdm
= clkdm_lookup("l4_per_clkdm");
171 l4wkup
= clkdm_lookup("l4_wkup_clkdm");
172 ducati_clkdm
= clkdm_lookup("ducati_clkdm");
173 if ((!mpuss_clkdm
) || (!emif_clkdm
) || (!l3_1_clkdm
) || (!l4wkup
) ||
174 (!l3_2_clkdm
) || (!ducati_clkdm
) || (!l4_per_clkdm
))
177 ret
= clkdm_add_wkdep(mpuss_clkdm
, emif_clkdm
);
178 ret
|= clkdm_add_wkdep(mpuss_clkdm
, l3_1_clkdm
);
179 ret
|= clkdm_add_wkdep(mpuss_clkdm
, l3_2_clkdm
);
180 ret
|= clkdm_add_wkdep(mpuss_clkdm
, l4_per_clkdm
);
181 ret
|= clkdm_add_wkdep(mpuss_clkdm
, l4wkup
);
182 ret
|= clkdm_add_wkdep(ducati_clkdm
, l3_1_clkdm
);
183 ret
|= clkdm_add_wkdep(ducati_clkdm
, l3_2_clkdm
);
185 pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
189 ret
= omap4_mpuss_init();
191 pr_err("Failed to initialise OMAP4 MPUSS\n");
195 (void) clkdm_for_each(omap_pm_clkdms_setup
, NULL
);
197 #ifdef CONFIG_SUSPEND
198 omap_pm_suspend
= omap4_pm_suspend
;
201 /* Overwrite the default cpu_do_idle() */
202 arm_pm_idle
= omap_default_idle
;
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