2 * OMAP4 Power domains framework
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
7 * Abhijit Pagare (abhijitpagare@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 * Paul Walmsley (paul@pwsan.com)
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
22 #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H
23 #define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H
25 #include <plat/powerdomain.h>
27 #include "prcm-common.h"
29 #include "cm-regbits-44xx.h"
31 #include "prm-regbits-44xx.h"
33 #if defined(CONFIG_ARCH_OMAP4)
35 /* core_44xx_pwrdm: CORE power domain */
36 static struct powerdomain core_44xx_pwrdm
= {
38 .prcm_offs
= OMAP4430_PRM_CORE_MOD
,
39 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
40 .pwrsts
= PWRSTS_RET_ON
,
41 .pwrsts_logic_ret
= PWRSTS_OFF_RET
,
44 [0] = PWRDM_POWER_OFF
, /* core_nret_bank */
45 [1] = PWRSTS_OFF_RET
, /* core_ocmram */
46 [2] = PWRDM_POWER_RET
, /* core_other_bank */
47 [3] = PWRSTS_OFF_RET
, /* ducati_l2ram */
48 [4] = PWRSTS_OFF_RET
, /* ducati_unicache */
51 [0] = PWRDM_POWER_ON
, /* core_nret_bank */
52 [1] = PWRSTS_OFF_RET
, /* core_ocmram */
53 [2] = PWRDM_POWER_ON
, /* core_other_bank */
54 [3] = PWRDM_POWER_ON
, /* ducati_l2ram */
55 [4] = PWRDM_POWER_ON
, /* ducati_unicache */
57 .flags
= PWRDM_HAS_LOWPOWERSTATECHANGE
,
60 /* gfx_44xx_pwrdm: 3D accelerator power domain */
61 static struct powerdomain gfx_44xx_pwrdm
= {
63 .prcm_offs
= OMAP4430_PRM_GFX_MOD
,
64 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
65 .pwrsts
= PWRSTS_OFF_ON
,
68 [0] = PWRDM_POWER_OFF
, /* gfx_mem */
71 [0] = PWRDM_POWER_ON
, /* gfx_mem */
73 .flags
= PWRDM_HAS_LOWPOWERSTATECHANGE
,
76 /* abe_44xx_pwrdm: Audio back end power domain */
77 static struct powerdomain abe_44xx_pwrdm
= {
79 .prcm_offs
= OMAP4430_PRM_ABE_MOD
,
80 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
81 .pwrsts
= PWRSTS_OFF_RET_ON
,
82 .pwrsts_logic_ret
= PWRDM_POWER_OFF
,
85 [0] = PWRDM_POWER_RET
, /* aessmem */
86 [1] = PWRDM_POWER_OFF
, /* periphmem */
89 [0] = PWRDM_POWER_ON
, /* aessmem */
90 [1] = PWRDM_POWER_ON
, /* periphmem */
92 .flags
= PWRDM_HAS_LOWPOWERSTATECHANGE
,
95 /* dss_44xx_pwrdm: Display subsystem power domain */
96 static struct powerdomain dss_44xx_pwrdm
= {
98 .prcm_offs
= OMAP4430_PRM_DSS_MOD
,
99 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
100 .pwrsts
= PWRSTS_OFF_RET_ON
,
101 .pwrsts_logic_ret
= PWRSTS_OFF_RET
,
104 [0] = PWRDM_POWER_OFF
, /* dss_mem */
107 [0] = PWRDM_POWER_ON
, /* dss_mem */
109 .flags
= PWRDM_HAS_LOWPOWERSTATECHANGE
,
112 /* tesla_44xx_pwrdm: Tesla processor power domain */
113 static struct powerdomain tesla_44xx_pwrdm
= {
114 .name
= "tesla_pwrdm",
115 .prcm_offs
= OMAP4430_PRM_TESLA_MOD
,
116 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
117 .pwrsts
= PWRSTS_OFF_RET_ON
,
118 .pwrsts_logic_ret
= PWRSTS_OFF_RET
,
121 [0] = PWRDM_POWER_RET
, /* tesla_edma */
122 [1] = PWRSTS_OFF_RET
, /* tesla_l1 */
123 [2] = PWRSTS_OFF_RET
, /* tesla_l2 */
126 [0] = PWRDM_POWER_ON
, /* tesla_edma */
127 [1] = PWRDM_POWER_ON
, /* tesla_l1 */
128 [2] = PWRDM_POWER_ON
, /* tesla_l2 */
130 .flags
= PWRDM_HAS_LOWPOWERSTATECHANGE
,
133 /* wkup_44xx_pwrdm: Wake-up power domain */
134 static struct powerdomain wkup_44xx_pwrdm
= {
135 .name
= "wkup_pwrdm",
136 .prcm_offs
= OMAP4430_PRM_WKUP_MOD
,
137 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
141 [0] = PWRDM_POWER_OFF
, /* wkup_bank */
144 [0] = PWRDM_POWER_ON
, /* wkup_bank */
148 /* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
149 static struct powerdomain cpu0_44xx_pwrdm
= {
150 .name
= "cpu0_pwrdm",
151 .prcm_offs
= OMAP4430_PRCM_MPU_CPU0_MOD
,
152 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
153 .pwrsts
= PWRSTS_OFF_RET_ON
,
154 .pwrsts_logic_ret
= PWRSTS_OFF_RET
,
157 [0] = PWRSTS_OFF_RET
, /* cpu0_l1 */
160 [0] = PWRDM_POWER_ON
, /* cpu0_l1 */
164 /* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
165 static struct powerdomain cpu1_44xx_pwrdm
= {
166 .name
= "cpu1_pwrdm",
167 .prcm_offs
= OMAP4430_PRCM_MPU_CPU1_MOD
,
168 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
169 .pwrsts
= PWRSTS_OFF_RET_ON
,
170 .pwrsts_logic_ret
= PWRSTS_OFF_RET
,
173 [0] = PWRSTS_OFF_RET
, /* cpu1_l1 */
176 [0] = PWRDM_POWER_ON
, /* cpu1_l1 */
180 /* emu_44xx_pwrdm: Emulation power domain */
181 static struct powerdomain emu_44xx_pwrdm
= {
183 .prcm_offs
= OMAP4430_PRM_EMU_MOD
,
184 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
185 .pwrsts
= PWRSTS_OFF_ON
,
188 [0] = PWRDM_POWER_OFF
, /* emu_bank */
191 [0] = PWRDM_POWER_ON
, /* emu_bank */
195 /* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
196 static struct powerdomain mpu_44xx_pwrdm
= {
198 .prcm_offs
= OMAP4430_PRM_MPU_MOD
,
199 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
200 .pwrsts
= PWRSTS_OFF_RET_ON
,
201 .pwrsts_logic_ret
= PWRSTS_OFF_RET
,
204 [0] = PWRSTS_OFF_RET
, /* mpu_l1 */
205 [1] = PWRSTS_OFF_RET
, /* mpu_l2 */
206 [2] = PWRDM_POWER_RET
, /* mpu_ram */
209 [0] = PWRDM_POWER_ON
, /* mpu_l1 */
210 [1] = PWRDM_POWER_ON
, /* mpu_l2 */
211 [2] = PWRDM_POWER_ON
, /* mpu_ram */
215 /* ivahd_44xx_pwrdm: IVA-HD power domain */
216 static struct powerdomain ivahd_44xx_pwrdm
= {
217 .name
= "ivahd_pwrdm",
218 .prcm_offs
= OMAP4430_PRM_IVAHD_MOD
,
219 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
220 .pwrsts
= PWRSTS_OFF_RET_ON
,
221 .pwrsts_logic_ret
= PWRDM_POWER_OFF
,
224 [0] = PWRDM_POWER_OFF
, /* hwa_mem */
225 [1] = PWRSTS_OFF_RET
, /* sl2_mem */
226 [2] = PWRSTS_OFF_RET
, /* tcm1_mem */
227 [3] = PWRSTS_OFF_RET
, /* tcm2_mem */
230 [0] = PWRDM_POWER_ON
, /* hwa_mem */
231 [1] = PWRDM_POWER_ON
, /* sl2_mem */
232 [2] = PWRDM_POWER_ON
, /* tcm1_mem */
233 [3] = PWRDM_POWER_ON
, /* tcm2_mem */
235 .flags
= PWRDM_HAS_LOWPOWERSTATECHANGE
,
238 /* cam_44xx_pwrdm: Camera subsystem power domain */
239 static struct powerdomain cam_44xx_pwrdm
= {
241 .prcm_offs
= OMAP4430_PRM_CAM_MOD
,
242 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
243 .pwrsts
= PWRSTS_OFF_ON
,
246 [0] = PWRDM_POWER_OFF
, /* cam_mem */
249 [0] = PWRDM_POWER_ON
, /* cam_mem */
251 .flags
= PWRDM_HAS_LOWPOWERSTATECHANGE
,
254 /* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
255 static struct powerdomain l3init_44xx_pwrdm
= {
256 .name
= "l3init_pwrdm",
257 .prcm_offs
= OMAP4430_PRM_L3INIT_MOD
,
258 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
259 .pwrsts
= PWRSTS_OFF_RET_ON
,
260 .pwrsts_logic_ret
= PWRSTS_OFF_RET
,
263 [0] = PWRDM_POWER_OFF
, /* l3init_bank1 */
266 [0] = PWRDM_POWER_ON
, /* l3init_bank1 */
268 .flags
= PWRDM_HAS_LOWPOWERSTATECHANGE
,
271 /* l4per_44xx_pwrdm: Target peripherals power domain */
272 static struct powerdomain l4per_44xx_pwrdm
= {
273 .name
= "l4per_pwrdm",
274 .prcm_offs
= OMAP4430_PRM_L4PER_MOD
,
275 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
276 .pwrsts
= PWRSTS_OFF_RET_ON
,
277 .pwrsts_logic_ret
= PWRSTS_OFF_RET
,
280 [0] = PWRDM_POWER_OFF
, /* nonretained_bank */
281 [1] = PWRDM_POWER_RET
, /* retained_bank */
284 [0] = PWRDM_POWER_ON
, /* nonretained_bank */
285 [1] = PWRDM_POWER_ON
, /* retained_bank */
287 .flags
= PWRDM_HAS_LOWPOWERSTATECHANGE
,
291 * always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage
294 static struct powerdomain always_on_core_44xx_pwrdm
= {
295 .name
= "always_on_core_pwrdm",
296 .prcm_offs
= OMAP4430_PRM_ALWAYS_ON_MOD
,
297 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
301 /* cefuse_44xx_pwrdm: Customer efuse controller power domain */
302 static struct powerdomain cefuse_44xx_pwrdm
= {
303 .name
= "cefuse_pwrdm",
304 .prcm_offs
= OMAP4430_PRM_CEFUSE_MOD
,
305 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
306 .pwrsts
= PWRSTS_OFF_ON
,
310 * The following power domains are not under SW control