arch/arm/mach-omap2/prcm-common.h

   1 #ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
   2 #define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
   3
   4 /*
   5  * OMAP2/3 PRCM base and module definitions
   6  *
   7  * Copyright (C) 2007-2009 Texas Instruments, Inc.
   8  * Copyright (C) 2007-2009 Nokia Corporation
   9  *
  10  * Written by Paul Walmsley
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 /* Module offsets from both CM_BASE & PRM_BASE */
  18
  19 /*
  20  * Offsets that are the same on 24xx and 34xx
  21  *
  22  * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
  23  * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
  24  */
  25 #define OCP_MOD                                         0x000
  26 #define MPU_MOD                                         0x100
  27 #define CORE_MOD                                        0x200
  28 #define GFX_MOD                                         0x300
  29 #define WKUP_MOD                                        0x400
  30 #define PLL_MOD                                         0x500
  31
  32
  33 /* Chip-specific module offsets */
  34 #define OMAP24XX_GR_MOD                                 OCP_MOD
  35 #define OMAP24XX_DSP_MOD                                0x800
  36
  37 #define OMAP2430_MDM_MOD                                0xc00
  38
  39 /* IVA2 module is < base on 3430 */
  40 #define OMAP3430_IVA2_MOD                               -0x800
  41 #define OMAP3430ES2_SGX_MOD                             GFX_MOD
  42 #define OMAP3430_CCR_MOD                                PLL_MOD
  43 #define OMAP3430_DSS_MOD                                0x600
  44 #define OMAP3430_CAM_MOD                                0x700
  45 #define OMAP3430_PER_MOD                                0x800
  46 #define OMAP3430_EMU_MOD                                0x900
  47 #define OMAP3430_GR_MOD                                 0xa00
  48 #define OMAP3430_NEON_MOD                               0xb00
  49 #define OMAP3430ES2_USBHOST_MOD                         0xc00
  50
  51 /* 24XX register bits shared between CM & PRM registers */
  52
  53 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
  54 #define OMAP2420_EN_MMC_SHIFT                           26
  55 #define OMAP2420_EN_MMC_MASK                            (1 << 26)
  56 #define OMAP24XX_EN_UART2_SHIFT                         22
  57 #define OMAP24XX_EN_UART2_MASK                          (1 << 22)
  58 #define OMAP24XX_EN_UART1_SHIFT                         21
  59 #define OMAP24XX_EN_UART1_MASK                          (1 << 21)
  60 #define OMAP24XX_EN_MCSPI2_SHIFT                        18
  61 #define OMAP24XX_EN_MCSPI2_MASK                         (1 << 18)
  62 #define OMAP24XX_EN_MCSPI1_SHIFT                        17
  63 #define OMAP24XX_EN_MCSPI1_MASK                         (1 << 17)
  64 #define OMAP24XX_EN_MCBSP2_SHIFT                        16
  65 #define OMAP24XX_EN_MCBSP2_MASK                         (1 << 16)
  66 #define OMAP24XX_EN_MCBSP1_SHIFT                        15
  67 #define OMAP24XX_EN_MCBSP1_MASK                         (1 << 15)
  68 #define OMAP24XX_EN_GPT12_SHIFT                         14
  69 #define OMAP24XX_EN_GPT12_MASK                          (1 << 14)
  70 #define OMAP24XX_EN_GPT11_SHIFT                         13
  71 #define OMAP24XX_EN_GPT11_MASK                          (1 << 13)
  72 #define OMAP24XX_EN_GPT10_SHIFT                         12
  73 #define OMAP24XX_EN_GPT10_MASK                          (1 << 12)
  74 #define OMAP24XX_EN_GPT9_SHIFT                          11
  75 #define OMAP24XX_EN_GPT9_MASK                           (1 << 11)
  76 #define OMAP24XX_EN_GPT8_SHIFT                          10
  77 #define OMAP24XX_EN_GPT8_MASK                           (1 << 10)
  78 #define OMAP24XX_EN_GPT7_SHIFT                          9
  79 #define OMAP24XX_EN_GPT7_MASK                           (1 << 9)
  80 #define OMAP24XX_EN_GPT6_SHIFT                          8
  81 #define OMAP24XX_EN_GPT6_MASK                           (1 << 8)
  82 #define OMAP24XX_EN_GPT5_SHIFT                          7
  83 #define OMAP24XX_EN_GPT5_MASK                           (1 << 7)
  84 #define OMAP24XX_EN_GPT4_SHIFT                          6
  85 #define OMAP24XX_EN_GPT4_MASK                           (1 << 6)
  86 #define OMAP24XX_EN_GPT3_SHIFT                          5
  87 #define OMAP24XX_EN_GPT3_MASK                           (1 << 5)
  88 #define OMAP24XX_EN_GPT2_SHIFT                          4
  89 #define OMAP24XX_EN_GPT2_MASK                           (1 << 4)
  90 #define OMAP2420_EN_VLYNQ_SHIFT                         3
  91 #define OMAP2420_EN_VLYNQ_MASK                          (1 << 3)
  92
  93 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
  94 #define OMAP2430_EN_GPIO5_SHIFT                         10
  95 #define OMAP2430_EN_GPIO5_MASK                          (1 << 10)
  96 #define OMAP2430_EN_MCSPI3_SHIFT                        9
  97 #define OMAP2430_EN_MCSPI3_MASK                         (1 << 9)
  98 #define OMAP2430_EN_MMCHS2_SHIFT                        8
  99 #define OMAP2430_EN_MMCHS2_MASK                         (1 << 8)
 100 #define OMAP2430_EN_MMCHS1_SHIFT                        7
 101 #define OMAP2430_EN_MMCHS1_MASK                         (1 << 7)
 102 #define OMAP24XX_EN_UART3_SHIFT                         2
 103 #define OMAP24XX_EN_UART3_MASK                          (1 << 2)
 104 #define OMAP24XX_EN_USB_SHIFT                           0
 105 #define OMAP24XX_EN_USB_MASK                            (1 << 0)
 106
 107 /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
 108 #define OMAP2430_EN_MDM_INTC_SHIFT                      11
 109 #define OMAP2430_EN_MDM_INTC_MASK                       (1 << 11)
 110 #define OMAP2430_EN_USBHS_SHIFT                         6
 111 #define OMAP2430_EN_USBHS_MASK                          (1 << 6)
 112
 113 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
 114 #define OMAP2420_ST_MMC_SHIFT                           26
 115 #define OMAP2420_ST_MMC_MASK                            (1 << 26)
 116 #define OMAP24XX_ST_UART2_SHIFT                         22
 117 #define OMAP24XX_ST_UART2_MASK                          (1 << 22)
 118 #define OMAP24XX_ST_UART1_SHIFT                         21
 119 #define OMAP24XX_ST_UART1_MASK                          (1 << 21)
 120 #define OMAP24XX_ST_MCSPI2_SHIFT                        18
 121 #define OMAP24XX_ST_MCSPI2_MASK                         (1 << 18)
 122 #define OMAP24XX_ST_MCSPI1_SHIFT                        17
 123 #define OMAP24XX_ST_MCSPI1_MASK                         (1 << 17)
 124 #define OMAP24XX_ST_GPT12_SHIFT                         14
 125 #define OMAP24XX_ST_GPT12_MASK                          (1 << 14)
 126 #define OMAP24XX_ST_GPT11_SHIFT                         13
 127 #define OMAP24XX_ST_GPT11_MASK                          (1 << 13)
 128 #define OMAP24XX_ST_GPT10_SHIFT                         12
 129 #define OMAP24XX_ST_GPT10_MASK                          (1 << 12)
 130 #define OMAP24XX_ST_GPT9_SHIFT                          11
 131 #define OMAP24XX_ST_GPT9_MASK                           (1 << 11)
 132 #define OMAP24XX_ST_GPT8_SHIFT                          10
 133 #define OMAP24XX_ST_GPT8_MASK                           (1 << 10)
 134 #define OMAP24XX_ST_GPT7_SHIFT                          9
 135 #define OMAP24XX_ST_GPT7_MASK                           (1 << 9)
 136 #define OMAP24XX_ST_GPT6_SHIFT                          8
 137 #define OMAP24XX_ST_GPT6_MASK                           (1 << 8)
 138 #define OMAP24XX_ST_GPT5_SHIFT                          7
 139 #define OMAP24XX_ST_GPT5_MASK                           (1 << 7)
 140 #define OMAP24XX_ST_GPT4_SHIFT                          6
 141 #define OMAP24XX_ST_GPT4_MASK                           (1 << 6)
 142 #define OMAP24XX_ST_GPT3_SHIFT                          5
 143 #define OMAP24XX_ST_GPT3_MASK                           (1 << 5)
 144 #define OMAP24XX_ST_GPT2_SHIFT                          4
 145 #define OMAP24XX_ST_GPT2_MASK                           (1 << 4)
 146 #define OMAP2420_ST_VLYNQ_SHIFT                         3
 147 #define OMAP2420_ST_VLYNQ_MASK                          (1 << 3)
 148
 149 /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
 150 #define OMAP2430_ST_MDM_INTC_SHIFT                      11
 151 #define OMAP2430_ST_MDM_INTC_MASK                       (1 << 11)
 152 #define OMAP2430_ST_GPIO5_SHIFT                         10
 153 #define OMAP2430_ST_GPIO5_MASK                          (1 << 10)
 154 #define OMAP2430_ST_MCSPI3_SHIFT                        9
 155 #define OMAP2430_ST_MCSPI3_MASK                         (1 << 9)
 156 #define OMAP2430_ST_MMCHS2_SHIFT                        8
 157 #define OMAP2430_ST_MMCHS2_MASK                         (1 << 8)
 158 #define OMAP2430_ST_MMCHS1_SHIFT                        7
 159 #define OMAP2430_ST_MMCHS1_MASK                         (1 << 7)
 160 #define OMAP2430_ST_USBHS_SHIFT                         6
 161 #define OMAP2430_ST_USBHS_MASK                          (1 << 6)
 162 #define OMAP24XX_ST_UART3_SHIFT                         2
 163 #define OMAP24XX_ST_UART3_MASK                          (1 << 2)
 164 #define OMAP24XX_ST_USB_SHIFT                           0
 165 #define OMAP24XX_ST_USB_MASK                            (1 << 0)
 166
 167 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
 168 #define OMAP24XX_EN_GPIOS_SHIFT                         2
 169 #define OMAP24XX_EN_GPIOS_MASK                          (1 << 2)
 170 #define OMAP24XX_EN_GPT1_SHIFT                          0
 171 #define OMAP24XX_EN_GPT1_MASK                           (1 << 0)
 172
 173 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
 174 #define OMAP24XX_ST_GPIOS_SHIFT                         2
 175 #define OMAP24XX_ST_GPIOS_MASK                          (1 << 2)
 176 #define OMAP24XX_ST_GPT1_SHIFT                          0
 177 #define OMAP24XX_ST_GPT1_MASK                           (1 << 0)
 178
 179 /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
 180 #define OMAP2430_ST_MDM_SHIFT                           0
 181 #define OMAP2430_ST_MDM_MASK                            (1 << 0)
 182
 183
 184 /* 3430 register bits shared between CM & PRM registers */
 185
 186 /* CM_REVISION, PRM_REVISION shared bits */
 187 #define OMAP3430_REV_SHIFT                              0
 188 #define OMAP3430_REV_MASK                               (0xff << 0)
 189
 190 /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
 191 #define OMAP3430_AUTOIDLE_MASK                          (1 << 0)
 192
 193 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
 194 #define OMAP3430_EN_MMC2_MASK                           (1 << 25)
 195 #define OMAP3430_EN_MMC2_SHIFT                          25
 196 #define OMAP3430_EN_MMC1_MASK                           (1 << 24)
 197 #define OMAP3430_EN_MMC1_SHIFT                          24
 198 #define OMAP3430_EN_MCSPI4_MASK                         (1 << 21)
 199 #define OMAP3430_EN_MCSPI4_SHIFT                        21
 200 #define OMAP3430_EN_MCSPI3_MASK                         (1 << 20)
 201 #define OMAP3430_EN_MCSPI3_SHIFT                        20
 202 #define OMAP3430_EN_MCSPI2_MASK                         (1 << 19)
 203 #define OMAP3430_EN_MCSPI2_SHIFT                        19
 204 #define OMAP3430_EN_MCSPI1_MASK                         (1 << 18)
 205 #define OMAP3430_EN_MCSPI1_SHIFT                        18
 206 #define OMAP3430_EN_I2C3_MASK                           (1 << 17)
 207 #define OMAP3430_EN_I2C3_SHIFT                          17
 208 #define OMAP3430_EN_I2C2_MASK                           (1 << 16)
 209 #define OMAP3430_EN_I2C2_SHIFT                          16
 210 #define OMAP3430_EN_I2C1_MASK                           (1 << 15)
 211 #define OMAP3430_EN_I2C1_SHIFT                          15
 212 #define OMAP3430_EN_UART2_MASK                          (1 << 14)
 213 #define OMAP3430_EN_UART2_SHIFT                         14
 214 #define OMAP3430_EN_UART1_MASK                          (1 << 13)
 215 #define OMAP3430_EN_UART1_SHIFT                         13
 216 #define OMAP3430_EN_GPT11_MASK                          (1 << 12)
 217 #define OMAP3430_EN_GPT11_SHIFT                         12
 218 #define OMAP3430_EN_GPT10_MASK                          (1 << 11)
 219 #define OMAP3430_EN_GPT10_SHIFT                         11
 220 #define OMAP3430_EN_MCBSP5_MASK                         (1 << 10)
 221 #define OMAP3430_EN_MCBSP5_SHIFT                        10
 222 #define OMAP3430_EN_MCBSP1_MASK                         (1 << 9)
 223 #define OMAP3430_EN_MCBSP1_SHIFT                        9
 224 #define OMAP3430_EN_FSHOSTUSB_MASK                      (1 << 5)
 225 #define OMAP3430_EN_FSHOSTUSB_SHIFT                     5
 226 #define OMAP3430_EN_D2D_MASK                            (1 << 3)
 227 #define OMAP3430_EN_D2D_SHIFT                           3
 228
 229 /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
 230 #define OMAP3430_EN_HSOTGUSB_MASK                       (1 << 4)
 231 #define OMAP3430_EN_HSOTGUSB_SHIFT                      4
 232
 233 /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
 234 #define OMAP3430_ST_MMC2_SHIFT                          25
 235 #define OMAP3430_ST_MMC2_MASK                           (1 << 25)
 236 #define OMAP3430_ST_MMC1_SHIFT                          24
 237 #define OMAP3430_ST_MMC1_MASK                           (1 << 24)
 238 #define OMAP3430_ST_MCSPI4_SHIFT                        21
 239 #define OMAP3430_ST_MCSPI4_MASK                         (1 << 21)
 240 #define OMAP3430_ST_MCSPI3_SHIFT                        20
 241 #define OMAP3430_ST_MCSPI3_MASK                         (1 << 20)
 242 #define OMAP3430_ST_MCSPI2_SHIFT                        19
 243 #define OMAP3430_ST_MCSPI2_MASK                         (1 << 19)
 244 #define OMAP3430_ST_MCSPI1_SHIFT                        18
 245 #define OMAP3430_ST_MCSPI1_MASK                         (1 << 18)
 246 #define OMAP3430_ST_I2C3_SHIFT                          17
 247 #define OMAP3430_ST_I2C3_MASK                           (1 << 17)
 248 #define OMAP3430_ST_I2C2_SHIFT                          16
 249 #define OMAP3430_ST_I2C2_MASK                           (1 << 16)
 250 #define OMAP3430_ST_I2C1_SHIFT                          15
 251 #define OMAP3430_ST_I2C1_MASK                           (1 << 15)
 252 #define OMAP3430_ST_UART2_SHIFT                         14
 253 #define OMAP3430_ST_UART2_MASK                          (1 << 14)
 254 #define OMAP3430_ST_UART1_SHIFT                         13
 255 #define OMAP3430_ST_UART1_MASK                          (1 << 13)
 256 #define OMAP3430_ST_GPT11_SHIFT                         12
 257 #define OMAP3430_ST_GPT11_MASK                          (1 << 12)
 258 #define OMAP3430_ST_GPT10_SHIFT                         11
 259 #define OMAP3430_ST_GPT10_MASK                          (1 << 11)
 260 #define OMAP3430_ST_MCBSP5_SHIFT                        10
 261 #define OMAP3430_ST_MCBSP5_MASK                         (1 << 10)
 262 #define OMAP3430_ST_MCBSP1_SHIFT                        9
 263 #define OMAP3430_ST_MCBSP1_MASK                         (1 << 9)
 264 #define OMAP3430ES1_ST_FSHOSTUSB_SHIFT                  5
 265 #define OMAP3430ES1_ST_FSHOSTUSB_MASK                   (1 << 5)
 266 #define OMAP3430ES1_ST_HSOTGUSB_SHIFT                   4
 267 #define OMAP3430ES1_ST_HSOTGUSB_MASK                    (1 << 4)
 268 #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT              5
 269 #define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK               (1 << 5)
 270 #define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT             4
 271 #define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK              (1 << 4)
 272 #define OMAP3430_ST_D2D_SHIFT                           3
 273 #define OMAP3430_ST_D2D_MASK                            (1 << 3)
 274
 275 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
 276 #define OMAP3430_EN_GPIO1_MASK                          (1 << 3)
 277 #define OMAP3430_EN_GPIO1_SHIFT                         3
 278 #define OMAP3430_EN_GPT12_MASK                          (1 << 1)
 279 #define OMAP3430_EN_GPT12_SHIFT                         1
 280 #define OMAP3430_EN_GPT1_MASK                           (1 << 0)
 281 #define OMAP3430_EN_GPT1_SHIFT                          0
 282
 283 /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
 284 #define OMAP3430_EN_SR2_MASK                            (1 << 7)
 285 #define OMAP3430_EN_SR2_SHIFT                           7
 286 #define OMAP3430_EN_SR1_MASK                            (1 << 6)
 287 #define OMAP3430_EN_SR1_SHIFT                           6
 288
 289 /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
 290 #define OMAP3430_EN_GPT12_MASK                          (1 << 1)
 291 #define OMAP3430_EN_GPT12_SHIFT                         1
 292
 293 /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
 294 #define OMAP3430_ST_SR2_SHIFT                           7
 295 #define OMAP3430_ST_SR2_MASK                            (1 << 7)
 296 #define OMAP3430_ST_SR1_SHIFT                           6
 297 #define OMAP3430_ST_SR1_MASK                            (1 << 6)
 298 #define OMAP3430_ST_GPIO1_SHIFT                         3
 299 #define OMAP3430_ST_GPIO1_MASK                          (1 << 3)
 300 #define OMAP3430_ST_GPT12_SHIFT                         1
 301 #define OMAP3430_ST_GPT12_MASK                          (1 << 1)
 302 #define OMAP3430_ST_GPT1_SHIFT                          0
 303 #define OMAP3430_ST_GPT1_MASK                           (1 << 0)
 304
 305 /*
 306  * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
 307  * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
 308  * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
 309  */
 310 #define OMAP3430_EN_MPU_MASK                            (1 << 1)
 311 #define OMAP3430_EN_MPU_SHIFT                           1
 312
 313 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
 314
 315 #define OMAP3630_EN_UART4_MASK                          (1 << 18)
 316 #define OMAP3630_EN_UART4_SHIFT                         18
 317 #define OMAP3430_EN_GPIO6_MASK                          (1 << 17)
 318 #define OMAP3430_EN_GPIO6_SHIFT                         17
 319 #define OMAP3430_EN_GPIO5_MASK                          (1 << 16)
 320 #define OMAP3430_EN_GPIO5_SHIFT                         16
 321 #define OMAP3430_EN_GPIO4_MASK                          (1 << 15)
 322 #define OMAP3430_EN_GPIO4_SHIFT                         15
 323 #define OMAP3430_EN_GPIO3_MASK                          (1 << 14)
 324 #define OMAP3430_EN_GPIO3_SHIFT                         14
 325 #define OMAP3430_EN_GPIO2_MASK                          (1 << 13)
 326 #define OMAP3430_EN_GPIO2_SHIFT                         13
 327 #define OMAP3430_EN_UART3_MASK                          (1 << 11)
 328 #define OMAP3430_EN_UART3_SHIFT                         11
 329 #define OMAP3430_EN_GPT9_MASK                           (1 << 10)
 330 #define OMAP3430_EN_GPT9_SHIFT                          10
 331 #define OMAP3430_EN_GPT8_MASK                           (1 << 9)
 332 #define OMAP3430_EN_GPT8_SHIFT                          9
 333 #define OMAP3430_EN_GPT7_MASK                           (1 << 8)
 334 #define OMAP3430_EN_GPT7_SHIFT                          8
 335 #define OMAP3430_EN_GPT6_MASK                           (1 << 7)
 336 #define OMAP3430_EN_GPT6_SHIFT                          7
 337 #define OMAP3430_EN_GPT5_MASK                           (1 << 6)
 338 #define OMAP3430_EN_GPT5_SHIFT                          6
 339 #define OMAP3430_EN_GPT4_MASK                           (1 << 5)
 340 #define OMAP3430_EN_GPT4_SHIFT                          5
 341 #define OMAP3430_EN_GPT3_MASK                           (1 << 4)
 342 #define OMAP3430_EN_GPT3_SHIFT                          4
 343 #define OMAP3430_EN_GPT2_MASK                           (1 << 3)
 344 #define OMAP3430_EN_GPT2_SHIFT                          3
 345
 346 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
 347 /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
 348  * be ST_* bits instead? */
 349 #define OMAP3430_EN_MCBSP4_MASK                         (1 << 2)
 350 #define OMAP3430_EN_MCBSP4_SHIFT                        2
 351 #define OMAP3430_EN_MCBSP3_MASK                         (1 << 1)
 352 #define OMAP3430_EN_MCBSP3_SHIFT                        1
 353 #define OMAP3430_EN_MCBSP2_MASK                         (1 << 0)
 354 #define OMAP3430_EN_MCBSP2_SHIFT                        0
 355
 356 /* CM_IDLEST_PER, PM_WKST_PER shared bits */
 357 #define OMAP3630_ST_UART4_SHIFT                         18
 358 #define OMAP3630_ST_UART4_MASK                          (1 << 18)
 359 #define OMAP3430_ST_GPIO6_SHIFT                         17
 360 #define OMAP3430_ST_GPIO6_MASK                          (1 << 17)
 361 #define OMAP3430_ST_GPIO5_SHIFT                         16
 362 #define OMAP3430_ST_GPIO5_MASK                          (1 << 16)
 363 #define OMAP3430_ST_GPIO4_SHIFT                         15
 364 #define OMAP3430_ST_GPIO4_MASK                          (1 << 15)
 365 #define OMAP3430_ST_GPIO3_SHIFT                         14
 366 #define OMAP3430_ST_GPIO3_MASK                          (1 << 14)
 367 #define OMAP3430_ST_GPIO2_SHIFT                         13
 368 #define OMAP3430_ST_GPIO2_MASK                          (1 << 13)
 369 #define OMAP3430_ST_UART3_SHIFT                         11
 370 #define OMAP3430_ST_UART3_MASK                          (1 << 11)
 371 #define OMAP3430_ST_GPT9_SHIFT                          10
 372 #define OMAP3430_ST_GPT9_MASK                           (1 << 10)
 373 #define OMAP3430_ST_GPT8_SHIFT                          9
 374 #define OMAP3430_ST_GPT8_MASK                           (1 << 9)
 375 #define OMAP3430_ST_GPT7_SHIFT                          8
 376 #define OMAP3430_ST_GPT7_MASK                           (1 << 8)
 377 #define OMAP3430_ST_GPT6_SHIFT                          7
 378 #define OMAP3430_ST_GPT6_MASK                           (1 << 7)
 379 #define OMAP3430_ST_GPT5_SHIFT                          6
 380 #define OMAP3430_ST_GPT5_MASK                           (1 << 6)
 381 #define OMAP3430_ST_GPT4_SHIFT                          5
 382 #define OMAP3430_ST_GPT4_MASK                           (1 << 5)
 383 #define OMAP3430_ST_GPT3_SHIFT                          4
 384 #define OMAP3430_ST_GPT3_MASK                           (1 << 4)
 385 #define OMAP3430_ST_GPT2_SHIFT                          3
 386 #define OMAP3430_ST_GPT2_MASK                           (1 << 3)
 387
 388 /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
 389 #define OMAP3430_EN_CORE_SHIFT                          0
 390 #define OMAP3430_EN_CORE_MASK                           (1 << 0)
 391
 392
 393 /*
 394  * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
 395  * submodule to exit hardreset
 396  */
 397 #define MAX_MODULE_HARDRESET_WAIT               10000
 398
 399 # ifndef __ASSEMBLER__
 400 extern void __iomem *prm_base;
 401 extern void __iomem *cm_base;
 402 extern void __iomem *cm2_base;
 403 # endif
 404
 405 #endif
 406