arch/arm/mach-omap2/prcm.c

   1 /*
   2  * linux/arch/arm/mach-omap2/prcm.c
   3  *
   4  * OMAP 24xx Power Reset and Clock Management (PRCM) functions
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  *
   8  * Written by Tony Lindgren <tony.lindgren@nokia.com>
   9  *
  10  * Copyright (C) 2007 Texas Instruments, Inc.
  11  * Rajendra Nayak <rnayak@ti.com>
  12  *
  13  * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
  14  * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/delay.h>
  26 #include <linux/export.h>
  27
  28 #include "common.h"
  29 #include <plat/prcm.h>
  30
  31 #include "soc.h"
  32 #include "clock.h"
  33 #include "clock2xxx.h"
  34 #include "cm2xxx_3xxx.h"
  35 #include "prm2xxx_3xxx.h"
  36 #include "prm44xx.h"
  37 #include "prminst44xx.h"
  38 #include "cminst44xx.h"
  39 #include "prm-regbits-24xx.h"
  40 #include "prm-regbits-44xx.h"
  41 #include "control.h"
  42
  43 void __iomem *prm_base;
  44 void __iomem *cm_base;
  45 void __iomem *cm2_base;
  46 void __iomem *prcm_mpu_base;
  47
  48 #define MAX_MODULE_ENABLE_WAIT          100000
  49
  50 u32 omap_prcm_get_reset_sources(void)
  51 {
  52         /* XXX This presumably needs modification for 34XX */
  53         if (cpu_is_omap24xx() || cpu_is_omap34xx())
  54                 return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
  55         if (cpu_is_omap44xx())
  56                 return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
  57
  58         return 0;
  59 }
  60 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
  61
  62 /* Resets clock rates and reboots the system. Only called from system.h */
  63 void omap_prcm_restart(char mode, const char *cmd)
  64 {
  65         s16 prcm_offs = 0;
  66
  67         if (cpu_is_omap24xx()) {
  68                 omap2xxx_clk_prepare_for_reboot();
  69
  70                 prcm_offs = WKUP_MOD;
  71         } else if (cpu_is_omap34xx()) {
  72                 prcm_offs = OMAP3430_GR_MOD;
  73                 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
  74         } else if (cpu_is_omap44xx()) {
  75                 omap4_prminst_global_warm_sw_reset(); /* never returns */
  76         } else {
  77                 WARN_ON(1);
  78         }
  79
  80         /*
  81          * As per Errata i520, in some cases, user will not be able to
  82          * access DDR memory after warm-reset.
  83          * This situation occurs while the warm-reset happens during a read
  84          * access to DDR memory. In that particular condition, DDR memory
  85          * does not respond to a corrupted read command due to the warm
  86          * reset occurrence but SDRC is waiting for read completion.
  87          * SDRC is not sensitive to the warm reset, but the interconnect is
  88          * reset on the fly, thus causing a misalignment between SDRC logic,
  89          * interconnect logic and DDR memory state.
  90          * WORKAROUND:
  91          * Steps to perform before a Warm reset is trigged:
  92          * 1. enable self-refresh on idle request
  93          * 2. put SDRC in idle
  94          * 3. wait until SDRC goes to idle
  95          * 4. generate SW reset (Global SW reset)
  96          *
  97          * Steps to be performed after warm reset occurs (in bootloader):
  98          * if HW warm reset is the source, apply below steps before any
  99          * accesses to SDRAM:
 100          * 1. Reset SMS and SDRC and wait till reset is complete
 101          * 2. Re-initialize SMS, SDRC and memory
 102          *
 103          * NOTE: Above work around is required only if arch reset is implemented
 104          * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
 105          * the WA since it resets SDRC as well as part of cold reset.
 106          */
 107
 108         /* XXX should be moved to some OMAP2/3 specific code */
 109         omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
 110                                    OMAP2_RM_RSTCTRL);
 111         omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
 112 }
 113
 114 /**
 115  * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
 116  * @reg: physical address of module IDLEST register
 117  * @mask: value to mask against to determine if the module is active
 118  * @idlest: idle state indicator (0 or 1) for the clock
 119  * @name: name of the clock (for printk)
 120  *
 121  * Returns 1 if the module indicated readiness in time, or 0 if it
 122  * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
 123  *
 124  * XXX This function is deprecated.  It should be removed once the
 125  * hwmod conversion is complete.
 126  */
 127 int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
 128                                 const char *name)
 129 {
 130         int i = 0;
 131         int ena = 0;
 132
 133         if (idlest)
 134                 ena = 0;
 135         else
 136                 ena = mask;
 137
 138         /* Wait for lock */
 139         omap_test_timeout(((__raw_readl(reg) & mask) == ena),
 140                           MAX_MODULE_ENABLE_WAIT, i);
 141
 142         if (i < MAX_MODULE_ENABLE_WAIT)
 143                 pr_debug("cm: Module associated with clock %s ready after %d loops\n",
 144                          name, i);
 145         else
 146                 pr_err("cm: Module associated with clock %s didn't enable in %d tries\n",
 147                        name, MAX_MODULE_ENABLE_WAIT);
 148
 149         return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
 150 };
 151
 152 void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
 153 {
 154         if (omap2_globals->prm)
 155                 prm_base = omap2_globals->prm;
 156         if (omap2_globals->cm)
 157                 cm_base = omap2_globals->cm;
 158         if (omap2_globals->cm2)
 159                 cm2_base = omap2_globals->cm2;
 160         if (omap2_globals->prcm_mpu)
 161                 prcm_mpu_base = omap2_globals->prcm_mpu;
 162
 163         if (cpu_is_omap44xx() || soc_is_omap54xx()) {
 164                 omap_prm_base_init();
 165                 omap_cm_base_init();
 166         }
 167 }
 168
 169 /*
 170  * Stubbed functions so that common files continue to build when
 171  * custom builds are used
 172  * XXX These are temporary and should be removed at the earliest possible
 173  * opportunity
 174  */
 175 int __weak omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
 176                                         u16 clkctrl_offs)
 177 {
 178         return 0;
 179 }
 180
 181 void __weak omap4_cminst_module_enable(u8 mode, u8 part, u16 inst,
 182                                 s16 cdoffs, u16 clkctrl_offs)
 183 {
 184 }
 185
 186 void __weak omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
 187                                  u16 clkctrl_offs)
 188 {
 189 }