2 * OMAP2/3 PRM module functions
4 * Copyright (C) 2010-2011 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/err.h>
18 #include <linux/irq.h>
22 #include <plat/prcm.h>
23 #include <plat/irqs.h>
27 #include "prm2xxx_3xxx.h"
28 #include "cm2xxx_3xxx.h"
29 #include "prm-regbits-24xx.h"
30 #include "prm-regbits-34xx.h"
32 static const struct omap_prcm_irq omap3_prcm_irqs
[] = {
33 OMAP_PRCM_IRQ("wkup", 0, 0),
34 OMAP_PRCM_IRQ("io", 9, 1),
37 static struct omap_prcm_irq_setup omap3_prcm_irq_setup
= {
38 .ack
= OMAP3_PRM_IRQSTATUS_MPU_OFFSET
,
39 .mask
= OMAP3_PRM_IRQENABLE_MPU_OFFSET
,
41 .irqs
= omap3_prcm_irqs
,
42 .nr_irqs
= ARRAY_SIZE(omap3_prcm_irqs
),
43 .irq
= INT_34XX_PRCM_MPU_IRQ
,
44 .read_pending_irqs
= &omap3xxx_prm_read_pending_irqs
,
45 .ocp_barrier
= &omap3xxx_prm_ocp_barrier
,
46 .save_and_clear_irqen
= &omap3xxx_prm_save_and_clear_irqen
,
47 .restore_irqen
= &omap3xxx_prm_restore_irqen
,
50 u32
omap2_prm_read_mod_reg(s16 module
, u16 idx
)
52 return __raw_readl(prm_base
+ module
+ idx
);
55 void omap2_prm_write_mod_reg(u32 val
, s16 module
, u16 idx
)
57 __raw_writel(val
, prm_base
+ module
+ idx
);
60 /* Read-modify-write a register in a PRM module. Caller must lock */
61 u32
omap2_prm_rmw_mod_reg_bits(u32 mask
, u32 bits
, s16 module
, s16 idx
)
65 v
= omap2_prm_read_mod_reg(module
, idx
);
68 omap2_prm_write_mod_reg(v
, module
, idx
);
73 /* Read a PRM register, AND it, and shift the result down to bit 0 */
74 u32
omap2_prm_read_mod_bits_shift(s16 domain
, s16 idx
, u32 mask
)
78 v
= omap2_prm_read_mod_reg(domain
, idx
);
85 u32
omap2_prm_set_mod_reg_bits(u32 bits
, s16 module
, s16 idx
)
87 return omap2_prm_rmw_mod_reg_bits(bits
, bits
, module
, idx
);
90 u32
omap2_prm_clear_mod_reg_bits(u32 bits
, s16 module
, s16 idx
)
92 return omap2_prm_rmw_mod_reg_bits(bits
, 0x0, module
, idx
);
97 * omap2_prm_is_hardreset_asserted - read the HW reset line state of
98 * submodules contained in the hwmod module
99 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
100 * @shift: register bit shift corresponding to the reset line to check
102 * Returns 1 if the (sub)module hardreset line is currently asserted,
103 * 0 if the (sub)module hardreset line is not currently asserted, or
104 * -EINVAL if called while running on a non-OMAP2/3 chip.
106 int omap2_prm_is_hardreset_asserted(s16 prm_mod
, u8 shift
)
108 if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
111 return omap2_prm_read_mod_bits_shift(prm_mod
, OMAP2_RM_RSTCTRL
,
116 * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
117 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
118 * @shift: register bit shift corresponding to the reset line to assert
120 * Some IPs like dsp or iva contain processors that require an HW
121 * reset line to be asserted / deasserted in order to fully enable the
122 * IP. These modules may have multiple hard-reset lines that reset
123 * different 'submodules' inside the IP block. This function will
124 * place the submodule into reset. Returns 0 upon success or -EINVAL
125 * upon an argument error.
127 int omap2_prm_assert_hardreset(s16 prm_mod
, u8 shift
)
131 if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
135 omap2_prm_rmw_mod_reg_bits(mask
, mask
, prm_mod
, OMAP2_RM_RSTCTRL
);
141 * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait
142 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
143 * @rst_shift: register bit shift corresponding to the reset line to deassert
144 * @st_shift: register bit shift for the status of the deasserted submodule
146 * Some IPs like dsp or iva contain processors that require an HW
147 * reset line to be asserted / deasserted in order to fully enable the
148 * IP. These modules may have multiple hard-reset lines that reset
149 * different 'submodules' inside the IP block. This function will
150 * take the submodule out of reset and wait until the PRCM indicates
151 * that the reset has completed before returning. Returns 0 upon success or
152 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
153 * of reset, or -EBUSY if the submodule did not exit reset promptly.
155 int omap2_prm_deassert_hardreset(s16 prm_mod
, u8 rst_shift
, u8 st_shift
)
160 if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
163 rst
= 1 << rst_shift
;
166 /* Check the current status to avoid de-asserting the line twice */
167 if (omap2_prm_read_mod_bits_shift(prm_mod
, OMAP2_RM_RSTCTRL
, rst
) == 0)
170 /* Clear the reset status by writing 1 to the status bit */
171 omap2_prm_rmw_mod_reg_bits(0xffffffff, st
, prm_mod
, OMAP2_RM_RSTST
);
172 /* de-assert the reset control line */
173 omap2_prm_rmw_mod_reg_bits(rst
, 0, prm_mod
, OMAP2_RM_RSTCTRL
);
174 /* wait the status to be set */
175 omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod
, OMAP2_RM_RSTST
,
177 MAX_MODULE_HARDRESET_WAIT
, c
);
179 return (c
== MAX_MODULE_HARDRESET_WAIT
) ? -EBUSY
: 0;
185 * struct omap3_vp - OMAP3 VP register access description.
186 * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
189 u32 tranxdone_status
;
192 static struct omap3_vp omap3_vp
[] = {
193 [OMAP3_VP_VDD_MPU_ID
] = {
194 .tranxdone_status
= OMAP3430_VP1_TRANXDONE_ST_MASK
,
196 [OMAP3_VP_VDD_CORE_ID
] = {
197 .tranxdone_status
= OMAP3430_VP2_TRANXDONE_ST_MASK
,
201 #define MAX_VP_ID ARRAY_SIZE(omap3_vp);
203 u32
omap3_prm_vp_check_txdone(u8 vp_id
)
205 struct omap3_vp
*vp
= &omap3_vp
[vp_id
];
208 irqstatus
= omap2_prm_read_mod_reg(OCP_MOD
,
209 OMAP3_PRM_IRQSTATUS_MPU_OFFSET
);
210 return irqstatus
& vp
->tranxdone_status
;
213 void omap3_prm_vp_clear_txdone(u8 vp_id
)
215 struct omap3_vp
*vp
= &omap3_vp
[vp_id
];
217 omap2_prm_write_mod_reg(vp
->tranxdone_status
,
218 OCP_MOD
, OMAP3_PRM_IRQSTATUS_MPU_OFFSET
);
221 u32
omap3_prm_vcvp_read(u8 offset
)
223 return omap2_prm_read_mod_reg(OMAP3430_GR_MOD
, offset
);
226 void omap3_prm_vcvp_write(u32 val
, u8 offset
)
228 omap2_prm_write_mod_reg(val
, OMAP3430_GR_MOD
, offset
);
231 u32
omap3_prm_vcvp_rmw(u32 mask
, u32 bits
, u8 offset
)
233 return omap2_prm_rmw_mod_reg_bits(mask
, bits
, OMAP3430_GR_MOD
, offset
);
237 * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
238 * @events: ptr to a u32, preallocated by caller
240 * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
241 * MPU IRQs, and store the result into the u32 pointed to by @events.
244 void omap3xxx_prm_read_pending_irqs(unsigned long *events
)
248 /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
249 mask
= omap2_prm_read_mod_reg(OCP_MOD
, OMAP3_PRM_IRQENABLE_MPU_OFFSET
);
250 st
= omap2_prm_read_mod_reg(OCP_MOD
, OMAP3_PRM_IRQSTATUS_MPU_OFFSET
);
252 events
[0] = mask
& st
;
256 * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
258 * Force any buffered writes to the PRM IP block to complete. Needed
259 * by the PRM IRQ handler, which reads and writes directly to the IP
260 * block, to avoid race conditions after acknowledging or clearing IRQ
261 * bits. No return value.
263 void omap3xxx_prm_ocp_barrier(void)
265 omap2_prm_read_mod_reg(OCP_MOD
, OMAP3_PRM_REVISION_OFFSET
);
269 * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
270 * @saved_mask: ptr to a u32 array to save IRQENABLE bits
272 * Save the PRM_IRQENABLE_MPU register to @saved_mask. @saved_mask
273 * must be allocated by the caller. Intended to be used in the PRM
274 * interrupt handler suspend callback. The OCP barrier is needed to
275 * ensure the write to disable PRM interrupts reaches the PRM before
276 * returning; otherwise, spurious interrupts might occur. No return
279 void omap3xxx_prm_save_and_clear_irqen(u32
*saved_mask
)
281 saved_mask
[0] = omap2_prm_read_mod_reg(OCP_MOD
,
282 OMAP3_PRM_IRQENABLE_MPU_OFFSET
);
283 omap2_prm_write_mod_reg(0, OCP_MOD
, OMAP3_PRM_IRQENABLE_MPU_OFFSET
);
286 omap2_prm_read_mod_reg(OCP_MOD
, OMAP3_PRM_REVISION_OFFSET
);
290 * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
291 * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
293 * Restore the PRM_IRQENABLE_MPU register from @saved_mask. Intended
294 * to be used in the PRM interrupt handler resume callback to restore
295 * values saved by omap3xxx_prm_save_and_clear_irqen(). No OCP
296 * barrier should be needed here; any pending PRM interrupts will fire
297 * once the writes reach the PRM. No return value.
299 void omap3xxx_prm_restore_irqen(u32
*saved_mask
)
301 omap2_prm_write_mod_reg(saved_mask
[0], OCP_MOD
,
302 OMAP3_PRM_IRQENABLE_MPU_OFFSET
);
305 static int __init
omap3xxx_prcm_init(void)
309 if (cpu_is_omap34xx()) {
310 ret
= omap_prcm_register_chain_handler(&omap3_prcm_irq_setup
);
312 irq_set_status_flags(omap_prcm_event_to_irq("io"),
318 subsys_initcall(omap3xxx_prcm_init
);