arch/arm/mach-omap2/prm2xxx_3xxx.c

   1 /*
   2  * OMAP2/3 PRM module functions
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2010 Nokia Corporation
   6  * Benoît Cousson
   7  * Paul Walmsley
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/errno.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18
  19 #include "common.h"
  20 #include <plat/cpu.h>
  21 #include <plat/prcm.h>
  22 #include <plat/irqs.h>
  23
  24 #include "vp.h"
  25
  26 #include "prm2xxx_3xxx.h"
  27 #include "cm2xxx_3xxx.h"
  28 #include "prm-regbits-24xx.h"
  29 #include "prm-regbits-34xx.h"
  30
  31 static const struct omap_prcm_irq omap3_prcm_irqs[] = {
  32         OMAP_PRCM_IRQ("wkup",   0,      0),
  33         OMAP_PRCM_IRQ("io",     9,      1),
  34 };
  35
  36 static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
  37         .ack                    = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
  38         .mask                   = OMAP3_PRM_IRQENABLE_MPU_OFFSET,
  39         .nr_regs                = 1,
  40         .irqs                   = omap3_prcm_irqs,
  41         .nr_irqs                = ARRAY_SIZE(omap3_prcm_irqs),
  42         .irq                    = INT_34XX_PRCM_MPU_IRQ,
  43         .read_pending_irqs      = &omap3xxx_prm_read_pending_irqs,
  44         .ocp_barrier            = &omap3xxx_prm_ocp_barrier,
  45         .save_and_clear_irqen   = &omap3xxx_prm_save_and_clear_irqen,
  46         .restore_irqen          = &omap3xxx_prm_restore_irqen,
  47 };
  48
  49 u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
  50 {
  51         return __raw_readl(prm_base + module + idx);
  52 }
  53
  54 void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
  55 {
  56         __raw_writel(val, prm_base + module + idx);
  57 }
  58
  59 /* Read-modify-write a register in a PRM module. Caller must lock */
  60 u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
  61 {
  62         u32 v;
  63
  64         v = omap2_prm_read_mod_reg(module, idx);
  65         v &= ~mask;
  66         v |= bits;
  67         omap2_prm_write_mod_reg(v, module, idx);
  68
  69         return v;
  70 }
  71
  72 /* Read a PRM register, AND it, and shift the result down to bit 0 */
  73 u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
  74 {
  75         u32 v;
  76
  77         v = omap2_prm_read_mod_reg(domain, idx);
  78         v &= mask;
  79         v >>= __ffs(mask);
  80
  81         return v;
  82 }
  83
  84 u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
  85 {
  86         return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
  87 }
  88
  89 u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
  90 {
  91         return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
  92 }
  93
  94
  95 /**
  96  * omap2_prm_is_hardreset_asserted - read the HW reset line state of
  97  * submodules contained in the hwmod module
  98  * @prm_mod: PRM submodule base (e.g. CORE_MOD)
  99  * @shift: register bit shift corresponding to the reset line to check
 100  *
 101  * Returns 1 if the (sub)module hardreset line is currently asserted,
 102  * 0 if the (sub)module hardreset line is not currently asserted, or
 103  * -EINVAL if called while running on a non-OMAP2/3 chip.
 104  */
 105 int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
 106 {
 107         if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
 108                 return -EINVAL;
 109
 110         return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
 111                                        (1 << shift));
 112 }
 113
 114 /**
 115  * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
 116  * @prm_mod: PRM submodule base (e.g. CORE_MOD)
 117  * @shift: register bit shift corresponding to the reset line to assert
 118  *
 119  * Some IPs like dsp or iva contain processors that require an HW
 120  * reset line to be asserted / deasserted in order to fully enable the
 121  * IP.  These modules may have multiple hard-reset lines that reset
 122  * different 'submodules' inside the IP block.  This function will
 123  * place the submodule into reset.  Returns 0 upon success or -EINVAL
 124  * upon an argument error.
 125  */
 126 int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
 127 {
 128         u32 mask;
 129
 130         if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
 131                 return -EINVAL;
 132
 133         mask = 1 << shift;
 134         omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
 135
 136         return 0;
 137 }
 138
 139 /**
 140  * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait
 141  * @prm_mod: PRM submodule base (e.g. CORE_MOD)
 142  * @rst_shift: register bit shift corresponding to the reset line to deassert
 143  * @st_shift: register bit shift for the status of the deasserted submodule
 144  *
 145  * Some IPs like dsp or iva contain processors that require an HW
 146  * reset line to be asserted / deasserted in order to fully enable the
 147  * IP.  These modules may have multiple hard-reset lines that reset
 148  * different 'submodules' inside the IP block.  This function will
 149  * take the submodule out of reset and wait until the PRCM indicates
 150  * that the reset has completed before returning.  Returns 0 upon success or
 151  * -EINVAL upon an argument error, -EEXIST if the submodule was already out
 152  * of reset, or -EBUSY if the submodule did not exit reset promptly.
 153  */
 154 int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
 155 {
 156         u32 rst, st;
 157         int c;
 158
 159         if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
 160                 return -EINVAL;
 161
 162         rst = 1 << rst_shift;
 163         st = 1 << st_shift;
 164
 165         /* Check the current status to avoid de-asserting the line twice */
 166         if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, rst) == 0)
 167                 return -EEXIST;
 168
 169         /* Clear the reset status by writing 1 to the status bit */
 170         omap2_prm_rmw_mod_reg_bits(0xffffffff, st, prm_mod, OMAP2_RM_RSTST);
 171         /* de-assert the reset control line */
 172         omap2_prm_rmw_mod_reg_bits(rst, 0, prm_mod, OMAP2_RM_RSTCTRL);
 173         /* wait the status to be set */
 174         omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
 175                                                   st),
 176                           MAX_MODULE_HARDRESET_WAIT, c);
 177
 178         return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
 179 }
 180
 181 /* PRM VP */
 182
 183 /*
 184  * struct omap3_vp - OMAP3 VP register access description.
 185  * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
 186  */
 187 struct omap3_vp {
 188         u32 tranxdone_status;
 189 };
 190
 191 static struct omap3_vp omap3_vp[] = {
 192         [OMAP3_VP_VDD_MPU_ID] = {
 193                 .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
 194         },
 195         [OMAP3_VP_VDD_CORE_ID] = {
 196                 .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
 197         },
 198 };
 199
 200 #define MAX_VP_ID ARRAY_SIZE(omap3_vp);
 201
 202 u32 omap3_prm_vp_check_txdone(u8 vp_id)
 203 {
 204         struct omap3_vp *vp = &omap3_vp[vp_id];
 205         u32 irqstatus;
 206
 207         irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
 208                                            OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 209         return irqstatus & vp->tranxdone_status;
 210 }
 211
 212 void omap3_prm_vp_clear_txdone(u8 vp_id)
 213 {
 214         struct omap3_vp *vp = &omap3_vp[vp_id];
 215
 216         omap2_prm_write_mod_reg(vp->tranxdone_status,
 217                                 OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 218 }
 219
 220 u32 omap3_prm_vcvp_read(u8 offset)
 221 {
 222         return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
 223 }
 224
 225 void omap3_prm_vcvp_write(u32 val, u8 offset)
 226 {
 227         omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
 228 }
 229
 230 u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
 231 {
 232         return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
 233 }
 234
 235 /**
 236  * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
 237  * @events: ptr to a u32, preallocated by caller
 238  *
 239  * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
 240  * MPU IRQs, and store the result into the u32 pointed to by @events.
 241  * No return value.
 242  */
 243 void omap3xxx_prm_read_pending_irqs(unsigned long *events)
 244 {
 245         u32 mask, st;
 246
 247         /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
 248         mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 249         st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 250
 251         events[0] = mask & st;
 252 }
 253
 254 /**
 255  * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
 256  *
 257  * Force any buffered writes to the PRM IP block to complete.  Needed
 258  * by the PRM IRQ handler, which reads and writes directly to the IP
 259  * block, to avoid race conditions after acknowledging or clearing IRQ
 260  * bits.  No return value.
 261  */
 262 void omap3xxx_prm_ocp_barrier(void)
 263 {
 264         omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
 265 }
 266
 267 /**
 268  * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
 269  * @saved_mask: ptr to a u32 array to save IRQENABLE bits
 270  *
 271  * Save the PRM_IRQENABLE_MPU register to @saved_mask.  @saved_mask
 272  * must be allocated by the caller.  Intended to be used in the PRM
 273  * interrupt handler suspend callback.  The OCP barrier is needed to
 274  * ensure the write to disable PRM interrupts reaches the PRM before
 275  * returning; otherwise, spurious interrupts might occur.  No return
 276  * value.
 277  */
 278 void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
 279 {
 280         saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
 281                                                OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 282         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 283
 284         /* OCP barrier */
 285         omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
 286 }
 287
 288 /**
 289  * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
 290  * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
 291  *
 292  * Restore the PRM_IRQENABLE_MPU register from @saved_mask.  Intended
 293  * to be used in the PRM interrupt handler resume callback to restore
 294  * values saved by omap3xxx_prm_save_and_clear_irqen().  No OCP
 295  * barrier should be needed here; any pending PRM interrupts will fire
 296  * once the writes reach the PRM.  No return value.
 297  */
 298 void omap3xxx_prm_restore_irqen(u32 *saved_mask)
 299 {
 300         omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
 301                                 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 302 }
 303
 304 static int __init omap3xxx_prcm_init(void)
 305 {
 306         if (cpu_is_omap34xx())
 307                 return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
 308         return 0;
 309 }
 310 subsys_initcall(omap3xxx_prcm_init);