arch/arm/mach-omap2/prm2xxx_3xxx.h

   1 /*
   2  * OMAP2/3 Power/Reset Management (PRM) register definitions
   3  *
   4  * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
   5  * Copyright (C) 2008-2010 Nokia Corporation
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The PRM hardware modules on the OMAP2/3 are quite similar to each
  13  * other.  The PRM on OMAP4 has a new register layout, and is handled
  14  * in a separate file.
  15  */
  16 #ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
  17 #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
  18
  19 #include "prcm-common.h"
  20 #include "prm.h"
  21
  22 #define OMAP2420_PRM_REGADDR(module, reg)                               \
  23                 OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
  24 #define OMAP2430_PRM_REGADDR(module, reg)                               \
  25                 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
  26 #define OMAP34XX_PRM_REGADDR(module, reg)                               \
  27                 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
  28
  29
  30 /*
  31  * OMAP2-specific global PRM registers
  32  * Use __raw_{read,write}l() with these registers.
  33  *
  34  * With a few exceptions, these are the register names beginning with
  35  * PRCM_* on 24xx.  (The exceptions are the IRQSTATUS and IRQENABLE
  36  * bits.)
  37  *
  38  */
  39
  40 #define OMAP2_PRCM_REVISION_OFFSET      0x0000
  41 #define OMAP2420_PRCM_REVISION          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
  42 #define OMAP2_PRCM_SYSCONFIG_OFFSET     0x0010
  43 #define OMAP2420_PRCM_SYSCONFIG         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
  44
  45 #define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
  46 #define OMAP2420_PRCM_IRQSTATUS_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
  47 #define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
  48 #define OMAP2420_PRCM_IRQENABLE_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
  49
  50 #define OMAP2_PRCM_VOLTCTRL_OFFSET      0x0050
  51 #define OMAP2420_PRCM_VOLTCTRL          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
  52 #define OMAP2_PRCM_VOLTST_OFFSET        0x0054
  53 #define OMAP2420_PRCM_VOLTST            OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
  54 #define OMAP2_PRCM_CLKSRC_CTRL_OFFSET   0x0060
  55 #define OMAP2420_PRCM_CLKSRC_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
  56 #define OMAP2_PRCM_CLKOUT_CTRL_OFFSET   0x0070
  57 #define OMAP2420_PRCM_CLKOUT_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
  58 #define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET  0x0078
  59 #define OMAP2420_PRCM_CLKEMUL_CTRL      OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
  60 #define OMAP2_PRCM_CLKCFG_CTRL_OFFSET   0x0080
  61 #define OMAP2420_PRCM_CLKCFG_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
  62 #define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
  63 #define OMAP2420_PRCM_CLKCFG_STATUS     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
  64 #define OMAP2_PRCM_VOLTSETUP_OFFSET     0x0090
  65 #define OMAP2420_PRCM_VOLTSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
  66 #define OMAP2_PRCM_CLKSSETUP_OFFSET     0x0094
  67 #define OMAP2420_PRCM_CLKSSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
  68 #define OMAP2_PRCM_POLCTRL_OFFSET       0x0098
  69 #define OMAP2420_PRCM_POLCTRL           OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
  70
  71 #define OMAP2430_PRCM_REVISION          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
  72 #define OMAP2430_PRCM_SYSCONFIG         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
  73
  74 #define OMAP2430_PRCM_IRQSTATUS_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
  75 #define OMAP2430_PRCM_IRQENABLE_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
  76
  77 #define OMAP2430_PRCM_VOLTCTRL          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
  78 #define OMAP2430_PRCM_VOLTST            OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
  79 #define OMAP2430_PRCM_CLKSRC_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
  80 #define OMAP2430_PRCM_CLKOUT_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
  81 #define OMAP2430_PRCM_CLKEMUL_CTRL      OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
  82 #define OMAP2430_PRCM_CLKCFG_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
  83 #define OMAP2430_PRCM_CLKCFG_STATUS     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
  84 #define OMAP2430_PRCM_VOLTSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
  85 #define OMAP2430_PRCM_CLKSSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
  86 #define OMAP2430_PRCM_POLCTRL           OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
  87
  88 /*
  89  * OMAP3-specific global PRM registers
  90  * Use __raw_{read,write}l() with these registers.
  91  *
  92  * With a few exceptions, these are the register names beginning with
  93  * PRM_* on 34xx.  (The exceptions are the IRQSTATUS and IRQENABLE
  94  * bits.)
  95  */
  96
  97 #define OMAP3_PRM_REVISION_OFFSET       0x0004
  98 #define OMAP3430_PRM_REVISION           OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
  99 #define OMAP3_PRM_SYSCONFIG_OFFSET      0x0014
 100 #define OMAP3430_PRM_SYSCONFIG          OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
 101
 102 #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET  0x0018
 103 #define OMAP3430_PRM_IRQSTATUS_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
 104 #define OMAP3_PRM_IRQENABLE_MPU_OFFSET  0x001c
 105 #define OMAP3430_PRM_IRQENABLE_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
 106
 107
 108 #define OMAP3_PRM_VC_SMPS_SA_OFFSET     0x0020
 109 #define OMAP3430_PRM_VC_SMPS_SA         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
 110 #define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
 111 #define OMAP3430_PRM_VC_SMPS_VOL_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
 112 #define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
 113 #define OMAP3430_PRM_VC_SMPS_CMD_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
 114 #define OMAP3_PRM_VC_CMD_VAL_0_OFFSET   0x002c
 115 #define OMAP3430_PRM_VC_CMD_VAL_0       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
 116 #define OMAP3_PRM_VC_CMD_VAL_1_OFFSET   0x0030
 117 #define OMAP3430_PRM_VC_CMD_VAL_1       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
 118 #define OMAP3_PRM_VC_CH_CONF_OFFSET     0x0034
 119 #define OMAP3430_PRM_VC_CH_CONF         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
 120 #define OMAP3_PRM_VC_I2C_CFG_OFFSET     0x0038
 121 #define OMAP3430_PRM_VC_I2C_CFG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
 122 #define OMAP3_PRM_VC_BYPASS_VAL_OFFSET  0x003c
 123 #define OMAP3430_PRM_VC_BYPASS_VAL      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
 124 #define OMAP3_PRM_RSTCTRL_OFFSET        0x0050
 125 #define OMAP3430_PRM_RSTCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
 126 #define OMAP3_PRM_RSTTIME_OFFSET        0x0054
 127 #define OMAP3430_PRM_RSTTIME            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
 128 #define OMAP3_PRM_RSTST_OFFSET  0x0058
 129 #define OMAP3430_PRM_RSTST              OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
 130 #define OMAP3_PRM_VOLTCTRL_OFFSET       0x0060
 131 #define OMAP3430_PRM_VOLTCTRL           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
 132 #define OMAP3_PRM_SRAM_PCHARGE_OFFSET   0x0064
 133 #define OMAP3430_PRM_SRAM_PCHARGE       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
 134 #define OMAP3_PRM_CLKSRC_CTRL_OFFSET    0x0070
 135 #define OMAP3430_PRM_CLKSRC_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
 136 #define OMAP3_PRM_VOLTSETUP1_OFFSET     0x0090
 137 #define OMAP3430_PRM_VOLTSETUP1         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
 138 #define OMAP3_PRM_VOLTOFFSET_OFFSET     0x0094
 139 #define OMAP3430_PRM_VOLTOFFSET         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
 140 #define OMAP3_PRM_CLKSETUP_OFFSET       0x0098
 141 #define OMAP3430_PRM_CLKSETUP           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
 142 #define OMAP3_PRM_POLCTRL_OFFSET        0x009c
 143 #define OMAP3430_PRM_POLCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
 144 #define OMAP3_PRM_VOLTSETUP2_OFFSET     0x00a0
 145 #define OMAP3430_PRM_VOLTSETUP2         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
 146 #define OMAP3_PRM_VP1_CONFIG_OFFSET     0x00b0
 147 #define OMAP3430_PRM_VP1_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
 148 #define OMAP3_PRM_VP1_VSTEPMIN_OFFSET   0x00b4
 149 #define OMAP3430_PRM_VP1_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
 150 #define OMAP3_PRM_VP1_VSTEPMAX_OFFSET   0x00b8
 151 #define OMAP3430_PRM_VP1_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
 152 #define OMAP3_PRM_VP1_VLIMITTO_OFFSET   0x00bc
 153 #define OMAP3430_PRM_VP1_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
 154 #define OMAP3_PRM_VP1_VOLTAGE_OFFSET    0x00c0
 155 #define OMAP3430_PRM_VP1_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
 156 #define OMAP3_PRM_VP1_STATUS_OFFSET     0x00c4
 157 #define OMAP3430_PRM_VP1_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
 158 #define OMAP3_PRM_VP2_CONFIG_OFFSET     0x00d0
 159 #define OMAP3430_PRM_VP2_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
 160 #define OMAP3_PRM_VP2_VSTEPMIN_OFFSET   0x00d4
 161 #define OMAP3430_PRM_VP2_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
 162 #define OMAP3_PRM_VP2_VSTEPMAX_OFFSET   0x00d8
 163 #define OMAP3430_PRM_VP2_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
 164 #define OMAP3_PRM_VP2_VLIMITTO_OFFSET   0x00dc
 165 #define OMAP3430_PRM_VP2_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
 166 #define OMAP3_PRM_VP2_VOLTAGE_OFFSET    0x00e0
 167 #define OMAP3430_PRM_VP2_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
 168 #define OMAP3_PRM_VP2_STATUS_OFFSET     0x00e4
 169 #define OMAP3430_PRM_VP2_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
 170
 171 #define OMAP3_PRM_CLKSEL_OFFSET 0x0040
 172 #define OMAP3430_PRM_CLKSEL             OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
 173 #define OMAP3_PRM_CLKOUT_CTRL_OFFSET    0x0070
 174 #define OMAP3430_PRM_CLKOUT_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
 175
 176 /*
 177  * Module specific PRM register offsets from PRM_BASE + domain offset
 178  *
 179  * Use prm_{read,write}_mod_reg() with these registers.
 180  *
 181  * With a few exceptions, these are the register names beginning with
 182  * {PM,RM}_* on both OMAP2/3 SoC families..  (The exceptions are the
 183  * IRQSTATUS and IRQENABLE bits.)
 184  */
 185
 186 /* Register offsets appearing on both OMAP2 and OMAP3 */
 187
 188 #define OMAP2_RM_RSTCTRL                                0x0050
 189 #define OMAP2_RM_RSTTIME                                0x0054
 190 #define OMAP2_RM_RSTST                                  0x0058
 191 #define OMAP2_PM_PWSTCTRL                               0x00e0
 192 #define OMAP2_PM_PWSTST                                 0x00e4
 193
 194 #define PM_WKEN                                         0x00a0
 195 #define PM_WKEN1                                        PM_WKEN
 196 #define PM_WKST                                         0x00b0
 197 #define PM_WKST1                                        PM_WKST
 198 #define PM_WKDEP                                        0x00c8
 199 #define PM_EVGENCTRL                                    0x00d4
 200 #define PM_EVGENONTIM                                   0x00d8
 201 #define PM_EVGENOFFTIM                                  0x00dc
 202
 203 /* OMAP2xxx specific register offsets */
 204 #define OMAP24XX_PM_WKEN2                               0x00a4
 205 #define OMAP24XX_PM_WKST2                               0x00b4
 206
 207 #define OMAP24XX_PRCM_IRQSTATUS_DSP                     0x00f0  /* IVA mod */
 208 #define OMAP24XX_PRCM_IRQENABLE_DSP                     0x00f4  /* IVA mod */
 209 #define OMAP24XX_PRCM_IRQSTATUS_IVA                     0x00f8
 210 #define OMAP24XX_PRCM_IRQENABLE_IVA                     0x00fc
 211
 212 /* OMAP3 specific register offsets */
 213 #define OMAP3430ES2_PM_WKEN3                            0x00f0
 214 #define OMAP3430ES2_PM_WKST3                            0x00b8
 215
 216 #define OMAP3430_PM_MPUGRPSEL                           0x00a4
 217 #define OMAP3430_PM_MPUGRPSEL1                          OMAP3430_PM_MPUGRPSEL
 218 #define OMAP3430ES2_PM_MPUGRPSEL3                       0x00f8
 219
 220 #define OMAP3430_PM_IVAGRPSEL                           0x00a8
 221 #define OMAP3430_PM_IVAGRPSEL1                          OMAP3430_PM_IVAGRPSEL
 222 #define OMAP3430ES2_PM_IVAGRPSEL3                       0x00f4
 223
 224 #define OMAP3430_PM_PREPWSTST                           0x00e8
 225
 226 #define OMAP3430_PRM_IRQSTATUS_IVA2                     0x00f8
 227 #define OMAP3430_PRM_IRQENABLE_IVA2                     0x00fc
 228
 229
 230 #ifndef __ASSEMBLER__
 231 /* Power/reset management domain register get/set */
 232 extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
 233 extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx);
 234 extern u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
 235 extern u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
 236 extern u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
 237 extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
 238
 239 /* These omap2_ PRM functions apply to both OMAP2 and 3 */
 240 extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
 241 extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
 242 extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
 243
 244 /* OMAP3-specific VP functions */
 245 u32 omap3_prm_vp_check_txdone(u8 vp_id);
 246 void omap3_prm_vp_clear_txdone(u8 vp_id);
 247
 248 /*
 249  * OMAP3 access functions for voltage controller (VC) and
 250  * voltage proccessor (VP) in the PRM.
 251  */
 252 extern u32 omap3_prm_vcvp_read(u8 offset);
 253 extern void omap3_prm_vcvp_write(u32 val, u8 offset);
 254 extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
 255
 256 extern void omap3xxx_prm_reconfigure_io_chain(void);
 257
 258 /* PRM interrupt-related functions */
 259 extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
 260 extern void omap3xxx_prm_ocp_barrier(void);
 261 extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
 262 extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
 263
 264 #endif /* __ASSEMBLER */
 265
 266 /*
 267  * Bits common to specific registers
 268  *
 269  * The 3430 register and bit names are generally used,
 270  * since they tend to make more sense
 271  */
 272
 273 /* PM_EVGENONTIM_MPU */
 274 /* Named PM_EVEGENONTIM_MPU on the 24XX */
 275 #define OMAP_ONTIMEVAL_SHIFT                            0
 276 #define OMAP_ONTIMEVAL_MASK                             (0xffffffff << 0)
 277
 278 /* PM_EVGENOFFTIM_MPU */
 279 /* Named PM_EVEGENOFFTIM_MPU on the 24XX */
 280 #define OMAP_OFFTIMEVAL_SHIFT                           0
 281 #define OMAP_OFFTIMEVAL_MASK                            (0xffffffff << 0)
 282
 283 /* PRM_CLKSETUP and PRCM_VOLTSETUP */
 284 /* Named PRCM_CLKSSETUP on the 24XX */
 285 #define OMAP_SETUP_TIME_SHIFT                           0
 286 #define OMAP_SETUP_TIME_MASK                            (0xffff << 0)
 287
 288 /* PRM_CLKSRC_CTRL */
 289 /* Named PRCM_CLKSRC_CTRL on the 24XX */
 290 #define OMAP_SYSCLKDIV_SHIFT                            6
 291 #define OMAP_SYSCLKDIV_MASK                             (0x3 << 6)
 292 #define OMAP_AUTOEXTCLKMODE_SHIFT                       3
 293 #define OMAP_AUTOEXTCLKMODE_MASK                        (0x3 << 3)
 294 #define OMAP_SYSCLKSEL_SHIFT                            0
 295 #define OMAP_SYSCLKSEL_MASK                             (0x3 << 0)
 296
 297 /* PM_EVGENCTRL_MPU */
 298 #define OMAP_OFFLOADMODE_SHIFT                          3
 299 #define OMAP_OFFLOADMODE_MASK                           (0x3 << 3)
 300 #define OMAP_ONLOADMODE_SHIFT                           1
 301 #define OMAP_ONLOADMODE_MASK                            (0x3 << 1)
 302 #define OMAP_ENABLE_MASK                                (1 << 0)
 303
 304 /* PRM_RSTTIME */
 305 /* Named RM_RSTTIME_WKUP on the 24xx */
 306 #define OMAP_RSTTIME2_SHIFT                             8
 307 #define OMAP_RSTTIME2_MASK                              (0x1f << 8)
 308 #define OMAP_RSTTIME1_SHIFT                             0
 309 #define OMAP_RSTTIME1_MASK                              (0xff << 0)
 310
 311 /* PRM_RSTCTRL */
 312 /* Named RM_RSTCTRL_WKUP on the 24xx */
 313 /* 2420 calls RST_DPLL3 'RST_DPLL' */
 314 #define OMAP_RST_DPLL3_MASK                             (1 << 2)
 315 #define OMAP_RST_GS_MASK                                (1 << 1)
 316
 317
 318 /*
 319  * Bits common to module-shared registers
 320  *
 321  * Not all registers of a particular type support all of these bits -
 322  * check TRM if you are unsure
 323  */
 324
 325 /*
 326  * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
 327  *       called 'COREWKUP_RST'
 328  *
 329  * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
 330  *       RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
 331  */
 332 #define OMAP_COREDOMAINWKUP_RST_MASK                    (1 << 3)
 333
 334 /*
 335  * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
 336  *
 337  * 2430: RM_RSTST_MDM
 338  *
 339  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
 340  */
 341 #define OMAP_DOMAINWKUP_RST_MASK                        (1 << 2)
 342
 343 /*
 344  * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
 345  *       On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
 346  *
 347  * 2430: RM_RSTST_MDM
 348  *
 349  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
 350  */
 351 #define OMAP_GLOBALWARM_RST_MASK                        (1 << 1)
 352 #define OMAP_GLOBALCOLD_RST_MASK                        (1 << 0)
 353
 354 /*
 355  * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
 356  *       2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
 357  *
 358  * 2430: PM_WKDEP_MDM
 359  *
 360  * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
 361  *       PM_WKDEP_PER
 362  */
 363 #define OMAP_EN_WKUP_SHIFT                              4
 364 #define OMAP_EN_WKUP_MASK                               (1 << 4)
 365
 366 /*
 367  * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
 368  *       PM_PWSTCTRL_DSP
 369  *
 370  * 2430: PM_PWSTCTRL_MDM
 371  *
 372  * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
 373  *       PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
 374  *       PM_PWSTCTRL_NEON
 375  */
 376 #define OMAP_LOGICRETSTATE_MASK                         (1 << 2)
 377
 378
 379 /*
 380  * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
 381  * submodule to exit hardreset
 382  */
 383 #define MAX_MODULE_HARDRESET_WAIT               10000
 384
 385
 386 #endif