arch/arm/mach-omap2/prm_common.c

   1 /*
   2  * OMAP2+ common Power & Reset Management (PRM) IP block functions
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc.
   5  * Tero Kristo <t-kristo@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  *
  12  * For historical purposes, the API used to configure the PRM
  13  * interrupt handler refers to it as the "PRCM interrupt."  The
  14  * underlying registers are located in the PRM on OMAP3/4.
  15  *
  16  * XXX This code should eventually be moved to a PRM driver.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/init.h>
  22 #include <linux/io.h>
  23 #include <linux/irq.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/slab.h>
  26
  27 #include <plat/prcm.h>
  28
  29 #include "prm2xxx_3xxx.h"
  30 #include "prm44xx.h"
  31
  32 /*
  33  * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
  34  * XXX this is technically not needed, since
  35  * omap_prcm_register_chain_handler() could allocate this based on the
  36  * actual amount of memory needed for the SoC
  37  */
  38 #define OMAP_PRCM_MAX_NR_PENDING_REG            2
  39
  40 /*
  41  * prcm_irq_chips: an array of all of the "generic IRQ chips" in use
  42  * by the PRCM interrupt handler code.  There will be one 'chip' per
  43  * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair.  (So OMAP3 will have
  44  * one "chip" and OMAP4 will have two.)
  45  */
  46 static struct irq_chip_generic **prcm_irq_chips;
  47
  48 /*
  49  * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
  50  * is currently running on.  Defined and passed by initialization code
  51  * that calls omap_prcm_register_chain_handler().
  52  */
  53 static struct omap_prcm_irq_setup *prcm_irq_setup;
  54
  55 /* Private functions */
  56
  57 /*
  58  * Move priority events from events to priority_events array
  59  */
  60 static void omap_prcm_events_filter_priority(unsigned long *events,
  61         unsigned long *priority_events)
  62 {
  63         int i;
  64
  65         for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
  66                 priority_events[i] =
  67                         events[i] & prcm_irq_setup->priority_mask[i];
  68                 events[i] ^= priority_events[i];
  69         }
  70 }
  71
  72 /*
  73  * PRCM Interrupt Handler
  74  *
  75  * This is a common handler for the OMAP PRCM interrupts. Pending
  76  * interrupts are detected by a call to prcm_pending_events and
  77  * dispatched accordingly. Clearing of the wakeup events should be
  78  * done by the SoC specific individual handlers.
  79  */
  80 static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
  81 {
  82         unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
  83         unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
  84         struct irq_chip *chip = irq_desc_get_chip(desc);
  85         unsigned int virtirq;
  86         int nr_irq = prcm_irq_setup->nr_regs * 32;
  87
  88         /*
  89          * If we are suspended, mask all interrupts from PRCM level,
  90          * this does not ack them, and they will be pending until we
  91          * re-enable the interrupts, at which point the
  92          * omap_prcm_irq_handler will be executed again.  The
  93          * _save_and_clear_irqen() function must ensure that the PRM
  94          * write to disable all IRQs has reached the PRM before
  95          * returning, or spurious PRCM interrupts may occur during
  96          * suspend.
  97          */
  98         if (prcm_irq_setup->suspended) {
  99                 prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
 100                 prcm_irq_setup->suspend_save_flag = true;
 101         }
 102
 103         /*
 104          * Loop until all pending irqs are handled, since
 105          * generic_handle_irq() can cause new irqs to come
 106          */
 107         while (!prcm_irq_setup->suspended) {
 108                 prcm_irq_setup->read_pending_irqs(pending);
 109
 110                 /* No bit set, then all IRQs are handled */
 111                 if (find_first_bit(pending, nr_irq) >= nr_irq)
 112                         break;
 113
 114                 omap_prcm_events_filter_priority(pending, priority_pending);
 115
 116                 /*
 117                  * Loop on all currently pending irqs so that new irqs
 118                  * cannot starve previously pending irqs
 119                  */
 120
 121                 /* Serve priority events first */
 122                 for_each_set_bit(virtirq, priority_pending, nr_irq)
 123                         generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
 124
 125                 /* Serve normal events next */
 126                 for_each_set_bit(virtirq, pending, nr_irq)
 127                         generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
 128         }
 129         if (chip->irq_ack)
 130                 chip->irq_ack(&desc->irq_data);
 131         if (chip->irq_eoi)
 132                 chip->irq_eoi(&desc->irq_data);
 133         chip->irq_unmask(&desc->irq_data);
 134
 135         prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
 136 }
 137
 138 /* Public functions */
 139
 140 /**
 141  * omap_prcm_event_to_irq - given a PRCM event name, returns the
 142  * corresponding IRQ on which the handler should be registered
 143  * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
 144  *
 145  * Returns the Linux internal IRQ ID corresponding to @name upon success,
 146  * or -ENOENT upon failure.
 147  */
 148 int omap_prcm_event_to_irq(const char *name)
 149 {
 150         int i;
 151
 152         if (!prcm_irq_setup || !name)
 153                 return -ENOENT;
 154
 155         for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
 156                 if (!strcmp(prcm_irq_setup->irqs[i].name, name))
 157                         return prcm_irq_setup->base_irq +
 158                                 prcm_irq_setup->irqs[i].offset;
 159
 160         return -ENOENT;
 161 }
 162
 163 /**
 164  * omap_prcm_irq_cleanup - reverses memory allocated and other steps
 165  * done by omap_prcm_register_chain_handler()
 166  *
 167  * No return value.
 168  */
 169 void omap_prcm_irq_cleanup(void)
 170 {
 171         int i;
 172
 173         if (!prcm_irq_setup) {
 174                 pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
 175                 return;
 176         }
 177
 178         if (prcm_irq_chips) {
 179                 for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
 180                         if (prcm_irq_chips[i])
 181                                 irq_remove_generic_chip(prcm_irq_chips[i],
 182                                         0xffffffff, 0, 0);
 183                         prcm_irq_chips[i] = NULL;
 184                 }
 185                 kfree(prcm_irq_chips);
 186                 prcm_irq_chips = NULL;
 187         }
 188
 189         kfree(prcm_irq_setup->saved_mask);
 190         prcm_irq_setup->saved_mask = NULL;
 191
 192         kfree(prcm_irq_setup->priority_mask);
 193         prcm_irq_setup->priority_mask = NULL;
 194
 195         irq_set_chained_handler(prcm_irq_setup->irq, NULL);
 196
 197         if (prcm_irq_setup->base_irq > 0)
 198                 irq_free_descs(prcm_irq_setup->base_irq,
 199                         prcm_irq_setup->nr_regs * 32);
 200         prcm_irq_setup->base_irq = 0;
 201 }
 202
 203 void omap_prcm_irq_prepare(void)
 204 {
 205         prcm_irq_setup->suspended = true;
 206 }
 207
 208 void omap_prcm_irq_complete(void)
 209 {
 210         prcm_irq_setup->suspended = false;
 211
 212         /* If we have not saved the masks, do not attempt to restore */
 213         if (!prcm_irq_setup->suspend_save_flag)
 214                 return;
 215
 216         prcm_irq_setup->suspend_save_flag = false;
 217
 218         /*
 219          * Re-enable all masked PRCM irq sources, this causes the PRCM
 220          * interrupt to fire immediately if the events were masked
 221          * previously in the chain handler
 222          */
 223         prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
 224 }
 225
 226 /**
 227  * omap_prcm_register_chain_handler - initializes the prcm chained interrupt
 228  * handler based on provided parameters
 229  * @irq_setup: hardware data about the underlying PRM/PRCM
 230  *
 231  * Set up the PRCM chained interrupt handler on the PRCM IRQ.  Sets up
 232  * one generic IRQ chip per PRM interrupt status/enable register pair.
 233  * Returns 0 upon success, -EINVAL if called twice or if invalid
 234  * arguments are passed, or -ENOMEM on any other error.
 235  */
 236 int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
 237 {
 238         int nr_regs;
 239         u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
 240         int offset, i;
 241         struct irq_chip_generic *gc;
 242         struct irq_chip_type *ct;
 243
 244         if (!irq_setup)
 245                 return -EINVAL;
 246
 247         nr_regs = irq_setup->nr_regs;
 248
 249         if (prcm_irq_setup) {
 250                 pr_err("PRCM: already initialized; won't reinitialize\n");
 251                 return -EINVAL;
 252         }
 253
 254         if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
 255                 pr_err("PRCM: nr_regs too large\n");
 256                 return -EINVAL;
 257         }
 258
 259         prcm_irq_setup = irq_setup;
 260
 261         prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL);
 262         prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
 263         prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
 264                 GFP_KERNEL);
 265
 266         if (!prcm_irq_chips || !prcm_irq_setup->saved_mask ||
 267             !prcm_irq_setup->priority_mask) {
 268                 pr_err("PRCM: kzalloc failed\n");
 269                 goto err;
 270         }
 271
 272         memset(mask, 0, sizeof(mask));
 273
 274         for (i = 0; i < irq_setup->nr_irqs; i++) {
 275                 offset = irq_setup->irqs[i].offset;
 276                 mask[offset >> 5] |= 1 << (offset & 0x1f);
 277                 if (irq_setup->irqs[i].priority)
 278                         irq_setup->priority_mask[offset >> 5] |=
 279                                 1 << (offset & 0x1f);
 280         }
 281
 282         irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
 283
 284         irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
 285                 0);
 286
 287         if (irq_setup->base_irq < 0) {
 288                 pr_err("PRCM: failed to allocate irq descs: %d\n",
 289                         irq_setup->base_irq);
 290                 goto err;
 291         }
 292
 293         for (i = 0; i < irq_setup->nr_regs; i++) {
 294                 gc = irq_alloc_generic_chip("PRCM", 1,
 295                         irq_setup->base_irq + i * 32, prm_base,
 296                         handle_level_irq);
 297
 298                 if (!gc) {
 299                         pr_err("PRCM: failed to allocate generic chip\n");
 300                         goto err;
 301                 }
 302                 ct = gc->chip_types;
 303                 ct->chip.irq_ack = irq_gc_ack_set_bit;
 304                 ct->chip.irq_mask = irq_gc_mask_clr_bit;
 305                 ct->chip.irq_unmask = irq_gc_mask_set_bit;
 306
 307                 ct->regs.ack = irq_setup->ack + i * 4;
 308                 ct->regs.mask = irq_setup->mask + i * 4;
 309
 310                 irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
 311                 prcm_irq_chips[i] = gc;
 312         }
 313
 314         return 0;
 315
 316 err:
 317         omap_prcm_irq_cleanup();
 318         return -ENOMEM;
 319 }
 320
 321 /*
 322  * Stubbed functions so that common files continue to build when
 323  * custom builds are used
 324  * XXX These are temporary and should be removed at the earliest possible
 325  * opportunity
 326  */
 327 u32 __weak omap2_prm_read_mod_reg(s16 module, u16 idx)
 328 {
 329         WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
 330         return 0;
 331 }
 332
 333 void __weak omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
 334 {
 335         WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
 336 }
 337
 338 u32 __weak omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits,
 339                 s16 module, s16 idx)
 340 {
 341         WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
 342         return 0;
 343 }
 344
 345 u32 __weak omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
 346 {
 347         WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
 348         return 0;
 349 }
 350
 351 u32 __weak omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 352 {
 353         WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
 354         return 0;
 355 }
 356
 357 u32 __weak omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
 358 {
 359         WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
 360         return 0;
 361 }
 362
 363 int __weak omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
 364 {
 365         WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
 366         return 0;
 367 }
 368
 369 int __weak omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
 370 {
 371         WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
 372         return 0;
 373 }
 374
 375 int __weak omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift,
 376                                                 u8 st_shift)
 377 {
 378         WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
 379         return 0;
 380 }
 381