1 #ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H
2 #define __ARCH_ARM_MACH_OMAP2_SDRC_H
5 * OMAP2/3 SDRC/SMS macros and prototypes
7 * Copyright (C) 2007-2008, 2012 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
24 extern void __iomem
*omap2_sdrc_base
;
25 extern void __iomem
*omap2_sms_base
;
27 #define OMAP_SDRC_REGADDR(reg) (omap2_sdrc_base + (reg))
28 #define OMAP_SMS_REGADDR(reg) (omap2_sms_base + (reg))
30 /* SDRC global register get/set */
32 static inline void sdrc_write_reg(u32 val
, u16 reg
)
34 __raw_writel(val
, OMAP_SDRC_REGADDR(reg
));
37 static inline u32
sdrc_read_reg(u16 reg
)
39 return __raw_readl(OMAP_SDRC_REGADDR(reg
));
42 /* SMS global register get/set */
44 static inline void sms_write_reg(u32 val
, u16 reg
)
46 __raw_writel(val
, OMAP_SMS_REGADDR(reg
));
49 static inline u32
sms_read_reg(u16 reg
)
51 return __raw_readl(OMAP_SMS_REGADDR(reg
));
56 * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
57 * @rate: SDRC clock rate (in Hz)
58 * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
59 * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
60 * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
61 * @mr: Value to program to SDRC_MR for this rate
63 * This structure holds a pre-computed set of register values for the
64 * SDRC for a given SDRC clock rate and SDRAM chip. These are
65 * intended to be pre-computed and specified in an array in the board-*.c
66 * files. The structure is keyed off the 'rate' field.
68 struct omap_sdrc_params
{
76 #ifdef CONFIG_SOC_HAS_OMAP2_SDRC
77 void omap2_sdrc_init(struct omap_sdrc_params
*sdrc_cs0
,
78 struct omap_sdrc_params
*sdrc_cs1
);
80 static inline void __init
omap2_sdrc_init(struct omap_sdrc_params
*sdrc_cs0
,
81 struct omap_sdrc_params
*sdrc_cs1
) {};
84 int omap2_sdrc_get_params(unsigned long r
,
85 struct omap_sdrc_params
**sdrc_cs0
,
86 struct omap_sdrc_params
**sdrc_cs1
);
87 void omap2_sms_save_context(void);
88 void omap2_sms_restore_context(void);
90 struct memory_timings
{
91 u32 m_type
; /* ddr = 1, sdr = 0 */
92 u32 dll_mode
; /* use lock mode = 1, unlock mode = 0 */
93 u32 slow_dll_ctrl
; /* unlock mode, dll value for slow speed */
94 u32 fast_dll_ctrl
; /* unlock mode, dll value for fast speed */
95 u32 base_cs
; /* base chip select to use for calculations */
98 extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode
);
99 struct omap_sdrc_params
*rx51_get_sdram_timings(void);
101 u32
omap2xxx_sdrc_dll_is_unlocked(void);
102 u32
omap2xxx_sdrc_reprogram(u32 level
, u32 force
);
106 #define OMAP242X_SDRC_REGADDR(reg) \
107 OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
108 #define OMAP243X_SDRC_REGADDR(reg) \
109 OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
110 #define OMAP34XX_SDRC_REGADDR(reg) \
111 OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
113 #endif /* __ASSEMBLER__ */
115 /* Minimum frequency that the SDRC DLL can lock at */
116 #define MIN_SDRC_DLL_LOCK_FREQ 83000000
118 /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
119 #define SDRC_MPURATE_SCALE 8
121 /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
122 #define SDRC_MPURATE_BASE_SHIFT 9
125 * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
126 * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
128 #define SDRC_MPURATE_LOOPS 96
130 /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
132 #define SDRC_SYSCONFIG 0x010
133 #define SDRC_CS_CFG 0x040
134 #define SDRC_SHARING 0x044
135 #define SDRC_ERR_TYPE 0x04C
136 #define SDRC_DLLA_CTRL 0x060
137 #define SDRC_DLLA_STATUS 0x064
138 #define SDRC_DLLB_CTRL 0x068
139 #define SDRC_DLLB_STATUS 0x06C
140 #define SDRC_POWER 0x070
141 #define SDRC_MCFG_0 0x080
142 #define SDRC_MR_0 0x084
143 #define SDRC_EMR2_0 0x08c
144 #define SDRC_ACTIM_CTRL_A_0 0x09c
145 #define SDRC_ACTIM_CTRL_B_0 0x0a0
146 #define SDRC_RFR_CTRL_0 0x0a4
147 #define SDRC_MANUAL_0 0x0a8
148 #define SDRC_MCFG_1 0x0B0
149 #define SDRC_MR_1 0x0B4
150 #define SDRC_EMR2_1 0x0BC
151 #define SDRC_ACTIM_CTRL_A_1 0x0C4
152 #define SDRC_ACTIM_CTRL_B_1 0x0C8
153 #define SDRC_RFR_CTRL_1 0x0D4
154 #define SDRC_MANUAL_1 0x0D8
156 #define SDRC_POWER_AUTOCOUNT_SHIFT 8
157 #define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
158 #define SDRC_POWER_CLKCTRL_SHIFT 4
159 #define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
160 #define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
163 * These values represent the number of memory clock cycles between
164 * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
165 * rows per device, and include a subtraction of a 50 cycle window in the
166 * event that the autorefresh command is delayed due to other SDRC activity.
167 * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
170 * These represent optimal values for common parts, it won't work for all.
171 * As long as you scale down, most parameters are still work, they just
172 * become sub-optimal. The RFR value goes in the opposite direction. If you
173 * don't adjust it down as your clock period increases the refresh interval
174 * will not be met. Setting all parameters for complete worst case may work,
175 * but may cut memory performance by 2x. Due to errata the DLLs need to be
176 * unlocked and their value needs run time calibration. A dynamic call is
177 * need for that as no single right value exists acorss production samples.
179 * Only the FULL speed values are given. Current code is such that rate
180 * changes must be made at DPLLoutx2. The actual value adjustment for low
181 * frequency operation will be handled by omap_set_performance()
183 * By having the boot loader boot up in the fastest L4 speed available likely
184 * will result in something which you can switch between.
186 #define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
187 #define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
188 #define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
189 #define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
190 #define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
194 * SMS register access
197 #define OMAP242X_SMS_REGADDR(reg) \
198 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
199 #define OMAP243X_SMS_REGADDR(reg) \
200 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
201 #define OMAP343X_SMS_REGADDR(reg) \
202 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
204 /* SMS register offsets - read/write with sms_{read,write}_reg() */
206 #define SMS_SYSCONFIG 0x010
207 /* REVISIT: fill in other SMS registers here */