arch/arm/mach-omap2/sdrc2xxx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/sdrc2xxx.c
   3  *
   4  * SDRAM timing related functions for OMAP2xxx
   5  *
   6  * Copyright (C) 2005, 2008 Texas Instruments Inc.
   7  * Copyright (C) 2005, 2008 Nokia Corporation
   8  *
   9  * Tony Lindgren <tony@atomide.com>
  10  * Paul Walmsley
  11  * Richard Woodruff <r-woodruff2@ti.com>
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/device.h>
  21 #include <linux/list.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/clk.h>
  25 #include <linux/io.h>
  26
  27 #include <plat/clock.h>
  28 #include <plat/sram.h>
  29 #include <plat/sdrc.h>
  30
  31 #include "soc.h"
  32 #include "iomap.h"
  33 #include "common.h"
  34 #include "prm2xxx_3xxx.h"
  35 #include "clock.h"
  36 #include "sdrc.h"
  37
  38 /* Memory timing, DLL mode flags */
  39 #define M_DDR           1
  40 #define M_LOCK_CTRL     (1 << 2)
  41 #define M_UNLOCK        0
  42 #define M_LOCK          1
  43
  44
  45 static struct memory_timings mem_timings;
  46 static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
  47
  48 static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
  49 {
  50         return mem_timings.slow_dll_ctrl;
  51 }
  52
  53 static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
  54 {
  55         return mem_timings.fast_dll_ctrl;
  56 }
  57
  58 static u32 omap2xxx_sdrc_get_type(void)
  59 {
  60         return mem_timings.m_type;
  61 }
  62
  63 /*
  64  * Check the DLL lock state, and return tue if running in unlock mode.
  65  * This is needed to compensate for the shifted DLL value in unlock mode.
  66  */
  67 u32 omap2xxx_sdrc_dll_is_unlocked(void)
  68 {
  69         /* dlla and dllb are a set */
  70         u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
  71
  72         if ((dll_state & (1 << 2)) == (1 << 2))
  73                 return 1;
  74         else
  75                 return 0;
  76 }
  77
  78 /*
  79  * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
  80  * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
  81  * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
  82  *
  83  * Used by the clock framework during CORE DPLL changes
  84  */
  85 u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
  86 {
  87         u32 dll_ctrl, m_type;
  88         u32 prev = curr_perf_level;
  89         unsigned long flags;
  90
  91         if ((curr_perf_level == level) && !force)
  92                 return prev;
  93
  94         if (level == CORE_CLK_SRC_DPLL)
  95                 dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
  96         else if (level == CORE_CLK_SRC_DPLL_X2)
  97                 dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
  98         else
  99                 return prev;
 100
 101         m_type = omap2xxx_sdrc_get_type();
 102
 103         local_irq_save(flags);
 104         /*
 105          * XXX These calls should be abstracted out through a
 106          * prm2xxx.c function
 107          */
 108         if (cpu_is_omap2420())
 109                 __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP);
 110         else
 111                 __raw_writel(0xffff, OMAP2430_PRCM_VOLTSETUP);
 112         omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
 113         curr_perf_level = level;
 114         local_irq_restore(flags);
 115
 116         return prev;
 117 }
 118
 119 /* Used by the clock framework during CORE DPLL changes */
 120 void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
 121 {
 122         unsigned long dll_cnt;
 123         u32 fast_dll = 0;
 124
 125         /* DDR = 1, SDR = 0 */
 126         mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
 127
 128         /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
 129          * In the case of 2422, its ok to use CS1 instead of CS0.
 130          */
 131         if (cpu_is_omap2422())
 132                 mem_timings.base_cs = 1;
 133         else
 134                 mem_timings.base_cs = 0;
 135
 136         if (mem_timings.m_type != M_DDR)
 137                 return;
 138
 139         /* With DDR we need to determine the low frequency DLL value */
 140         if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
 141                 mem_timings.dll_mode = M_UNLOCK;
 142         else
 143                 mem_timings.dll_mode = M_LOCK;
 144
 145         if (mem_timings.base_cs == 0) {
 146                 fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
 147                 dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
 148         } else {
 149                 fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
 150                 dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
 151         }
 152         if (force_lock_to_unlock_mode) {
 153                 fast_dll &= ~0xff00;
 154                 fast_dll |= dll_cnt;            /* Current lock mode */
 155         }
 156         /* set fast timings with DLL filter disabled */
 157         mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
 158
 159         /* No disruptions, DDR will be offline & C-ABI not followed */
 160         omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
 161                             mem_timings.fast_dll_ctrl,
 162                             mem_timings.base_cs,
 163                             force_lock_to_unlock_mode);
 164         mem_timings.slow_dll_ctrl &= 0xff00;    /* Keep lock value */
 165
 166         /* Turn status into unlock ctrl */
 167         mem_timings.slow_dll_ctrl |=
 168                 ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
 169
 170         /* 90 degree phase for anything below 133Mhz + disable DLL filter */
 171         mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
 172 }