2 * arch/arm/mach-omap2/serial.c
4 * OMAP2 serial support.
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * Major rework for PM support by Kevin Hilman
11 * Based off of arch/arm/mach-omap/omap1/serial.c
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/serial_8250.h>
23 #include <linux/serial_reg.h>
24 #include <linux/clk.h>
26 #include <linux/delay.h>
28 #include <plat/common.h>
29 #include <plat/board.h>
30 #include <plat/clock.h>
31 #include <plat/control.h>
35 #include "prm-regbits-34xx.h"
37 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
38 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
40 #define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0)
41 #define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1)
44 * NOTE: By default the serial timeout is disabled as it causes lost characters
45 * over the serial ports. This means that the UART clocks will stay on until
46 * disabled via sysfs. This also causes that any deeper omap sleep states are
49 #define DEFAULT_TIMEOUT 0
51 struct omap_uart_state
{
54 struct timer_list timer
;
66 struct plat_serial8250_port
*p
;
67 struct list_head node
;
68 struct platform_device pdev
;
71 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
74 /* Registers to be saved/restored for OFF-mode */
85 static LIST_HEAD(uart_list
);
87 static struct plat_serial8250_port serial_platform_data0
[] = {
90 .flags
= UPF_BOOT_AUTOCONF
,
93 .uartclk
= OMAP24XX_BASE_BAUD
* 16,
99 static struct plat_serial8250_port serial_platform_data1
[] = {
102 .flags
= UPF_BOOT_AUTOCONF
,
105 .uartclk
= OMAP24XX_BASE_BAUD
* 16,
111 static struct plat_serial8250_port serial_platform_data2
[] = {
114 .flags
= UPF_BOOT_AUTOCONF
,
117 .uartclk
= OMAP24XX_BASE_BAUD
* 16,
123 static struct plat_serial8250_port serial_platform_data3
[] = {
126 .flags
= UPF_BOOT_AUTOCONF
,
129 .uartclk
= OMAP24XX_BASE_BAUD
* 16,
135 void __init
omap2_set_globals_uart(struct omap_globals
*omap2_globals
)
137 serial_platform_data0
[0].mapbase
= omap2_globals
->uart1_phys
;
138 serial_platform_data1
[0].mapbase
= omap2_globals
->uart2_phys
;
139 serial_platform_data2
[0].mapbase
= omap2_globals
->uart3_phys
;
140 serial_platform_data3
[0].mapbase
= omap2_globals
->uart4_phys
;
143 static inline unsigned int __serial_read_reg(struct uart_port
*up
,
146 offset
<<= up
->regshift
;
147 return (unsigned int)__raw_readb(up
->membase
+ offset
);
150 static inline unsigned int serial_read_reg(struct plat_serial8250_port
*up
,
153 offset
<<= up
->regshift
;
154 return (unsigned int)__raw_readb(up
->membase
+ offset
);
157 static inline void __serial_write_reg(struct uart_port
*up
, int offset
,
160 offset
<<= up
->regshift
;
161 __raw_writeb(value
, up
->membase
+ offset
);
164 static inline void serial_write_reg(struct plat_serial8250_port
*p
, int offset
,
167 offset
<<= p
->regshift
;
168 __raw_writeb(value
, p
->membase
+ offset
);
172 * Internal UARTs need to be initialized for the 8250 autoconfig to work
173 * properly. Note that the TX watermark initialization may not be needed
174 * once the 8250.c watermark handling code is merged.
176 static inline void __init
omap_uart_reset(struct omap_uart_state
*uart
)
178 struct plat_serial8250_port
*p
= uart
->p
;
180 serial_write_reg(p
, UART_OMAP_MDR1
, 0x07);
181 serial_write_reg(p
, UART_OMAP_SCR
, 0x08);
182 serial_write_reg(p
, UART_OMAP_MDR1
, 0x00);
183 serial_write_reg(p
, UART_OMAP_SYSC
, (0x02 << 3) | (1 << 2) | (1 << 0));
186 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
189 * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
190 * The access to uart register after MDR1 Access
191 * causes UART to corrupt data.
194 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
195 * give 10 times as much
197 static void omap_uart_mdr1_errataset(struct omap_uart_state
*uart
, u8 mdr1_val
,
200 struct plat_serial8250_port
*p
= uart
->p
;
203 serial_write_reg(p
, UART_OMAP_MDR1
, mdr1_val
);
205 serial_write_reg(p
, UART_FCR
, fcr_val
| UART_FCR_CLEAR_XMIT
|
206 UART_FCR_CLEAR_RCVR
);
208 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
209 * TX_FIFO_E bit is 1.
211 while (UART_LSR_THRE
!= (serial_read_reg(p
, UART_LSR
) &
212 (UART_LSR_THRE
| UART_LSR_DR
))) {
215 /* Should *never* happen. we warn and carry on */
216 dev_crit(&uart
->pdev
.dev
, "Errata i202: timedout %x\n",
217 serial_read_reg(p
, UART_LSR
));
224 static void omap_uart_save_context(struct omap_uart_state
*uart
)
227 struct plat_serial8250_port
*p
= uart
->p
;
229 if (!enable_off_mode
)
232 lcr
= serial_read_reg(p
, UART_LCR
);
233 serial_write_reg(p
, UART_LCR
, 0xBF);
234 uart
->dll
= serial_read_reg(p
, UART_DLL
);
235 uart
->dlh
= serial_read_reg(p
, UART_DLM
);
236 serial_write_reg(p
, UART_LCR
, lcr
);
237 uart
->ier
= serial_read_reg(p
, UART_IER
);
238 uart
->sysc
= serial_read_reg(p
, UART_OMAP_SYSC
);
239 uart
->scr
= serial_read_reg(p
, UART_OMAP_SCR
);
240 uart
->wer
= serial_read_reg(p
, UART_OMAP_WER
);
241 serial_write_reg(p
, UART_LCR
, 0x80);
242 uart
->mcr
= serial_read_reg(p
, UART_MCR
);
243 serial_write_reg(p
, UART_LCR
, lcr
);
245 uart
->context_valid
= 1;
248 static void omap_uart_restore_context(struct omap_uart_state
*uart
)
251 struct plat_serial8250_port
*p
= uart
->p
;
253 if (!enable_off_mode
)
256 if (!uart
->context_valid
)
259 uart
->context_valid
= 0;
261 if (uart
->errata
& UART_ERRATA_i202_MDR1_ACCESS
)
262 omap_uart_mdr1_errataset(uart
, 0x07, 0xA0);
264 serial_write_reg(p
, UART_OMAP_MDR1
, 0x7);
265 serial_write_reg(p
, UART_LCR
, 0xBF); /* Config B mode */
266 efr
= serial_read_reg(p
, UART_EFR
);
267 serial_write_reg(p
, UART_EFR
, UART_EFR_ECB
);
268 serial_write_reg(p
, UART_LCR
, 0x0); /* Operational mode */
269 serial_write_reg(p
, UART_IER
, 0x0);
270 serial_write_reg(p
, UART_LCR
, 0xBF); /* Config B mode */
271 serial_write_reg(p
, UART_DLL
, uart
->dll
);
272 serial_write_reg(p
, UART_DLM
, uart
->dlh
);
273 serial_write_reg(p
, UART_LCR
, 0x0); /* Operational mode */
274 serial_write_reg(p
, UART_IER
, uart
->ier
);
275 serial_write_reg(p
, UART_LCR
, 0x80);
276 serial_write_reg(p
, UART_MCR
, uart
->mcr
);
277 serial_write_reg(p
, UART_LCR
, 0xBF); /* Config B mode */
278 serial_write_reg(p
, UART_EFR
, efr
);
279 serial_write_reg(p
, UART_LCR
, UART_LCR_WLEN8
);
280 serial_write_reg(p
, UART_OMAP_SCR
, uart
->scr
);
281 serial_write_reg(p
, UART_OMAP_WER
, uart
->wer
);
282 serial_write_reg(p
, UART_OMAP_SYSC
, uart
->sysc
);
283 if (uart
->errata
& UART_ERRATA_i202_MDR1_ACCESS
)
284 omap_uart_mdr1_errataset(uart
, 0x00, 0xA1);
286 serial_write_reg(p
, UART_OMAP_MDR1
, 0x00); /* UART 16x mode */
289 static inline void omap_uart_save_context(struct omap_uart_state
*uart
) {}
290 static inline void omap_uart_restore_context(struct omap_uart_state
*uart
) {}
291 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
293 static inline void omap_uart_enable_clocks(struct omap_uart_state
*uart
)
298 clk_enable(uart
->ick
);
299 clk_enable(uart
->fck
);
301 omap_uart_restore_context(uart
);
306 static inline void omap_uart_disable_clocks(struct omap_uart_state
*uart
)
311 omap_uart_save_context(uart
);
313 clk_disable(uart
->ick
);
314 clk_disable(uart
->fck
);
317 static void omap_uart_enable_wakeup(struct omap_uart_state
*uart
)
319 /* Set wake-enable bit */
320 if (uart
->wk_en
&& uart
->wk_mask
) {
321 u32 v
= __raw_readl(uart
->wk_en
);
323 __raw_writel(v
, uart
->wk_en
);
326 /* Ensure IOPAD wake-enables are set */
327 if (cpu_is_omap34xx() && uart
->padconf
) {
328 u16 v
= omap_ctrl_readw(uart
->padconf
);
329 v
|= OMAP3_PADCONF_WAKEUPENABLE0
;
330 omap_ctrl_writew(v
, uart
->padconf
);
334 static void omap_uart_disable_wakeup(struct omap_uart_state
*uart
)
336 /* Clear wake-enable bit */
337 if (uart
->wk_en
&& uart
->wk_mask
) {
338 u32 v
= __raw_readl(uart
->wk_en
);
340 __raw_writel(v
, uart
->wk_en
);
343 /* Ensure IOPAD wake-enables are cleared */
344 if (cpu_is_omap34xx() && uart
->padconf
) {
345 u16 v
= omap_ctrl_readw(uart
->padconf
);
346 v
&= ~OMAP3_PADCONF_WAKEUPENABLE0
;
347 omap_ctrl_writew(v
, uart
->padconf
);
351 static void omap_uart_smart_idle_enable(struct omap_uart_state
*uart
,
354 struct plat_serial8250_port
*p
= uart
->p
;
357 sysc
= serial_read_reg(p
, UART_OMAP_SYSC
) & 0x7;
363 serial_write_reg(p
, UART_OMAP_SYSC
, sysc
);
366 static void omap_uart_block_sleep(struct omap_uart_state
*uart
)
368 omap_uart_enable_clocks(uart
);
370 omap_uart_smart_idle_enable(uart
, 0);
373 mod_timer(&uart
->timer
, jiffies
+ uart
->timeout
);
375 del_timer(&uart
->timer
);
378 static void omap_uart_allow_sleep(struct omap_uart_state
*uart
)
380 if (device_may_wakeup(&uart
->pdev
.dev
))
381 omap_uart_enable_wakeup(uart
);
383 omap_uart_disable_wakeup(uart
);
388 omap_uart_smart_idle_enable(uart
, 1);
390 del_timer(&uart
->timer
);
393 static void omap_uart_idle_timer(unsigned long data
)
395 struct omap_uart_state
*uart
= (struct omap_uart_state
*)data
;
397 omap_uart_allow_sleep(uart
);
400 void omap_uart_prepare_idle(int num
)
402 struct omap_uart_state
*uart
;
404 list_for_each_entry(uart
, &uart_list
, node
) {
405 if (num
== uart
->num
&& uart
->can_sleep
) {
406 omap_uart_disable_clocks(uart
);
412 void omap_uart_resume_idle(int num
)
414 struct omap_uart_state
*uart
;
416 list_for_each_entry(uart
, &uart_list
, node
) {
417 if (num
== uart
->num
) {
418 omap_uart_enable_clocks(uart
);
420 /* Check for IO pad wakeup */
421 if (cpu_is_omap34xx() && uart
->padconf
) {
422 u16 p
= omap_ctrl_readw(uart
->padconf
);
424 if (p
& OMAP3_PADCONF_WAKEUPEVENT0
)
425 omap_uart_block_sleep(uart
);
428 /* Check for normal UART wakeup */
429 if (__raw_readl(uart
->wk_st
) & uart
->wk_mask
)
430 omap_uart_block_sleep(uart
);
436 void omap_uart_prepare_suspend(void)
438 struct omap_uart_state
*uart
;
440 list_for_each_entry(uart
, &uart_list
, node
) {
441 omap_uart_allow_sleep(uart
);
445 int omap_uart_can_sleep(void)
447 struct omap_uart_state
*uart
;
450 list_for_each_entry(uart
, &uart_list
, node
) {
454 if (!uart
->can_sleep
) {
459 /* This UART can now safely sleep. */
460 omap_uart_allow_sleep(uart
);
467 * omap_uart_interrupt()
469 * This handler is used only to detect that *any* UART interrupt has
470 * occurred. It does _nothing_ to handle the interrupt. Rather,
471 * any UART interrupt will trigger the inactivity timer so the
472 * UART will not idle or sleep for its timeout period.
475 static irqreturn_t
omap_uart_interrupt(int irq
, void *dev_id
)
477 struct omap_uart_state
*uart
= dev_id
;
479 omap_uart_block_sleep(uart
);
484 static void omap_uart_idle_init(struct omap_uart_state
*uart
)
486 struct plat_serial8250_port
*p
= uart
->p
;
490 uart
->timeout
= DEFAULT_TIMEOUT
;
491 setup_timer(&uart
->timer
, omap_uart_idle_timer
,
492 (unsigned long) uart
);
494 mod_timer(&uart
->timer
, jiffies
+ uart
->timeout
);
495 omap_uart_smart_idle_enable(uart
, 0);
497 if (cpu_is_omap34xx()) {
498 u32 mod
= (uart
->num
== 2) ? OMAP3430_PER_MOD
: CORE_MOD
;
502 uart
->wk_en
= OMAP34XX_PRM_REGADDR(mod
, PM_WKEN1
);
503 uart
->wk_st
= OMAP34XX_PRM_REGADDR(mod
, PM_WKST1
);
506 wk_mask
= OMAP3430_ST_UART1_MASK
;
510 wk_mask
= OMAP3430_ST_UART2_MASK
;
514 wk_mask
= OMAP3430_ST_UART3_MASK
;
518 uart
->wk_mask
= wk_mask
;
519 uart
->padconf
= padconf
;
520 } else if (cpu_is_omap24xx()) {
523 if (cpu_is_omap2430()) {
524 uart
->wk_en
= OMAP2430_PRM_REGADDR(CORE_MOD
, PM_WKEN1
);
525 uart
->wk_st
= OMAP2430_PRM_REGADDR(CORE_MOD
, PM_WKST1
);
526 } else if (cpu_is_omap2420()) {
527 uart
->wk_en
= OMAP2420_PRM_REGADDR(CORE_MOD
, PM_WKEN1
);
528 uart
->wk_st
= OMAP2420_PRM_REGADDR(CORE_MOD
, PM_WKST1
);
532 wk_mask
= OMAP24XX_ST_UART1_MASK
;
535 wk_mask
= OMAP24XX_ST_UART2_MASK
;
538 wk_mask
= OMAP24XX_ST_UART3_MASK
;
541 uart
->wk_mask
= wk_mask
;
549 p
->irqflags
|= IRQF_SHARED
;
550 ret
= request_irq(p
->irq
, omap_uart_interrupt
, IRQF_SHARED
,
551 "serial idle", (void *)uart
);
555 void omap_uart_enable_irqs(int enable
)
558 struct omap_uart_state
*uart
;
560 list_for_each_entry(uart
, &uart_list
, node
) {
562 ret
= request_irq(uart
->p
->irq
, omap_uart_interrupt
,
563 IRQF_SHARED
, "serial idle", (void *)uart
);
565 free_irq(uart
->p
->irq
, (void *)uart
);
569 static ssize_t
sleep_timeout_show(struct device
*dev
,
570 struct device_attribute
*attr
,
573 struct platform_device
*pdev
= container_of(dev
,
574 struct platform_device
, dev
);
575 struct omap_uart_state
*uart
= container_of(pdev
,
576 struct omap_uart_state
, pdev
);
578 return sprintf(buf
, "%u\n", uart
->timeout
/ HZ
);
581 static ssize_t
sleep_timeout_store(struct device
*dev
,
582 struct device_attribute
*attr
,
583 const char *buf
, size_t n
)
585 struct platform_device
*pdev
= container_of(dev
,
586 struct platform_device
, dev
);
587 struct omap_uart_state
*uart
= container_of(pdev
,
588 struct omap_uart_state
, pdev
);
591 if (sscanf(buf
, "%u", &value
) != 1) {
592 dev_err(dev
, "sleep_timeout_store: Invalid value\n");
596 uart
->timeout
= value
* HZ
;
598 mod_timer(&uart
->timer
, jiffies
+ uart
->timeout
);
600 /* A zero value means disable timeout feature */
601 omap_uart_block_sleep(uart
);
606 static DEVICE_ATTR(sleep_timeout
, 0644, sleep_timeout_show
,
607 sleep_timeout_store
);
608 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
610 static inline void omap_uart_idle_init(struct omap_uart_state
*uart
) {}
611 #define DEV_CREATE_FILE(dev, attr)
612 #endif /* CONFIG_PM */
614 static struct omap_uart_state omap_uart
[] = {
617 .name
= "serial8250",
618 .id
= PLAT8250_DEV_PLATFORM
,
620 .platform_data
= serial_platform_data0
,
625 .name
= "serial8250",
626 .id
= PLAT8250_DEV_PLATFORM1
,
628 .platform_data
= serial_platform_data1
,
633 .name
= "serial8250",
634 .id
= PLAT8250_DEV_PLATFORM2
,
636 .platform_data
= serial_platform_data2
,
640 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
643 .name
= "serial8250",
646 .platform_data
= serial_platform_data3
,
654 * Override the default 8250 read handler: mem_serial_in()
655 * Empty RX fifo read causes an abort on omap3630 and omap4
656 * This function makes sure that an empty rx fifo is not read on these silicons
657 * (OMAP1/2/3430 are not affected)
659 static unsigned int serial_in_override(struct uart_port
*up
, int offset
)
661 if (UART_RX
== offset
) {
663 lsr
= __serial_read_reg(up
, UART_LSR
);
664 if (!(lsr
& UART_LSR_DR
))
668 return __serial_read_reg(up
, offset
);
671 static void serial_out_override(struct uart_port
*up
, int offset
, int value
)
673 unsigned int status
, tmout
= 10000;
675 status
= __serial_read_reg(up
, UART_LSR
);
676 while (!(status
& UART_LSR_THRE
)) {
677 /* Wait up to 10ms for the character(s) to be sent. */
681 status
= __serial_read_reg(up
, UART_LSR
);
683 __serial_write_reg(up
, offset
, value
);
685 void __init
omap_serial_early_init(void)
690 if (!(cpu_is_omap3630() || cpu_is_omap4430()))
693 nr_ports
= ARRAY_SIZE(omap_uart
);
696 * Make sure the serial ports are muxed on at this point.
697 * You have to mux them off in device drivers later on
701 for (i
= 0; i
< nr_ports
; i
++) {
702 struct omap_uart_state
*uart
= &omap_uart
[i
];
703 struct platform_device
*pdev
= &uart
->pdev
;
704 struct device
*dev
= &pdev
->dev
;
705 struct plat_serial8250_port
*p
= dev
->platform_data
;
707 /* Don't map zero-based physical address */
708 if (p
->mapbase
== 0) {
709 dev_warn(dev
, "no physical address for uart#%d,"
710 " so skipping early_init...\n", i
);
714 * Module 4KB + L4 interconnect 4KB
715 * Static mapping, never released
717 p
->membase
= ioremap(p
->mapbase
, SZ_8K
);
719 dev_err(dev
, "ioremap failed for uart%i\n", i
+ 1);
723 sprintf(name
, "uart%d_ick", i
+ 1);
724 uart
->ick
= clk_get(NULL
, name
);
725 if (IS_ERR(uart
->ick
)) {
726 dev_err(dev
, "Could not get uart%d_ick\n", i
+ 1);
730 sprintf(name
, "uart%d_fck", i
+1);
731 uart
->fck
= clk_get(NULL
, name
);
732 if (IS_ERR(uart
->fck
)) {
733 dev_err(dev
, "Could not get uart%d_fck\n", i
+ 1);
737 /* FIXME: Remove this once the clkdev is ready */
738 if (!cpu_is_omap44xx()) {
739 if (!uart
->ick
|| !uart
->fck
)
744 p
->private_data
= uart
;
747 if (cpu_is_omap44xx())
753 * omap_serial_init_port() - initialize single serial port
754 * @port: serial port number (0-3)
756 * This function initialies serial driver for given @port only.
757 * Platforms can call this function instead of omap_serial_init()
758 * if they don't plan to use all available UARTs as serial ports.
760 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
761 * use only one of the two.
763 void __init
omap_serial_init_port(int port
)
765 struct omap_uart_state
*uart
;
766 struct platform_device
*pdev
;
770 BUG_ON(port
>= ARRAY_SIZE(omap_uart
));
772 uart
= &omap_uart
[port
];
776 /* Don't proceed if there's no clocks available */
777 if (unlikely(!uart
->ick
|| !uart
->fck
)) {
778 WARN(1, "%s: can't init uart%d, no clocks available\n",
779 kobject_name(&dev
->kobj
), port
);
783 omap_uart_enable_clocks(uart
);
785 omap_uart_reset(uart
);
786 omap_uart_idle_init(uart
);
788 list_add_tail(&uart
->node
, &uart_list
);
790 if (WARN_ON(platform_device_register(pdev
)))
793 if ((cpu_is_omap34xx() && uart
->padconf
) ||
794 (uart
->wk_en
&& uart
->wk_mask
)) {
795 device_init_wakeup(dev
, true);
796 DEV_CREATE_FILE(dev
, &dev_attr_sleep_timeout
);
800 * omap44xx: Never read empty UART fifo
801 * omap3xxx: Never read empty UART fifo on UARTs
804 if (cpu_is_omap44xx())
805 uart
->errata
|= UART_ERRATA_FIFO_FULL_ABORT
;
806 else if ((serial_read_reg(uart
->p
, UART_OMAP_MVER
) & 0xFF)
807 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV
)
808 uart
->errata
|= UART_ERRATA_FIFO_FULL_ABORT
;
810 if (uart
->errata
& UART_ERRATA_FIFO_FULL_ABORT
) {
811 uart
->p
->serial_in
= serial_in_override
;
812 uart
->p
->serial_out
= serial_out_override
;
815 /* Enable the MDR1 errata for OMAP3 */
816 if (cpu_is_omap34xx())
817 uart
->errata
|= UART_ERRATA_i202_MDR1_ACCESS
;
821 * omap_serial_init() - intialize all supported serial ports
823 * Initializes all available UARTs as serial ports. Platforms
824 * can call this function when they want to have default behaviour
825 * for serial ports (e.g initialize them all as serial ports).
827 void __init
omap_serial_init(void)
831 if (!(cpu_is_omap3630() || cpu_is_omap4430()))
834 nr_ports
= ARRAY_SIZE(omap_uart
);
836 for (i
= 0; i
< nr_ports
; i
++)
837 omap_serial_init_port(i
);