arch/arm/mach-omap2/timer.c

   1 /*
   2  * linux/arch/arm/mach-omap2/timer.c
   3  *
   4  * OMAP2 GP timer support.
   5  *
   6  * Copyright (C) 2009 Nokia Corporation
   7  *
   8  * Update to use new clocksource/clockevent layers
   9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  10  * Copyright (C) 2007 MontaVista Software, Inc.
  11  *
  12  * Original driver:
  13  * Copyright (C) 2005 Nokia Corporation
  14  * Author: Paul Mundt <paul.mundt@nokia.com>
  15  *         Juha Yrjölä <juha.yrjola@nokia.com>
  16  * OMAP Dual-mode timer framework support by Timo Teras
  17  *
  18  * Some parts based off of TI's 24xx code:
  19  *
  20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
  21  *
  22  * Roughly modelled after the OMAP1 MPU timer code.
  23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  24  *
  25  * This file is subject to the terms and conditions of the GNU General Public
  26  * License. See the file "COPYING" in the main directory of this archive
  27  * for more details.
  28  */
  29 #include <linux/init.h>
  30 #include <linux/time.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <linux/irq.h>
  36 #include <linux/clocksource.h>
  37 #include <linux/clockchips.h>
  38 #include <linux/slab.h>
  39
  40 #include <asm/mach/time.h>
  41 #include <plat/dmtimer.h>
  42 #include <asm/smp_twd.h>
  43 #include <asm/sched_clock.h>
  44 #include "common.h"
  45 #include <plat/omap_hwmod.h>
  46 #include <plat/omap_device.h>
  47 #include <plat/omap-pm.h>
  48
  49 #include "powerdomain.h"
  50
  51 /* Parent clocks, eventually these will come from the clock framework */
  52
  53 #define OMAP2_MPU_SOURCE        "sys_ck"
  54 #define OMAP3_MPU_SOURCE        OMAP2_MPU_SOURCE
  55 #define OMAP4_MPU_SOURCE        "sys_clkin_ck"
  56 #define OMAP2_32K_SOURCE        "func_32k_ck"
  57 #define OMAP3_32K_SOURCE        "omap_32k_fck"
  58 #define OMAP4_32K_SOURCE        "sys_32k_ck"
  59
  60 #ifdef CONFIG_OMAP_32K_TIMER
  61 #define OMAP2_CLKEV_SOURCE      OMAP2_32K_SOURCE
  62 #define OMAP3_CLKEV_SOURCE      OMAP3_32K_SOURCE
  63 #define OMAP4_CLKEV_SOURCE      OMAP4_32K_SOURCE
  64 #define OMAP3_SECURE_TIMER      12
  65 #else
  66 #define OMAP2_CLKEV_SOURCE      OMAP2_MPU_SOURCE
  67 #define OMAP3_CLKEV_SOURCE      OMAP3_MPU_SOURCE
  68 #define OMAP4_CLKEV_SOURCE      OMAP4_MPU_SOURCE
  69 #define OMAP3_SECURE_TIMER      1
  70 #endif
  71
  72 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
  73 #define MAX_GPTIMER_ID          12
  74
  75 static u32 sys_timer_reserved;
  76
  77 /* Clockevent code */
  78
  79 static struct omap_dm_timer clkev;
  80 static struct clock_event_device clockevent_gpt;
  81
  82 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  83 {
  84         struct clock_event_device *evt = &clockevent_gpt;
  85
  86         __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
  87
  88         evt->event_handler(evt);
  89         return IRQ_HANDLED;
  90 }
  91
  92 static struct irqaction omap2_gp_timer_irq = {
  93         .name           = "gp_timer",
  94         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  95         .handler        = omap2_gp_timer_interrupt,
  96 };
  97
  98 static int omap2_gp_timer_set_next_event(unsigned long cycles,
  99                                          struct clock_event_device *evt)
 100 {
 101         __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
 102                                                 0xffffffff - cycles, 1);
 103
 104         return 0;
 105 }
 106
 107 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 108                                     struct clock_event_device *evt)
 109 {
 110         u32 period;
 111
 112         __omap_dm_timer_stop(&clkev, 1, clkev.rate);
 113
 114         switch (mode) {
 115         case CLOCK_EVT_MODE_PERIODIC:
 116                 period = clkev.rate / HZ;
 117                 period -= 1;
 118                 /* Looks like we need to first set the load value separately */
 119                 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
 120                                         0xffffffff - period, 1);
 121                 __omap_dm_timer_load_start(&clkev,
 122                                         OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
 123                                                 0xffffffff - period, 1);
 124                 break;
 125         case CLOCK_EVT_MODE_ONESHOT:
 126                 break;
 127         case CLOCK_EVT_MODE_UNUSED:
 128         case CLOCK_EVT_MODE_SHUTDOWN:
 129         case CLOCK_EVT_MODE_RESUME:
 130                 break;
 131         }
 132 }
 133
 134 static struct clock_event_device clockevent_gpt = {
 135         .name           = "gp_timer",
 136         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 137         .shift          = 32,
 138         .set_next_event = omap2_gp_timer_set_next_event,
 139         .set_mode       = omap2_gp_timer_set_mode,
 140 };
 141
 142 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 143                                                 int gptimer_id,
 144                                                 const char *fck_source)
 145 {
 146         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
 147         struct omap_hwmod *oh;
 148         struct resource irq_rsrc, mem_rsrc;
 149         size_t size;
 150         int res = 0;
 151         int r;
 152
 153         sprintf(name, "timer%d", gptimer_id);
 154         omap_hwmod_setup_one(name);
 155         oh = omap_hwmod_lookup(name);
 156         if (!oh)
 157                 return -ENODEV;
 158
 159         r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
 160         if (r)
 161                 return -ENXIO;
 162         timer->irq = irq_rsrc.start;
 163
 164         r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
 165         if (r)
 166                 return -ENXIO;
 167         timer->phys_base = mem_rsrc.start;
 168         size = mem_rsrc.end - mem_rsrc.start;
 169
 170         /* Static mapping, never released */
 171         timer->io_base = ioremap(timer->phys_base, size);
 172         if (!timer->io_base)
 173                 return -ENXIO;
 174
 175         /* After the dmtimer is using hwmod these clocks won't be needed */
 176         sprintf(name, "gpt%d_fck", gptimer_id);
 177         timer->fclk = clk_get(NULL, name);
 178         if (IS_ERR(timer->fclk))
 179                 return -ENODEV;
 180
 181         omap_hwmod_enable(oh);
 182
 183         sys_timer_reserved |= (1 << (gptimer_id - 1));
 184
 185         if (gptimer_id != 12) {
 186                 struct clk *src;
 187
 188                 src = clk_get(NULL, fck_source);
 189                 if (IS_ERR(src)) {
 190                         res = -EINVAL;
 191                 } else {
 192                         res = __omap_dm_timer_set_source(timer->fclk, src);
 193                         if (IS_ERR_VALUE(res))
 194                                 pr_warning("%s: timer%i cannot set source\n",
 195                                                 __func__, gptimer_id);
 196                         clk_put(src);
 197                 }
 198         }
 199         __omap_dm_timer_init_regs(timer);
 200         __omap_dm_timer_reset(timer, 1, 1);
 201         timer->posted = 1;
 202
 203         timer->rate = clk_get_rate(timer->fclk);
 204
 205         timer->reserved = 1;
 206
 207         return res;
 208 }
 209
 210 static void __init omap2_gp_clockevent_init(int gptimer_id,
 211                                                 const char *fck_source)
 212 {
 213         int res;
 214
 215         res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
 216         BUG_ON(res);
 217
 218         omap2_gp_timer_irq.dev_id = (void *)&clkev;
 219         setup_irq(clkev.irq, &omap2_gp_timer_irq);
 220
 221         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
 222
 223         clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
 224                                      clockevent_gpt.shift);
 225         clockevent_gpt.max_delta_ns =
 226                 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
 227         clockevent_gpt.min_delta_ns =
 228                 clockevent_delta2ns(3, &clockevent_gpt);
 229                 /* Timer internal resynch latency. */
 230
 231         clockevent_gpt.cpumask = cpumask_of(0);
 232         clockevents_register_device(&clockevent_gpt);
 233
 234         pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
 235                 gptimer_id, clkev.rate);
 236 }
 237
 238 /* Clocksource code */
 239 static struct omap_dm_timer clksrc;
 240 static bool use_gptimer_clksrc;
 241
 242 /*
 243  * clocksource
 244  */
 245 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 246 {
 247         return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
 248 }
 249
 250 static struct clocksource clocksource_gpt = {
 251         .name           = "gp_timer",
 252         .rating         = 300,
 253         .read           = clocksource_read_cycles,
 254         .mask           = CLOCKSOURCE_MASK(32),
 255         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 256 };
 257
 258 static u32 notrace dmtimer_read_sched_clock(void)
 259 {
 260         if (clksrc.reserved)
 261                 return __omap_dm_timer_read_counter(&clksrc, 1);
 262
 263         return 0;
 264 }
 265
 266 /* Setup free-running counter for clocksource */
 267 static int __init omap2_sync32k_clocksource_init(void)
 268 {
 269         int ret;
 270         struct omap_hwmod *oh;
 271         void __iomem *vbase;
 272         const char *oh_name = "counter_32k";
 273
 274         /*
 275          * First check hwmod data is available for sync32k counter
 276          */
 277         oh = omap_hwmod_lookup(oh_name);
 278         if (!oh || oh->slaves_cnt == 0)
 279                 return -ENODEV;
 280
 281         omap_hwmod_setup_one(oh_name);
 282
 283         vbase = omap_hwmod_get_mpu_rt_va(oh);
 284         if (!vbase) {
 285                 pr_warn("%s: failed to get counter_32k resource\n", __func__);
 286                 return -ENXIO;
 287         }
 288
 289         ret = omap_hwmod_enable(oh);
 290         if (ret) {
 291                 pr_warn("%s: failed to enable counter_32k module (%d)\n",
 292                                                         __func__, ret);
 293                 return ret;
 294         }
 295
 296         ret = omap_init_clocksource_32k(vbase);
 297         if (ret) {
 298                 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
 299                                                         __func__, ret);
 300                 omap_hwmod_idle(oh);
 301         }
 302
 303         return ret;
 304 }
 305
 306 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
 307                                                 const char *fck_source)
 308 {
 309         int res;
 310
 311         res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
 312         BUG_ON(res);
 313
 314         __omap_dm_timer_load_start(&clksrc,
 315                         OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
 316         setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
 317
 318         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
 319                 pr_err("Could not register clocksource %s\n",
 320                         clocksource_gpt.name);
 321         else
 322                 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
 323                         gptimer_id, clksrc.rate);
 324 }
 325
 326 static void __init omap2_clocksource_init(int gptimer_id,
 327                                                 const char *fck_source)
 328 {
 329         /*
 330          * First give preference to kernel parameter configuration
 331          * by user (clocksource="gp_timer").
 332          *
 333          * In case of missing kernel parameter for clocksource,
 334          * first check for availability for 32k-sync timer, in case
 335          * of failure in finding 32k_counter module or registering
 336          * it as clocksource, execution will fallback to gp-timer.
 337          */
 338         if (use_gptimer_clksrc == true)
 339                 omap2_gptimer_clocksource_init(gptimer_id, fck_source);
 340         else if (omap2_sync32k_clocksource_init())
 341                 /* Fall back to gp-timer code */
 342                 omap2_gptimer_clocksource_init(gptimer_id, fck_source);
 343 }
 344
 345 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,                  \
 346                                 clksrc_nr, clksrc_src)                  \
 347 static void __init omap##name##_timer_init(void)                        \
 348 {                                                                       \
 349         omap2_gp_clockevent_init((clkev_nr), clkev_src);                \
 350         omap2_clocksource_init((clksrc_nr), clksrc_src);                \
 351 }
 352
 353 #define OMAP_SYS_TIMER(name)                                            \
 354 struct sys_timer omap##name##_timer = {                                 \
 355         .init   = omap##name##_timer_init,                              \
 356 };
 357
 358 #ifdef CONFIG_ARCH_OMAP2
 359 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
 360 OMAP_SYS_TIMER(2)
 361 #endif
 362
 363 #ifdef CONFIG_ARCH_OMAP3
 364 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
 365 OMAP_SYS_TIMER(3)
 366 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
 367                         2, OMAP3_MPU_SOURCE)
 368 OMAP_SYS_TIMER(3_secure)
 369 #endif
 370
 371 #ifdef CONFIG_ARCH_OMAP4
 372 #ifdef CONFIG_LOCAL_TIMERS
 373 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
 374                               OMAP44XX_LOCAL_TWD_BASE,
 375                               OMAP44XX_IRQ_LOCALTIMER);
 376 #endif
 377
 378 static void __init omap4_timer_init(void)
 379 {
 380         omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
 381         omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
 382 #ifdef CONFIG_LOCAL_TIMERS
 383         /* Local timers are not supprted on OMAP4430 ES1.0 */
 384         if (omap_rev() != OMAP4430_REV_ES1_0) {
 385                 int err;
 386
 387                 err = twd_local_timer_register(&twd_local_timer);
 388                 if (err)
 389                         pr_err("twd_local_timer_register failed %d\n", err);
 390         }
 391 #endif
 392 }
 393 OMAP_SYS_TIMER(4)
 394 #endif
 395
 396 /**
 397  * omap2_dm_timer_set_src - change the timer input clock source
 398  * @pdev:       timer platform device pointer
 399  * @source:     array index of parent clock source
 400  */
 401 static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
 402 {
 403         int ret;
 404         struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
 405         struct clk *fclk, *parent;
 406         char *parent_name = NULL;
 407
 408         fclk = clk_get(&pdev->dev, "fck");
 409         if (IS_ERR_OR_NULL(fclk)) {
 410                 dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
 411                                 __func__, __LINE__);
 412                 return -EINVAL;
 413         }
 414
 415         switch (source) {
 416         case OMAP_TIMER_SRC_SYS_CLK:
 417                 parent_name = "sys_ck";
 418                 break;
 419
 420         case OMAP_TIMER_SRC_32_KHZ:
 421                 parent_name = "32k_ck";
 422                 break;
 423
 424         case OMAP_TIMER_SRC_EXT_CLK:
 425                 if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
 426                         parent_name = "alt_ck";
 427                         break;
 428                 }
 429                 dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
 430                         __func__, __LINE__);
 431                 clk_put(fclk);
 432                 return -EINVAL;
 433         }
 434
 435         parent = clk_get(&pdev->dev, parent_name);
 436         if (IS_ERR_OR_NULL(parent)) {
 437                 dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
 438                         __func__, __LINE__, parent_name);
 439                 clk_put(fclk);
 440                 return -EINVAL;
 441         }
 442
 443         ret = clk_set_parent(fclk, parent);
 444         if (IS_ERR_VALUE(ret)) {
 445                 dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
 446                         __func__, parent_name);
 447                 ret = -EINVAL;
 448         }
 449
 450         clk_put(parent);
 451         clk_put(fclk);
 452
 453         return ret;
 454 }
 455
 456 /**
 457  * omap_timer_init - build and register timer device with an
 458  * associated timer hwmod
 459  * @oh: timer hwmod pointer to be used to build timer device
 460  * @user:       parameter that can be passed from calling hwmod API
 461  *
 462  * Called by omap_hwmod_for_each_by_class to register each of the timer
 463  * devices present in the system. The number of timer devices is known
 464  * by parsing through the hwmod database for a given class name. At the
 465  * end of function call memory is allocated for timer device and it is
 466  * registered to the framework ready to be proved by the driver.
 467  */
 468 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
 469 {
 470         int id;
 471         int ret = 0;
 472         char *name = "omap_timer";
 473         struct dmtimer_platform_data *pdata;
 474         struct platform_device *pdev;
 475         struct omap_timer_capability_dev_attr *timer_dev_attr;
 476         struct powerdomain *pwrdm;
 477
 478         pr_debug("%s: %s\n", __func__, oh->name);
 479
 480         /* on secure device, do not register secure timer */
 481         timer_dev_attr = oh->dev_attr;
 482         if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
 483                 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
 484                         return ret;
 485
 486         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 487         if (!pdata) {
 488                 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
 489                 return -ENOMEM;
 490         }
 491
 492         /*
 493          * Extract the IDs from name field in hwmod database
 494          * and use the same for constructing ids' for the
 495          * timer devices. In a way, we are avoiding usage of
 496          * static variable witin the function to do the same.
 497          * CAUTION: We have to be careful and make sure the
 498          * name in hwmod database does not change in which case
 499          * we might either make corresponding change here or
 500          * switch back static variable mechanism.
 501          */
 502         sscanf(oh->name, "timer%2d", &id);
 503
 504         pdata->set_timer_src = omap2_dm_timer_set_src;
 505         pdata->timer_ip_version = oh->class->rev;
 506
 507         /* Mark clocksource and clockevent timers as reserved */
 508         if ((sys_timer_reserved >> (id - 1)) & 0x1)
 509                 pdata->reserved = 1;
 510
 511         pwrdm = omap_hwmod_get_pwrdm(oh);
 512         pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
 513 #ifdef CONFIG_PM
 514         pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
 515 #endif
 516         pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
 517                                  NULL, 0, 0);
 518
 519         if (IS_ERR(pdev)) {
 520                 pr_err("%s: Can't build omap_device for %s: %s.\n",
 521                         __func__, name, oh->name);
 522                 ret = -EINVAL;
 523         }
 524
 525         kfree(pdata);
 526
 527         return ret;
 528 }
 529
 530 /**
 531  * omap2_dm_timer_init - top level regular device initialization
 532  *
 533  * Uses dedicated hwmod api to parse through hwmod database for
 534  * given class name and then build and register the timer device.
 535  */
 536 static int __init omap2_dm_timer_init(void)
 537 {
 538         int ret;
 539
 540         ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
 541         if (unlikely(ret)) {
 542                 pr_err("%s: device registration failed.\n", __func__);
 543                 return -EINVAL;
 544         }
 545
 546         return 0;
 547 }
 548 arch_initcall(omap2_dm_timer_init);
 549
 550 /**
 551  * omap2_override_clocksource - clocksource override with user configuration
 552  *
 553  * Allows user to override default clocksource, using kernel parameter
 554  *   clocksource="gp_timer"     (For all OMAP2PLUS architectures)
 555  *
 556  * Note that, here we are using same standard kernel parameter "clocksource=",
 557  * and not introducing any OMAP specific interface.
 558  */
 559 static int __init omap2_override_clocksource(char *str)
 560 {
 561         if (!str)
 562                 return 0;
 563         /*
 564          * For OMAP architecture, we only have two options
 565          *    - sync_32k (default)
 566          *    - gp_timer (sys_clk based)
 567          */
 568         if (!strcmp(str, "gp_timer"))
 569                 use_gptimer_clksrc = true;
 570
 571         return 0;
 572 }
 573 early_param("clocksource", omap2_override_clocksource);