arch/arm/mach-omap2/timer.c

   1 /*
   2  * linux/arch/arm/mach-omap2/timer.c
   3  *
   4  * OMAP2 GP timer support.
   5  *
   6  * Copyright (C) 2009 Nokia Corporation
   7  *
   8  * Update to use new clocksource/clockevent layers
   9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  10  * Copyright (C) 2007 MontaVista Software, Inc.
  11  *
  12  * Original driver:
  13  * Copyright (C) 2005 Nokia Corporation
  14  * Author: Paul Mundt <paul.mundt@nokia.com>
  15  *         Juha Yrjölä <juha.yrjola@nokia.com>
  16  * OMAP Dual-mode timer framework support by Timo Teras
  17  *
  18  * Some parts based off of TI's 24xx code:
  19  *
  20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
  21  *
  22  * Roughly modelled after the OMAP1 MPU timer code.
  23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  24  *
  25  * This file is subject to the terms and conditions of the GNU General Public
  26  * License. See the file "COPYING" in the main directory of this archive
  27  * for more details.
  28  */
  29 #include <linux/init.h>
  30 #include <linux/time.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <linux/irq.h>
  36 #include <linux/clocksource.h>
  37 #include <linux/clockchips.h>
  38 #include <linux/slab.h>
  39 #include <linux/of.h>
  40 #include <linux/of_address.h>
  41 #include <linux/of_irq.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/platform_data/dmtimer-omap.h>
  44
  45 #include <asm/mach/time.h>
  46 #include <asm/smp_twd.h>
  47 #include <asm/sched_clock.h>
  48
  49 #include <asm/arch_timer.h>
  50 #include "omap_hwmod.h"
  51 #include "omap_device.h"
  52 #include <plat/counter-32k.h>
  53 #include <plat/dmtimer.h>
  54 #include "omap-pm.h"
  55
  56 #include "soc.h"
  57 #include "common.h"
  58 #include "powerdomain.h"
  59
  60 #define REALTIME_COUNTER_BASE                           0x48243200
  61 #define INCREMENTER_NUMERATOR_OFFSET                    0x10
  62 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
  63 #define NUMERATOR_DENUMERATOR_MASK                      0xfffff000
  64
  65 /* Clockevent code */
  66
  67 static struct omap_dm_timer clkev;
  68 static struct clock_event_device clockevent_gpt;
  69
  70 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  71 {
  72         struct clock_event_device *evt = &clockevent_gpt;
  73
  74         __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
  75
  76         evt->event_handler(evt);
  77         return IRQ_HANDLED;
  78 }
  79
  80 static struct irqaction omap2_gp_timer_irq = {
  81         .name           = "gp_timer",
  82         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  83         .handler        = omap2_gp_timer_interrupt,
  84 };
  85
  86 static int omap2_gp_timer_set_next_event(unsigned long cycles,
  87                                          struct clock_event_device *evt)
  88 {
  89         __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
  90                                    0xffffffff - cycles, OMAP_TIMER_POSTED);
  91
  92         return 0;
  93 }
  94
  95 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
  96                                     struct clock_event_device *evt)
  97 {
  98         u32 period;
  99
 100         __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
 101
 102         switch (mode) {
 103         case CLOCK_EVT_MODE_PERIODIC:
 104                 period = clkev.rate / HZ;
 105                 period -= 1;
 106                 /* Looks like we need to first set the load value separately */
 107                 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
 108                                       0xffffffff - period, OMAP_TIMER_POSTED);
 109                 __omap_dm_timer_load_start(&clkev,
 110                                         OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
 111                                         0xffffffff - period, OMAP_TIMER_POSTED);
 112                 break;
 113         case CLOCK_EVT_MODE_ONESHOT:
 114                 break;
 115         case CLOCK_EVT_MODE_UNUSED:
 116         case CLOCK_EVT_MODE_SHUTDOWN:
 117         case CLOCK_EVT_MODE_RESUME:
 118                 break;
 119         }
 120 }
 121
 122 static struct clock_event_device clockevent_gpt = {
 123         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 124         .shift          = 32,
 125         .rating         = 300,
 126         .set_next_event = omap2_gp_timer_set_next_event,
 127         .set_mode       = omap2_gp_timer_set_mode,
 128 };
 129
 130 static struct property device_disabled = {
 131         .name = "status",
 132         .length = sizeof("disabled"),
 133         .value = "disabled",
 134 };
 135
 136 static struct of_device_id omap_timer_match[] __initdata = {
 137         { .compatible = "ti,omap2-timer", },
 138         { }
 139 };
 140
 141 /**
 142  * omap_get_timer_dt - get a timer using device-tree
 143  * @match       - device-tree match structure for matching a device type
 144  * @property    - optional timer property to match
 145  *
 146  * Helper function to get a timer during early boot using device-tree for use
 147  * as kernel system timer. Optionally, the property argument can be used to
 148  * select a timer with a specific property. Once a timer is found then mark
 149  * the timer node in device-tree as disabled, to prevent the kernel from
 150  * registering this timer as a platform device and so no one else can use it.
 151  */
 152 static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
 153                                                      const char *property)
 154 {
 155         struct device_node *np;
 156
 157         for_each_matching_node(np, match) {
 158                 if (!of_device_is_available(np))
 159                         continue;
 160
 161                 if (property && !of_get_property(np, property, NULL))
 162                         continue;
 163
 164                 of_add_property(np, &device_disabled);
 165                 return np;
 166         }
 167
 168         return NULL;
 169 }
 170
 171 /**
 172  * omap_dmtimer_init - initialisation function when device tree is used
 173  *
 174  * For secure OMAP3 devices, timers with device type "timer-secure" cannot
 175  * be used by the kernel as they are reserved. Therefore, to prevent the
 176  * kernel registering these devices remove them dynamically from the device
 177  * tree on boot.
 178  */
 179 static void __init omap_dmtimer_init(void)
 180 {
 181         struct device_node *np;
 182
 183         if (!cpu_is_omap34xx())
 184                 return;
 185
 186         /* If we are a secure device, remove any secure timer nodes */
 187         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
 188                 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
 189                 if (np)
 190                         of_node_put(np);
 191         }
 192 }
 193
 194 /**
 195  * omap_dm_timer_get_errata - get errata flags for a timer
 196  *
 197  * Get the timer errata flags that are specific to the OMAP device being used.
 198  */
 199 static u32 __init omap_dm_timer_get_errata(void)
 200 {
 201         if (cpu_is_omap24xx())
 202                 return 0;
 203
 204         return OMAP_TIMER_ERRATA_I103_I767;
 205 }
 206
 207 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 208                                          int gptimer_id,
 209                                          const char *fck_source,
 210                                          const char *property,
 211                                          const char **timer_name,
 212                                          int posted)
 213 {
 214         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
 215         const char *oh_name;
 216         struct device_node *np;
 217         struct omap_hwmod *oh;
 218         struct resource irq, mem;
 219         struct clk *src;
 220         int r = 0;
 221
 222         if (of_have_populated_dt()) {
 223                 np = omap_get_timer_dt(omap_timer_match, NULL);
 224                 if (!np)
 225                         return -ENODEV;
 226
 227                 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 228                 if (!oh_name)
 229                         return -ENODEV;
 230
 231                 timer->irq = irq_of_parse_and_map(np, 0);
 232                 if (!timer->irq)
 233                         return -ENXIO;
 234
 235                 timer->io_base = of_iomap(np, 0);
 236
 237                 of_node_put(np);
 238         } else {
 239                 if (omap_dm_timer_reserve_systimer(gptimer_id))
 240                         return -ENODEV;
 241
 242                 sprintf(name, "timer%d", gptimer_id);
 243                 oh_name = name;
 244         }
 245
 246         oh = omap_hwmod_lookup(oh_name);
 247         if (!oh)
 248                 return -ENODEV;
 249
 250         *timer_name = oh->name;
 251
 252         if (!of_have_populated_dt()) {
 253                 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
 254                                                    &irq);
 255                 if (r)
 256                         return -ENXIO;
 257                 timer->irq = irq.start;
 258
 259                 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
 260                                                    &mem);
 261                 if (r)
 262                         return -ENXIO;
 263
 264                 /* Static mapping, never released */
 265                 timer->io_base = ioremap(mem.start, mem.end - mem.start);
 266         }
 267
 268         if (!timer->io_base)
 269                 return -ENXIO;
 270
 271         /* After the dmtimer is using hwmod these clocks won't be needed */
 272         timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
 273         if (IS_ERR(timer->fclk))
 274                 return PTR_ERR(timer->fclk);
 275
 276         src = clk_get(NULL, fck_source);
 277         if (IS_ERR(src))
 278                 return PTR_ERR(src);
 279
 280         if (clk_get_parent(timer->fclk) != src) {
 281                 r = clk_set_parent(timer->fclk, src);
 282                 if (r < 0) {
 283                         pr_warn("%s: %s cannot set source\n", __func__,
 284                                 oh->name);
 285                         clk_put(src);
 286                         return r;
 287                 }
 288         }
 289
 290         clk_put(src);
 291
 292         omap_hwmod_setup_one(oh_name);
 293         omap_hwmod_enable(oh);
 294         __omap_dm_timer_init_regs(timer);
 295
 296         if (posted)
 297                 __omap_dm_timer_enable_posted(timer);
 298
 299         /* Check that the intended posted configuration matches the actual */
 300         if (posted != timer->posted)
 301                 return -EINVAL;
 302
 303         timer->rate = clk_get_rate(timer->fclk);
 304         timer->reserved = 1;
 305
 306         return r;
 307 }
 308
 309 static void __init omap2_gp_clockevent_init(int gptimer_id,
 310                                                 const char *fck_source,
 311                                                 const char *property)
 312 {
 313         int res;
 314
 315         clkev.errata = omap_dm_timer_get_errata();
 316
 317         /*
 318          * For clock-event timers we never read the timer counter and
 319          * so we are not impacted by errata i103 and i767. Therefore,
 320          * we can safely ignore this errata for clock-event timers.
 321          */
 322         __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
 323
 324         res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property,
 325                                      &clockevent_gpt.name, OMAP_TIMER_POSTED);
 326         BUG_ON(res);
 327
 328         omap2_gp_timer_irq.dev_id = &clkev;
 329         setup_irq(clkev.irq, &omap2_gp_timer_irq);
 330
 331         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
 332
 333         clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
 334                                      clockevent_gpt.shift);
 335         clockevent_gpt.max_delta_ns =
 336                 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
 337         clockevent_gpt.min_delta_ns =
 338                 clockevent_delta2ns(3, &clockevent_gpt);
 339                 /* Timer internal resynch latency. */
 340
 341         clockevent_gpt.cpumask = cpu_possible_mask;
 342         clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
 343         clockevents_register_device(&clockevent_gpt);
 344
 345         pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
 346                 clkev.rate);
 347 }
 348
 349 /* Clocksource code */
 350 static struct omap_dm_timer clksrc;
 351 static bool use_gptimer_clksrc;
 352
 353 /*
 354  * clocksource
 355  */
 356 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 357 {
 358         return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
 359                                                      OMAP_TIMER_NONPOSTED);
 360 }
 361
 362 static struct clocksource clocksource_gpt = {
 363         .rating         = 300,
 364         .read           = clocksource_read_cycles,
 365         .mask           = CLOCKSOURCE_MASK(32),
 366         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 367 };
 368
 369 static u32 notrace dmtimer_read_sched_clock(void)
 370 {
 371         if (clksrc.reserved)
 372                 return __omap_dm_timer_read_counter(&clksrc,
 373                                                     OMAP_TIMER_NONPOSTED);
 374
 375         return 0;
 376 }
 377
 378 static struct of_device_id omap_counter_match[] __initdata = {
 379         { .compatible = "ti,omap-counter32k", },
 380         { }
 381 };
 382
 383 /* Setup free-running counter for clocksource */
 384 static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
 385 {
 386         int ret;
 387         struct device_node *np = NULL;
 388         struct omap_hwmod *oh;
 389         void __iomem *vbase;
 390         const char *oh_name = "counter_32k";
 391
 392         /*
 393          * If device-tree is present, then search the DT blob
 394          * to see if the 32kHz counter is supported.
 395          */
 396         if (of_have_populated_dt()) {
 397                 np = omap_get_timer_dt(omap_counter_match, NULL);
 398                 if (!np)
 399                         return -ENODEV;
 400
 401                 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 402                 if (!oh_name)
 403                         return -ENODEV;
 404         }
 405
 406         /*
 407          * First check hwmod data is available for sync32k counter
 408          */
 409         oh = omap_hwmod_lookup(oh_name);
 410         if (!oh || oh->slaves_cnt == 0)
 411                 return -ENODEV;
 412
 413         omap_hwmod_setup_one(oh_name);
 414
 415         if (np) {
 416                 vbase = of_iomap(np, 0);
 417                 of_node_put(np);
 418         } else {
 419                 vbase = omap_hwmod_get_mpu_rt_va(oh);
 420         }
 421
 422         if (!vbase) {
 423                 pr_warn("%s: failed to get counter_32k resource\n", __func__);
 424                 return -ENXIO;
 425         }
 426
 427         ret = omap_hwmod_enable(oh);
 428         if (ret) {
 429                 pr_warn("%s: failed to enable counter_32k module (%d)\n",
 430                                                         __func__, ret);
 431                 return ret;
 432         }
 433
 434         ret = omap_init_clocksource_32k(vbase);
 435         if (ret) {
 436                 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
 437                                                         __func__, ret);
 438                 omap_hwmod_idle(oh);
 439         }
 440
 441         return ret;
 442 }
 443
 444 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
 445                                                 const char *fck_source)
 446 {
 447         int res;
 448
 449         clksrc.errata = omap_dm_timer_get_errata();
 450
 451         res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL,
 452                                      &clocksource_gpt.name,
 453                                      OMAP_TIMER_NONPOSTED);
 454         BUG_ON(res);
 455
 456         __omap_dm_timer_load_start(&clksrc,
 457                                    OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
 458                                    OMAP_TIMER_NONPOSTED);
 459         setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
 460
 461         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
 462                 pr_err("Could not register clocksource %s\n",
 463                         clocksource_gpt.name);
 464         else
 465                 pr_info("OMAP clocksource: %s at %lu Hz\n",
 466                         clocksource_gpt.name, clksrc.rate);
 467 }
 468
 469 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
 470 /*
 471  * The realtime counter also called master counter, is a free-running
 472  * counter, which is related to real time. It produces the count used
 473  * by the CPU local timer peripherals in the MPU cluster. The timer counts
 474  * at a rate of 6.144 MHz. Because the device operates on different clocks
 475  * in different power modes, the master counter shifts operation between
 476  * clocks, adjusting the increment per clock in hardware accordingly to
 477  * maintain a constant count rate.
 478  */
 479 static void __init realtime_counter_init(void)
 480 {
 481         void __iomem *base;
 482         static struct clk *sys_clk;
 483         unsigned long rate;
 484         unsigned int reg, num, den;
 485
 486         base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
 487         if (!base) {
 488                 pr_err("%s: ioremap failed\n", __func__);
 489                 return;
 490         }
 491         sys_clk = clk_get(NULL, "sys_clkin_ck");
 492         if (IS_ERR(sys_clk)) {
 493                 pr_err("%s: failed to get system clock handle\n", __func__);
 494                 iounmap(base);
 495                 return;
 496         }
 497
 498         rate = clk_get_rate(sys_clk);
 499         /* Numerator/denumerator values refer TRM Realtime Counter section */
 500         switch (rate) {
 501         case 1200000:
 502                 num = 64;
 503                 den = 125;
 504                 break;
 505         case 1300000:
 506                 num = 768;
 507                 den = 1625;
 508                 break;
 509         case 19200000:
 510                 num = 8;
 511                 den = 25;
 512                 break;
 513         case 2600000:
 514                 num = 384;
 515                 den = 1625;
 516                 break;
 517         case 2700000:
 518                 num = 256;
 519                 den = 1125;
 520                 break;
 521         case 38400000:
 522         default:
 523                 /* Program it for 38.4 MHz */
 524                 num = 4;
 525                 den = 25;
 526                 break;
 527         }
 528
 529         /* Program numerator and denumerator registers */
 530         reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
 531                         NUMERATOR_DENUMERATOR_MASK;
 532         reg |= num;
 533         __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
 534
 535         reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
 536                         NUMERATOR_DENUMERATOR_MASK;
 537         reg |= den;
 538         __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
 539
 540         iounmap(base);
 541 }
 542 #else
 543 static inline void __init realtime_counter_init(void)
 544 {}
 545 #endif
 546
 547 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,   \
 548                                clksrc_nr, clksrc_src)                   \
 549 void __init omap##name##_gptimer_timer_init(void)                       \
 550 {                                                                       \
 551         omap_dmtimer_init();                                            \
 552         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
 553         omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);        \
 554 }
 555
 556 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,  \
 557                                 clksrc_nr, clksrc_src)                  \
 558 void __init omap##name##_sync32k_timer_init(void)               \
 559 {                                                                       \
 560         omap_dmtimer_init();                                            \
 561         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
 562         /* Enable the use of clocksource="gp_timer" kernel parameter */ \
 563         if (use_gptimer_clksrc)                                         \
 564                 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);\
 565         else                                                            \
 566                 omap2_sync32k_clocksource_init();                       \
 567 }
 568
 569 #ifdef CONFIG_ARCH_OMAP2
 570 OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon",
 571                         2, "timer_sys_ck");
 572 #endif /* CONFIG_ARCH_OMAP2 */
 573
 574 #ifdef CONFIG_ARCH_OMAP3
 575 OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon",
 576                         2, "timer_sys_ck");
 577 OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure",
 578                         2, "timer_sys_ck");
 579 OMAP_SYS_GP_TIMER_INIT(3_gp, 1, "timer_sys_ck", "ti,timer-alwon",
 580                        2, "timer_sys_ck");
 581 #endif /* CONFIG_ARCH_OMAP3 */
 582
 583 #ifdef CONFIG_SOC_AM33XX
 584 OMAP_SYS_GP_TIMER_INIT(3_am33xx, 1, "timer_sys_ck", "ti,timer-alwon",
 585                        2, "timer_sys_ck");
 586 #endif /* CONFIG_SOC_AM33XX */
 587
 588 #ifdef CONFIG_ARCH_OMAP4
 589 OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
 590                         2, "sys_clkin_ck");
 591 #ifdef CONFIG_LOCAL_TIMERS
 592 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
 593 void __init omap4_local_timer_init(void)
 594 {
 595         omap4_sync32k_timer_init();
 596         /* Local timers are not supprted on OMAP4430 ES1.0 */
 597         if (omap_rev() != OMAP4430_REV_ES1_0) {
 598                 int err;
 599
 600                 if (of_have_populated_dt()) {
 601                         twd_local_timer_of_register();
 602                         return;
 603                 }
 604
 605                 err = twd_local_timer_register(&twd_local_timer);
 606                 if (err)
 607                         pr_err("twd_local_timer_register failed %d\n", err);
 608         }
 609 }
 610 #else /* CONFIG_LOCAL_TIMERS */
 611 void __init omap4_local_timer_init(void)
 612 {
 613         omap4_sync32k_timer_init();
 614 }
 615 #endif /* CONFIG_LOCAL_TIMERS */
 616 #endif /* CONFIG_ARCH_OMAP4 */
 617
 618 #ifdef CONFIG_SOC_OMAP5
 619 OMAP_SYS_32K_TIMER_INIT(5, 1, "timer_32k_ck", "ti,timer-alwon",
 620                         2, "sys_clkin_ck");
 621 void __init omap5_realtime_timer_init(void)
 622 {
 623         int err;
 624
 625         omap5_sync32k_timer_init();
 626         realtime_counter_init();
 627
 628         err = arch_timer_of_register();
 629         if (err)
 630                 pr_err("%s: arch_timer_register failed %d\n", __func__, err);
 631 }
 632 #endif /* CONFIG_SOC_OMAP5 */
 633
 634 /**
 635  * omap_timer_init - build and register timer device with an
 636  * associated timer hwmod
 637  * @oh: timer hwmod pointer to be used to build timer device
 638  * @user:       parameter that can be passed from calling hwmod API
 639  *
 640  * Called by omap_hwmod_for_each_by_class to register each of the timer
 641  * devices present in the system. The number of timer devices is known
 642  * by parsing through the hwmod database for a given class name. At the
 643  * end of function call memory is allocated for timer device and it is
 644  * registered to the framework ready to be proved by the driver.
 645  */
 646 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
 647 {
 648         int id;
 649         int ret = 0;
 650         char *name = "omap_timer";
 651         struct dmtimer_platform_data *pdata;
 652         struct platform_device *pdev;
 653         struct omap_timer_capability_dev_attr *timer_dev_attr;
 654
 655         pr_debug("%s: %s\n", __func__, oh->name);
 656
 657         /* on secure device, do not register secure timer */
 658         timer_dev_attr = oh->dev_attr;
 659         if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
 660                 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
 661                         return ret;
 662
 663         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 664         if (!pdata) {
 665                 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
 666                 return -ENOMEM;
 667         }
 668
 669         /*
 670          * Extract the IDs from name field in hwmod database
 671          * and use the same for constructing ids' for the
 672          * timer devices. In a way, we are avoiding usage of
 673          * static variable witin the function to do the same.
 674          * CAUTION: We have to be careful and make sure the
 675          * name in hwmod database does not change in which case
 676          * we might either make corresponding change here or
 677          * switch back static variable mechanism.
 678          */
 679         sscanf(oh->name, "timer%2d", &id);
 680
 681         if (timer_dev_attr)
 682                 pdata->timer_capability = timer_dev_attr->timer_capability;
 683
 684         pdata->timer_errata = omap_dm_timer_get_errata();
 685         pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
 686
 687         pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
 688                                  NULL, 0, 0);
 689
 690         if (IS_ERR(pdev)) {
 691                 pr_err("%s: Can't build omap_device for %s: %s.\n",
 692                         __func__, name, oh->name);
 693                 ret = -EINVAL;
 694         }
 695
 696         kfree(pdata);
 697
 698         return ret;
 699 }
 700
 701 /**
 702  * omap2_dm_timer_init - top level regular device initialization
 703  *
 704  * Uses dedicated hwmod api to parse through hwmod database for
 705  * given class name and then build and register the timer device.
 706  */
 707 static int __init omap2_dm_timer_init(void)
 708 {
 709         int ret;
 710
 711         /* If dtb is there, the devices will be created dynamically */
 712         if (of_have_populated_dt())
 713                 return -ENODEV;
 714
 715         ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
 716         if (unlikely(ret)) {
 717                 pr_err("%s: device registration failed.\n", __func__);
 718                 return -EINVAL;
 719         }
 720
 721         return 0;
 722 }
 723 arch_initcall(omap2_dm_timer_init);
 724
 725 /**
 726  * omap2_override_clocksource - clocksource override with user configuration
 727  *
 728  * Allows user to override default clocksource, using kernel parameter
 729  *   clocksource="gp_timer"     (For all OMAP2PLUS architectures)
 730  *
 731  * Note that, here we are using same standard kernel parameter "clocksource=",
 732  * and not introducing any OMAP specific interface.
 733  */
 734 static int __init omap2_override_clocksource(char *str)
 735 {
 736         if (!str)
 737                 return 0;
 738         /*
 739          * For OMAP architecture, we only have two options
 740          *    - sync_32k (default)
 741          *    - gp_timer (sys_clk based)
 742          */
 743         if (!strcmp(str, "gp_timer"))
 744                 use_gptimer_clksrc = true;
 745
 746         return 0;
 747 }
 748 early_param("clocksource", omap2_override_clocksource);