arch/arm/mach-omap2/timer.c

   1 /*
   2  * linux/arch/arm/mach-omap2/timer.c
   3  *
   4  * OMAP2 GP timer support.
   5  *
   6  * Copyright (C) 2009 Nokia Corporation
   7  *
   8  * Update to use new clocksource/clockevent layers
   9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  10  * Copyright (C) 2007 MontaVista Software, Inc.
  11  *
  12  * Original driver:
  13  * Copyright (C) 2005 Nokia Corporation
  14  * Author: Paul Mundt <paul.mundt@nokia.com>
  15  *         Juha Yrjölä <juha.yrjola@nokia.com>
  16  * OMAP Dual-mode timer framework support by Timo Teras
  17  *
  18  * Some parts based off of TI's 24xx code:
  19  *
  20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
  21  *
  22  * Roughly modelled after the OMAP1 MPU timer code.
  23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  24  *
  25  * This file is subject to the terms and conditions of the GNU General Public
  26  * License. See the file "COPYING" in the main directory of this archive
  27  * for more details.
  28  */
  29 #include <linux/init.h>
  30 #include <linux/time.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <linux/irq.h>
  36 #include <linux/clocksource.h>
  37 #include <linux/clockchips.h>
  38 #include <linux/slab.h>
  39
  40 #include <asm/mach/time.h>
  41 #include <plat/dmtimer.h>
  42 #include <asm/smp_twd.h>
  43 #include <asm/sched_clock.h>
  44 #include "common.h"
  45 #include <plat/omap_hwmod.h>
  46 #include <plat/omap_device.h>
  47 #include <plat/omap-pm.h>
  48
  49 #include "powerdomain.h"
  50
  51 /* Parent clocks, eventually these will come from the clock framework */
  52
  53 #define OMAP2_MPU_SOURCE        "sys_ck"
  54 #define OMAP3_MPU_SOURCE        OMAP2_MPU_SOURCE
  55 #define OMAP4_MPU_SOURCE        "sys_clkin_ck"
  56 #define OMAP2_32K_SOURCE        "func_32k_ck"
  57 #define OMAP3_32K_SOURCE        "omap_32k_fck"
  58 #define OMAP4_32K_SOURCE        "sys_32k_ck"
  59
  60 #ifdef CONFIG_OMAP_32K_TIMER
  61 #define OMAP2_CLKEV_SOURCE      OMAP2_32K_SOURCE
  62 #define OMAP3_CLKEV_SOURCE      OMAP3_32K_SOURCE
  63 #define OMAP4_CLKEV_SOURCE      OMAP4_32K_SOURCE
  64 #define OMAP3_SECURE_TIMER      12
  65 #else
  66 #define OMAP2_CLKEV_SOURCE      OMAP2_MPU_SOURCE
  67 #define OMAP3_CLKEV_SOURCE      OMAP3_MPU_SOURCE
  68 #define OMAP4_CLKEV_SOURCE      OMAP4_MPU_SOURCE
  69 #define OMAP3_SECURE_TIMER      1
  70 #endif
  71
  72 /* Clockevent code */
  73
  74 static struct omap_dm_timer clkev;
  75 static struct clock_event_device clockevent_gpt;
  76
  77 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  78 {
  79         struct clock_event_device *evt = &clockevent_gpt;
  80
  81         __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
  82
  83         evt->event_handler(evt);
  84         return IRQ_HANDLED;
  85 }
  86
  87 static struct irqaction omap2_gp_timer_irq = {
  88         .name           = "gp_timer",
  89         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  90         .handler        = omap2_gp_timer_interrupt,
  91 };
  92
  93 static int omap2_gp_timer_set_next_event(unsigned long cycles,
  94                                          struct clock_event_device *evt)
  95 {
  96         __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
  97                                                 0xffffffff - cycles, 1);
  98
  99         return 0;
 100 }
 101
 102 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 103                                     struct clock_event_device *evt)
 104 {
 105         u32 period;
 106
 107         __omap_dm_timer_stop(&clkev, 1, clkev.rate);
 108
 109         switch (mode) {
 110         case CLOCK_EVT_MODE_PERIODIC:
 111                 period = clkev.rate / HZ;
 112                 period -= 1;
 113                 /* Looks like we need to first set the load value separately */
 114                 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
 115                                         0xffffffff - period, 1);
 116                 __omap_dm_timer_load_start(&clkev,
 117                                         OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
 118                                                 0xffffffff - period, 1);
 119                 break;
 120         case CLOCK_EVT_MODE_ONESHOT:
 121                 break;
 122         case CLOCK_EVT_MODE_UNUSED:
 123         case CLOCK_EVT_MODE_SHUTDOWN:
 124         case CLOCK_EVT_MODE_RESUME:
 125                 break;
 126         }
 127 }
 128
 129 static struct clock_event_device clockevent_gpt = {
 130         .name           = "gp_timer",
 131         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 132         .shift          = 32,
 133         .set_next_event = omap2_gp_timer_set_next_event,
 134         .set_mode       = omap2_gp_timer_set_mode,
 135 };
 136
 137 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 138                                                 int gptimer_id,
 139                                                 const char *fck_source)
 140 {
 141         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
 142         struct omap_hwmod *oh;
 143         struct resource irq_rsrc, mem_rsrc;
 144         size_t size;
 145         int res = 0;
 146         int r;
 147
 148         sprintf(name, "timer%d", gptimer_id);
 149         omap_hwmod_setup_one(name);
 150         oh = omap_hwmod_lookup(name);
 151         if (!oh)
 152                 return -ENODEV;
 153
 154         r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
 155         if (r)
 156                 return -ENXIO;
 157         timer->irq = irq_rsrc.start;
 158
 159         r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
 160         if (r)
 161                 return -ENXIO;
 162         timer->phys_base = mem_rsrc.start;
 163         size = mem_rsrc.end - mem_rsrc.start;
 164
 165         /* Static mapping, never released */
 166         timer->io_base = ioremap(timer->phys_base, size);
 167         if (!timer->io_base)
 168                 return -ENXIO;
 169
 170         /* After the dmtimer is using hwmod these clocks won't be needed */
 171         sprintf(name, "gpt%d_fck", gptimer_id);
 172         timer->fclk = clk_get(NULL, name);
 173         if (IS_ERR(timer->fclk))
 174                 return -ENODEV;
 175
 176         omap_hwmod_enable(oh);
 177
 178         if (omap_dm_timer_reserve_systimer(gptimer_id))
 179                 return -ENODEV;
 180
 181         if (gptimer_id != 12) {
 182                 struct clk *src;
 183
 184                 src = clk_get(NULL, fck_source);
 185                 if (IS_ERR(src)) {
 186                         res = -EINVAL;
 187                 } else {
 188                         res = __omap_dm_timer_set_source(timer->fclk, src);
 189                         if (IS_ERR_VALUE(res))
 190                                 pr_warning("%s: timer%i cannot set source\n",
 191                                                 __func__, gptimer_id);
 192                         clk_put(src);
 193                 }
 194         }
 195         __omap_dm_timer_init_regs(timer);
 196         __omap_dm_timer_reset(timer, 1, 1);
 197         timer->posted = 1;
 198
 199         timer->rate = clk_get_rate(timer->fclk);
 200
 201         timer->reserved = 1;
 202
 203         return res;
 204 }
 205
 206 static void __init omap2_gp_clockevent_init(int gptimer_id,
 207                                                 const char *fck_source)
 208 {
 209         int res;
 210
 211         res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
 212         BUG_ON(res);
 213
 214         omap2_gp_timer_irq.dev_id = (void *)&clkev;
 215         setup_irq(clkev.irq, &omap2_gp_timer_irq);
 216
 217         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
 218
 219         clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
 220                                      clockevent_gpt.shift);
 221         clockevent_gpt.max_delta_ns =
 222                 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
 223         clockevent_gpt.min_delta_ns =
 224                 clockevent_delta2ns(3, &clockevent_gpt);
 225                 /* Timer internal resynch latency. */
 226
 227         clockevent_gpt.cpumask = cpumask_of(0);
 228         clockevents_register_device(&clockevent_gpt);
 229
 230         pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
 231                 gptimer_id, clkev.rate);
 232 }
 233
 234 /* Clocksource code */
 235 static struct omap_dm_timer clksrc;
 236 static bool use_gptimer_clksrc;
 237
 238 /*
 239  * clocksource
 240  */
 241 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 242 {
 243         return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
 244 }
 245
 246 static struct clocksource clocksource_gpt = {
 247         .name           = "gp_timer",
 248         .rating         = 300,
 249         .read           = clocksource_read_cycles,
 250         .mask           = CLOCKSOURCE_MASK(32),
 251         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 252 };
 253
 254 static u32 notrace dmtimer_read_sched_clock(void)
 255 {
 256         if (clksrc.reserved)
 257                 return __omap_dm_timer_read_counter(&clksrc, 1);
 258
 259         return 0;
 260 }
 261
 262 /* Setup free-running counter for clocksource */
 263 static int __init omap2_sync32k_clocksource_init(void)
 264 {
 265         int ret;
 266         struct omap_hwmod *oh;
 267         void __iomem *vbase;
 268         const char *oh_name = "counter_32k";
 269
 270         /*
 271          * First check hwmod data is available for sync32k counter
 272          */
 273         oh = omap_hwmod_lookup(oh_name);
 274         if (!oh || oh->slaves_cnt == 0)
 275                 return -ENODEV;
 276
 277         omap_hwmod_setup_one(oh_name);
 278
 279         vbase = omap_hwmod_get_mpu_rt_va(oh);
 280         if (!vbase) {
 281                 pr_warn("%s: failed to get counter_32k resource\n", __func__);
 282                 return -ENXIO;
 283         }
 284
 285         ret = omap_hwmod_enable(oh);
 286         if (ret) {
 287                 pr_warn("%s: failed to enable counter_32k module (%d)\n",
 288                                                         __func__, ret);
 289                 return ret;
 290         }
 291
 292         ret = omap_init_clocksource_32k(vbase);
 293         if (ret) {
 294                 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
 295                                                         __func__, ret);
 296                 omap_hwmod_idle(oh);
 297         }
 298
 299         return ret;
 300 }
 301
 302 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
 303                                                 const char *fck_source)
 304 {
 305         int res;
 306
 307         res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
 308         BUG_ON(res);
 309
 310         __omap_dm_timer_load_start(&clksrc,
 311                         OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
 312         setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
 313
 314         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
 315                 pr_err("Could not register clocksource %s\n",
 316                         clocksource_gpt.name);
 317         else
 318                 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
 319                         gptimer_id, clksrc.rate);
 320 }
 321
 322 static void __init omap2_clocksource_init(int gptimer_id,
 323                                                 const char *fck_source)
 324 {
 325         /*
 326          * First give preference to kernel parameter configuration
 327          * by user (clocksource="gp_timer").
 328          *
 329          * In case of missing kernel parameter for clocksource,
 330          * first check for availability for 32k-sync timer, in case
 331          * of failure in finding 32k_counter module or registering
 332          * it as clocksource, execution will fallback to gp-timer.
 333          */
 334         if (use_gptimer_clksrc == true)
 335                 omap2_gptimer_clocksource_init(gptimer_id, fck_source);
 336         else if (omap2_sync32k_clocksource_init())
 337                 /* Fall back to gp-timer code */
 338                 omap2_gptimer_clocksource_init(gptimer_id, fck_source);
 339 }
 340
 341 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,                  \
 342                                 clksrc_nr, clksrc_src)                  \
 343 static void __init omap##name##_timer_init(void)                        \
 344 {                                                                       \
 345         omap2_gp_clockevent_init((clkev_nr), clkev_src);                \
 346         omap2_clocksource_init((clksrc_nr), clksrc_src);                \
 347 }
 348
 349 #define OMAP_SYS_TIMER(name)                                            \
 350 struct sys_timer omap##name##_timer = {                                 \
 351         .init   = omap##name##_timer_init,                              \
 352 };
 353
 354 #ifdef CONFIG_ARCH_OMAP2
 355 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
 356 OMAP_SYS_TIMER(2)
 357 #endif
 358
 359 #ifdef CONFIG_ARCH_OMAP3
 360 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
 361 OMAP_SYS_TIMER(3)
 362 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
 363                         2, OMAP3_MPU_SOURCE)
 364 OMAP_SYS_TIMER(3_secure)
 365 #endif
 366
 367 #ifdef CONFIG_ARCH_OMAP4
 368 #ifdef CONFIG_LOCAL_TIMERS
 369 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
 370                               OMAP44XX_LOCAL_TWD_BASE,
 371                               OMAP44XX_IRQ_LOCALTIMER);
 372 #endif
 373
 374 static void __init omap4_timer_init(void)
 375 {
 376         omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
 377         omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
 378 #ifdef CONFIG_LOCAL_TIMERS
 379         /* Local timers are not supprted on OMAP4430 ES1.0 */
 380         if (omap_rev() != OMAP4430_REV_ES1_0) {
 381                 int err;
 382
 383                 err = twd_local_timer_register(&twd_local_timer);
 384                 if (err)
 385                         pr_err("twd_local_timer_register failed %d\n", err);
 386         }
 387 #endif
 388 }
 389 OMAP_SYS_TIMER(4)
 390 #endif
 391
 392 /**
 393  * omap2_dm_timer_set_src - change the timer input clock source
 394  * @pdev:       timer platform device pointer
 395  * @source:     array index of parent clock source
 396  */
 397 static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
 398 {
 399         int ret;
 400         struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
 401         struct clk *fclk, *parent;
 402         char *parent_name = NULL;
 403
 404         fclk = clk_get(&pdev->dev, "fck");
 405         if (IS_ERR_OR_NULL(fclk)) {
 406                 dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
 407                                 __func__, __LINE__);
 408                 return -EINVAL;
 409         }
 410
 411         switch (source) {
 412         case OMAP_TIMER_SRC_SYS_CLK:
 413                 parent_name = "sys_ck";
 414                 break;
 415
 416         case OMAP_TIMER_SRC_32_KHZ:
 417                 parent_name = "32k_ck";
 418                 break;
 419
 420         case OMAP_TIMER_SRC_EXT_CLK:
 421                 if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
 422                         parent_name = "alt_ck";
 423                         break;
 424                 }
 425                 dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
 426                         __func__, __LINE__);
 427                 clk_put(fclk);
 428                 return -EINVAL;
 429         }
 430
 431         parent = clk_get(&pdev->dev, parent_name);
 432         if (IS_ERR_OR_NULL(parent)) {
 433                 dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
 434                         __func__, __LINE__, parent_name);
 435                 clk_put(fclk);
 436                 return -EINVAL;
 437         }
 438
 439         ret = clk_set_parent(fclk, parent);
 440         if (IS_ERR_VALUE(ret)) {
 441                 dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
 442                         __func__, parent_name);
 443                 ret = -EINVAL;
 444         }
 445
 446         clk_put(parent);
 447         clk_put(fclk);
 448
 449         return ret;
 450 }
 451
 452 /**
 453  * omap_timer_init - build and register timer device with an
 454  * associated timer hwmod
 455  * @oh: timer hwmod pointer to be used to build timer device
 456  * @user:       parameter that can be passed from calling hwmod API
 457  *
 458  * Called by omap_hwmod_for_each_by_class to register each of the timer
 459  * devices present in the system. The number of timer devices is known
 460  * by parsing through the hwmod database for a given class name. At the
 461  * end of function call memory is allocated for timer device and it is
 462  * registered to the framework ready to be proved by the driver.
 463  */
 464 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
 465 {
 466         int id;
 467         int ret = 0;
 468         char *name = "omap_timer";
 469         struct dmtimer_platform_data *pdata;
 470         struct platform_device *pdev;
 471         struct omap_timer_capability_dev_attr *timer_dev_attr;
 472         struct powerdomain *pwrdm;
 473
 474         pr_debug("%s: %s\n", __func__, oh->name);
 475
 476         /* on secure device, do not register secure timer */
 477         timer_dev_attr = oh->dev_attr;
 478         if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
 479                 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
 480                         return ret;
 481
 482         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 483         if (!pdata) {
 484                 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
 485                 return -ENOMEM;
 486         }
 487
 488         /*
 489          * Extract the IDs from name field in hwmod database
 490          * and use the same for constructing ids' for the
 491          * timer devices. In a way, we are avoiding usage of
 492          * static variable witin the function to do the same.
 493          * CAUTION: We have to be careful and make sure the
 494          * name in hwmod database does not change in which case
 495          * we might either make corresponding change here or
 496          * switch back static variable mechanism.
 497          */
 498         sscanf(oh->name, "timer%2d", &id);
 499
 500         pdata->set_timer_src = omap2_dm_timer_set_src;
 501         pdata->timer_ip_version = oh->class->rev;
 502
 503         if (timer_dev_attr)
 504                 pdata->timer_capability = timer_dev_attr->timer_capability;
 505
 506         pwrdm = omap_hwmod_get_pwrdm(oh);
 507         pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
 508 #ifdef CONFIG_PM
 509         pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
 510 #endif
 511         pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
 512                                  NULL, 0, 0);
 513
 514         if (IS_ERR(pdev)) {
 515                 pr_err("%s: Can't build omap_device for %s: %s.\n",
 516                         __func__, name, oh->name);
 517                 ret = -EINVAL;
 518         }
 519
 520         kfree(pdata);
 521
 522         return ret;
 523 }
 524
 525 /**
 526  * omap2_dm_timer_init - top level regular device initialization
 527  *
 528  * Uses dedicated hwmod api to parse through hwmod database for
 529  * given class name and then build and register the timer device.
 530  */
 531 static int __init omap2_dm_timer_init(void)
 532 {
 533         int ret;
 534
 535         ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
 536         if (unlikely(ret)) {
 537                 pr_err("%s: device registration failed.\n", __func__);
 538                 return -EINVAL;
 539         }
 540
 541         return 0;
 542 }
 543 arch_initcall(omap2_dm_timer_init);
 544
 545 /**
 546  * omap2_override_clocksource - clocksource override with user configuration
 547  *
 548  * Allows user to override default clocksource, using kernel parameter
 549  *   clocksource="gp_timer"     (For all OMAP2PLUS architectures)
 550  *
 551  * Note that, here we are using same standard kernel parameter "clocksource=",
 552  * and not introducing any OMAP specific interface.
 553  */
 554 static int __init omap2_override_clocksource(char *str)
 555 {
 556         if (!str)
 557                 return 0;
 558         /*
 559          * For OMAP architecture, we only have two options
 560          *    - sync_32k (default)
 561          *    - gp_timer (sys_clk based)
 562          */
 563         if (!strcmp(str, "gp_timer"))
 564                 use_gptimer_clksrc = true;
 565
 566         return 0;
 567 }
 568 early_param("clocksource", omap2_override_clocksource);