arch/arm/mach-orion5x/common.c

   1 /*
   2  * arch/arm/mach-orion5x/common.c
   3  *
   4  * Core functions for Marvell Orion 5x SoCs
   5  *
   6  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/serial_8250.h>
  18 #include <linux/mbus.h>
  19 #include <linux/mv643xx_i2c.h>
  20 #include <linux/ata_platform.h>
  21 #include <linux/delay.h>
  22 #include <net/dsa.h>
  23 #include <asm/page.h>
  24 #include <asm/setup.h>
  25 #include <asm/timex.h>
  26 #include <asm/mach/arch.h>
  27 #include <asm/mach/map.h>
  28 #include <asm/mach/time.h>
  29 #include <mach/bridge-regs.h>
  30 #include <mach/hardware.h>
  31 #include <mach/orion5x.h>
  32 #include <plat/orion_nand.h>
  33 #include <plat/time.h>
  34 #include <plat/common.h>
  35 #include "common.h"
  36
  37 /*****************************************************************************
  38  * I/O Address Mapping
  39  ****************************************************************************/
  40 static struct map_desc orion5x_io_desc[] __initdata = {
  41         {
  42                 .virtual        = ORION5X_REGS_VIRT_BASE,
  43                 .pfn            = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
  44                 .length         = ORION5X_REGS_SIZE,
  45                 .type           = MT_DEVICE,
  46         }, {
  47                 .virtual        = ORION5X_PCIE_IO_VIRT_BASE,
  48                 .pfn            = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
  49                 .length         = ORION5X_PCIE_IO_SIZE,
  50                 .type           = MT_DEVICE,
  51         }, {
  52                 .virtual        = ORION5X_PCI_IO_VIRT_BASE,
  53                 .pfn            = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
  54                 .length         = ORION5X_PCI_IO_SIZE,
  55                 .type           = MT_DEVICE,
  56         }, {
  57                 .virtual        = ORION5X_PCIE_WA_VIRT_BASE,
  58                 .pfn            = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
  59                 .length         = ORION5X_PCIE_WA_SIZE,
  60                 .type           = MT_DEVICE,
  61         },
  62 };
  63
  64 void __init orion5x_map_io(void)
  65 {
  66         iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
  67 }
  68
  69
  70 /*****************************************************************************
  71  * EHCI0
  72  ****************************************************************************/
  73 void __init orion5x_ehci0_init(void)
  74 {
  75         orion_ehci_init(&orion5x_mbus_dram_info,
  76                         ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
  77 }
  78
  79
  80 /*****************************************************************************
  81  * EHCI1
  82  ****************************************************************************/
  83 void __init orion5x_ehci1_init(void)
  84 {
  85         orion_ehci_1_init(&orion5x_mbus_dram_info,
  86                           ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
  87 }
  88
  89
  90 /*****************************************************************************
  91  * GE00
  92  ****************************************************************************/
  93 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
  94 {
  95         orion_ge00_init(eth_data, &orion5x_mbus_dram_info,
  96                         ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
  97                         IRQ_ORION5X_ETH_ERR, orion5x_tclk);
  98 }
  99
 100
 101 /*****************************************************************************
 102  * Ethernet switch
 103  ****************************************************************************/
 104 void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
 105 {
 106         orion_ge00_switch_init(d, irq);
 107 }
 108
 109
 110 /*****************************************************************************
 111  * I2C
 112  ****************************************************************************/
 113 void __init orion5x_i2c_init(void)
 114 {
 115         orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
 116
 117 }
 118
 119
 120 /*****************************************************************************
 121  * SATA
 122  ****************************************************************************/
 123 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
 124 {
 125         orion_sata_init(sata_data, &orion5x_mbus_dram_info,
 126                         ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
 127 }
 128
 129
 130 /*****************************************************************************
 131  * SPI
 132  ****************************************************************************/
 133 void __init orion5x_spi_init()
 134 {
 135         orion_spi_init(SPI_PHYS_BASE, orion5x_tclk);
 136 }
 137
 138
 139 /*****************************************************************************
 140  * UART0
 141  ****************************************************************************/
 142 void __init orion5x_uart0_init(void)
 143 {
 144         orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
 145                          IRQ_ORION5X_UART0, orion5x_tclk);
 146 }
 147
 148 /*****************************************************************************
 149  * UART1
 150  ****************************************************************************/
 151 void __init orion5x_uart1_init(void)
 152 {
 153         orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
 154                          IRQ_ORION5X_UART1, orion5x_tclk);
 155 }
 156
 157 /*****************************************************************************
 158  * XOR engine
 159  ****************************************************************************/
 160 void __init orion5x_xor_init(void)
 161 {
 162         orion_xor0_init(&orion5x_mbus_dram_info,
 163                         ORION5X_XOR_PHYS_BASE,
 164                         ORION5X_XOR_PHYS_BASE + 0x200,
 165                         IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
 166 }
 167
 168 /*****************************************************************************
 169  * Cryptographic Engines and Security Accelerator (CESA)
 170  ****************************************************************************/
 171 static void __init orion5x_crypto_init(void)
 172 {
 173         int ret;
 174
 175         ret = orion5x_setup_sram_win();
 176         if (ret)
 177                 return;
 178
 179         orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
 180                           SZ_8K, IRQ_ORION5X_CESA);
 181 }
 182
 183 /*****************************************************************************
 184  * Watchdog
 185  ****************************************************************************/
 186 void __init orion5x_wdt_init(void)
 187 {
 188         orion_wdt_init(orion5x_tclk);
 189 }
 190
 191
 192 /*****************************************************************************
 193  * Time handling
 194  ****************************************************************************/
 195 void __init orion5x_init_early(void)
 196 {
 197         orion_time_set_base(TIMER_VIRT_BASE);
 198 }
 199
 200 int orion5x_tclk;
 201
 202 int __init orion5x_find_tclk(void)
 203 {
 204         u32 dev, rev;
 205
 206         orion5x_pcie_id(&dev, &rev);
 207         if (dev == MV88F6183_DEV_ID &&
 208             (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
 209                 return 133333333;
 210
 211         return 166666667;
 212 }
 213
 214 static void orion5x_timer_init(void)
 215 {
 216         orion5x_tclk = orion5x_find_tclk();
 217
 218         orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 219                         IRQ_ORION5X_BRIDGE, orion5x_tclk);
 220 }
 221
 222 struct sys_timer orion5x_timer = {
 223         .init = orion5x_timer_init,
 224 };
 225
 226
 227 /*****************************************************************************
 228  * General
 229  ****************************************************************************/
 230 /*
 231  * Identify device ID and rev from PCIe configuration header space '0'.
 232  */
 233 static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
 234 {
 235         orion5x_pcie_id(dev, rev);
 236
 237         if (*dev == MV88F5281_DEV_ID) {
 238                 if (*rev == MV88F5281_REV_D2) {
 239                         *dev_name = "MV88F5281-D2";
 240                 } else if (*rev == MV88F5281_REV_D1) {
 241                         *dev_name = "MV88F5281-D1";
 242                 } else if (*rev == MV88F5281_REV_D0) {
 243                         *dev_name = "MV88F5281-D0";
 244                 } else {
 245                         *dev_name = "MV88F5281-Rev-Unsupported";
 246                 }
 247         } else if (*dev == MV88F5182_DEV_ID) {
 248                 if (*rev == MV88F5182_REV_A2) {
 249                         *dev_name = "MV88F5182-A2";
 250                 } else {
 251                         *dev_name = "MV88F5182-Rev-Unsupported";
 252                 }
 253         } else if (*dev == MV88F5181_DEV_ID) {
 254                 if (*rev == MV88F5181_REV_B1) {
 255                         *dev_name = "MV88F5181-Rev-B1";
 256                 } else if (*rev == MV88F5181L_REV_A1) {
 257                         *dev_name = "MV88F5181L-Rev-A1";
 258                 } else {
 259                         *dev_name = "MV88F5181(L)-Rev-Unsupported";
 260                 }
 261         } else if (*dev == MV88F6183_DEV_ID) {
 262                 if (*rev == MV88F6183_REV_B0) {
 263                         *dev_name = "MV88F6183-Rev-B0";
 264                 } else {
 265                         *dev_name = "MV88F6183-Rev-Unsupported";
 266                 }
 267         } else {
 268                 *dev_name = "Device-Unknown";
 269         }
 270 }
 271
 272 void __init orion5x_init(void)
 273 {
 274         char *dev_name;
 275         u32 dev, rev;
 276
 277         orion5x_id(&dev, &rev, &dev_name);
 278         printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
 279
 280         /*
 281          * Setup Orion address map
 282          */
 283         orion5x_setup_cpu_mbus_bridge();
 284
 285         /*
 286          * Don't issue "Wait for Interrupt" instruction if we are
 287          * running on D0 5281 silicon.
 288          */
 289         if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
 290                 printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
 291                 disable_hlt();
 292         }
 293
 294         /*
 295          * The 5082/5181l/5182/6082/6082l/6183 have crypto
 296          * while 5180n/5181/5281 don't have crypto.
 297          */
 298         if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
 299             dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
 300                 orion5x_crypto_init();
 301
 302         /*
 303          * Register watchdog driver
 304          */
 305         orion5x_wdt_init();
 306 }
 307
 308 void orion5x_restart(char mode, const char *cmd)
 309 {
 310         /*
 311          * Enable and issue soft reset
 312          */
 313         orion5x_setbits(RSTOUTn_MASK, (1 << 2));
 314         orion5x_setbits(CPU_SOFT_RESET, 1);
 315         mdelay(200);
 316         orion5x_clrbits(CPU_SOFT_RESET, 1);
 317 }
 318
 319 /*
 320  * Many orion-based systems have buggy bootloader implementations.
 321  * This is a common fixup for bogus memory tags.
 322  */
 323 void __init tag_fixup_mem32(struct tag *t, char **from,
 324                             struct meminfo *meminfo)
 325 {
 326         for (; t->hdr.size; t = tag_next(t))
 327                 if (t->hdr.tag == ATAG_MEM &&
 328                     (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
 329                      t->u.mem.start & ~PAGE_MASK)) {
 330                         printk(KERN_WARNING
 331                                "Clearing invalid memory bank %dKB@0x%08x\n",
 332                                t->u.mem.size / 1024, t->u.mem.start);
 333                         t->hdr.tag = 0;
 334                 }
 335 }