arch/arm/mach-orion5x/common.c

   1 /*
   2  * arch/arm/mach-orion5x/common.c
   3  *
   4  * Core functions for Marvell Orion 5x SoCs
   5  *
   6  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/serial_8250.h>
  18 #include <linux/mbus.h>
  19 #include <linux/mv643xx_i2c.h>
  20 #include <linux/ata_platform.h>
  21 #include <net/dsa.h>
  22 #include <asm/page.h>
  23 #include <asm/setup.h>
  24 #include <asm/timex.h>
  25 #include <asm/mach/arch.h>
  26 #include <asm/mach/map.h>
  27 #include <asm/mach/time.h>
  28 #include <mach/bridge-regs.h>
  29 #include <mach/hardware.h>
  30 #include <mach/orion5x.h>
  31 #include <plat/orion_nand.h>
  32 #include <plat/time.h>
  33 #include <plat/common.h>
  34 #include "common.h"
  35
  36 /*****************************************************************************
  37  * I/O Address Mapping
  38  ****************************************************************************/
  39 static struct map_desc orion5x_io_desc[] __initdata = {
  40         {
  41                 .virtual        = ORION5X_REGS_VIRT_BASE,
  42                 .pfn            = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
  43                 .length         = ORION5X_REGS_SIZE,
  44                 .type           = MT_DEVICE,
  45         }, {
  46                 .virtual        = ORION5X_PCIE_IO_VIRT_BASE,
  47                 .pfn            = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
  48                 .length         = ORION5X_PCIE_IO_SIZE,
  49                 .type           = MT_DEVICE,
  50         }, {
  51                 .virtual        = ORION5X_PCI_IO_VIRT_BASE,
  52                 .pfn            = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
  53                 .length         = ORION5X_PCI_IO_SIZE,
  54                 .type           = MT_DEVICE,
  55         }, {
  56                 .virtual        = ORION5X_PCIE_WA_VIRT_BASE,
  57                 .pfn            = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
  58                 .length         = ORION5X_PCIE_WA_SIZE,
  59                 .type           = MT_DEVICE,
  60         },
  61 };
  62
  63 void __init orion5x_map_io(void)
  64 {
  65         iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
  66 }
  67
  68
  69 /*****************************************************************************
  70  * EHCI0
  71  ****************************************************************************/
  72 void __init orion5x_ehci0_init(void)
  73 {
  74         orion_ehci_init(&orion5x_mbus_dram_info,
  75                         ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
  76 }
  77
  78
  79 /*****************************************************************************
  80  * EHCI1
  81  ****************************************************************************/
  82 void __init orion5x_ehci1_init(void)
  83 {
  84         orion_ehci_1_init(&orion5x_mbus_dram_info,
  85                           ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
  86 }
  87
  88
  89 /*****************************************************************************
  90  * GE00
  91  ****************************************************************************/
  92 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
  93 {
  94         orion_ge00_init(eth_data, &orion5x_mbus_dram_info,
  95                         ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
  96                         IRQ_ORION5X_ETH_ERR, orion5x_tclk);
  97 }
  98
  99
 100 /*****************************************************************************
 101  * Ethernet switch
 102  ****************************************************************************/
 103 void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
 104 {
 105         orion_ge00_switch_init(d, irq);
 106 }
 107
 108
 109 /*****************************************************************************
 110  * I2C
 111  ****************************************************************************/
 112 void __init orion5x_i2c_init(void)
 113 {
 114         orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
 115
 116 }
 117
 118
 119 /*****************************************************************************
 120  * SATA
 121  ****************************************************************************/
 122 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
 123 {
 124         orion_sata_init(sata_data, &orion5x_mbus_dram_info,
 125                         ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
 126 }
 127
 128
 129 /*****************************************************************************
 130  * SPI
 131  ****************************************************************************/
 132 void __init orion5x_spi_init()
 133 {
 134         orion_spi_init(SPI_PHYS_BASE, orion5x_tclk);
 135 }
 136
 137
 138 /*****************************************************************************
 139  * UART0
 140  ****************************************************************************/
 141 void __init orion5x_uart0_init(void)
 142 {
 143         orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
 144                          IRQ_ORION5X_UART0, orion5x_tclk);
 145 }
 146
 147 /*****************************************************************************
 148  * UART1
 149  ****************************************************************************/
 150 void __init orion5x_uart1_init(void)
 151 {
 152         orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
 153                          IRQ_ORION5X_UART1, orion5x_tclk);
 154 }
 155
 156 /*****************************************************************************
 157  * XOR engine
 158  ****************************************************************************/
 159 void __init orion5x_xor_init(void)
 160 {
 161         orion_xor0_init(&orion5x_mbus_dram_info,
 162                         ORION5X_XOR_PHYS_BASE,
 163                         ORION5X_XOR_PHYS_BASE + 0x200,
 164                         IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
 165 }
 166
 167 static struct resource orion5x_crypto_res[] = {
 168         {
 169                 .name   = "regs",
 170                 .start  = ORION5X_CRYPTO_PHYS_BASE,
 171                 .end    = ORION5X_CRYPTO_PHYS_BASE + 0xffff,
 172                 .flags  = IORESOURCE_MEM,
 173         }, {
 174                 .name   = "sram",
 175                 .start  = ORION5X_SRAM_PHYS_BASE,
 176                 .end    = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1,
 177                 .flags  = IORESOURCE_MEM,
 178         }, {
 179                 .name   = "crypto interrupt",
 180                 .start  = IRQ_ORION5X_CESA,
 181                 .end    = IRQ_ORION5X_CESA,
 182                 .flags  = IORESOURCE_IRQ,
 183         },
 184 };
 185
 186 static struct platform_device orion5x_crypto_device = {
 187         .name           = "mv_crypto",
 188         .id             = -1,
 189         .num_resources  = ARRAY_SIZE(orion5x_crypto_res),
 190         .resource       = orion5x_crypto_res,
 191 };
 192
 193 static int __init orion5x_crypto_init(void)
 194 {
 195         int ret;
 196
 197         ret = orion5x_setup_sram_win();
 198         if (ret)
 199                 return ret;
 200
 201         return platform_device_register(&orion5x_crypto_device);
 202 }
 203
 204 /*****************************************************************************
 205  * Watchdog
 206  ****************************************************************************/
 207 void __init orion5x_wdt_init(void)
 208 {
 209         orion_wdt_init(orion5x_tclk);
 210 }
 211
 212
 213 /*****************************************************************************
 214  * Time handling
 215  ****************************************************************************/
 216 void __init orion5x_init_early(void)
 217 {
 218         orion_time_set_base(TIMER_VIRT_BASE);
 219 }
 220
 221 int orion5x_tclk;
 222
 223 int __init orion5x_find_tclk(void)
 224 {
 225         u32 dev, rev;
 226
 227         orion5x_pcie_id(&dev, &rev);
 228         if (dev == MV88F6183_DEV_ID &&
 229             (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
 230                 return 133333333;
 231
 232         return 166666667;
 233 }
 234
 235 static void orion5x_timer_init(void)
 236 {
 237         orion5x_tclk = orion5x_find_tclk();
 238
 239         orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 240                         IRQ_ORION5X_BRIDGE, orion5x_tclk);
 241 }
 242
 243 struct sys_timer orion5x_timer = {
 244         .init = orion5x_timer_init,
 245 };
 246
 247
 248 /*****************************************************************************
 249  * General
 250  ****************************************************************************/
 251 /*
 252  * Identify device ID and rev from PCIe configuration header space '0'.
 253  */
 254 static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
 255 {
 256         orion5x_pcie_id(dev, rev);
 257
 258         if (*dev == MV88F5281_DEV_ID) {
 259                 if (*rev == MV88F5281_REV_D2) {
 260                         *dev_name = "MV88F5281-D2";
 261                 } else if (*rev == MV88F5281_REV_D1) {
 262                         *dev_name = "MV88F5281-D1";
 263                 } else if (*rev == MV88F5281_REV_D0) {
 264                         *dev_name = "MV88F5281-D0";
 265                 } else {
 266                         *dev_name = "MV88F5281-Rev-Unsupported";
 267                 }
 268         } else if (*dev == MV88F5182_DEV_ID) {
 269                 if (*rev == MV88F5182_REV_A2) {
 270                         *dev_name = "MV88F5182-A2";
 271                 } else {
 272                         *dev_name = "MV88F5182-Rev-Unsupported";
 273                 }
 274         } else if (*dev == MV88F5181_DEV_ID) {
 275                 if (*rev == MV88F5181_REV_B1) {
 276                         *dev_name = "MV88F5181-Rev-B1";
 277                 } else if (*rev == MV88F5181L_REV_A1) {
 278                         *dev_name = "MV88F5181L-Rev-A1";
 279                 } else {
 280                         *dev_name = "MV88F5181(L)-Rev-Unsupported";
 281                 }
 282         } else if (*dev == MV88F6183_DEV_ID) {
 283                 if (*rev == MV88F6183_REV_B0) {
 284                         *dev_name = "MV88F6183-Rev-B0";
 285                 } else {
 286                         *dev_name = "MV88F6183-Rev-Unsupported";
 287                 }
 288         } else {
 289                 *dev_name = "Device-Unknown";
 290         }
 291 }
 292
 293 void __init orion5x_init(void)
 294 {
 295         char *dev_name;
 296         u32 dev, rev;
 297
 298         orion5x_id(&dev, &rev, &dev_name);
 299         printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
 300
 301         /*
 302          * Setup Orion address map
 303          */
 304         orion5x_setup_cpu_mbus_bridge();
 305
 306         /*
 307          * Don't issue "Wait for Interrupt" instruction if we are
 308          * running on D0 5281 silicon.
 309          */
 310         if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
 311                 printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
 312                 disable_hlt();
 313         }
 314
 315         /*
 316          * The 5082/5181l/5182/6082/6082l/6183 have crypto
 317          * while 5180n/5181/5281 don't have crypto.
 318          */
 319         if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
 320             dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
 321                 orion5x_crypto_init();
 322
 323         /*
 324          * Register watchdog driver
 325          */
 326         orion5x_wdt_init();
 327 }
 328
 329 /*
 330  * Many orion-based systems have buggy bootloader implementations.
 331  * This is a common fixup for bogus memory tags.
 332  */
 333 void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t,
 334                             char **from, struct meminfo *meminfo)
 335 {
 336         for (; t->hdr.size; t = tag_next(t))
 337                 if (t->hdr.tag == ATAG_MEM &&
 338                     (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
 339                      t->u.mem.start & ~PAGE_MASK)) {
 340                         printk(KERN_WARNING
 341                                "Clearing invalid memory bank %dKB@0x%08x\n",
 342                                t->u.mem.size / 1024, t->u.mem.start);
 343                         t->hdr.tag = 0;
 344                 }
 345 }