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Merge tag 'kvm-arm-for-v4.7-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / arch / arm / mach-orion5x / pci.c
1 /*
2 * arch/arm/mach-orion5x/pci.c
3 *
4 * PCI and PCIe functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/mbus.h>
17 #include <video/vga.h>
18 #include <asm/irq.h>
19 #include <asm/mach/pci.h>
20 #include <plat/pcie.h>
21 #include <plat/addr-map.h>
22 #include "common.h"
23 #include "orion5x.h"
24
25 /*****************************************************************************
26 * Orion has one PCIe controller and one PCI controller.
27 *
28 * Note1: The local PCIe bus number is '0'. The local PCI bus number
29 * follows the scanned PCIe bridged busses, if any.
30 *
31 * Note2: It is possible for PCI/PCIe agents to access many subsystem's
32 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
33 * device bus, Orion registers, etc. However this code only enable the
34 * access to DDR banks.
35 ****************************************************************************/
36
37
38 /*****************************************************************************
39 * PCIe controller
40 ****************************************************************************/
41 #define PCIE_BASE (ORION5X_PCIE_VIRT_BASE)
42
43 void __init orion5x_pcie_id(u32 *dev, u32 *rev)
44 {
45 *dev = orion_pcie_dev_id(PCIE_BASE);
46 *rev = orion_pcie_rev(PCIE_BASE);
47 }
48
49 static int pcie_valid_config(int bus, int dev)
50 {
51 /*
52 * Don't go out when trying to access --
53 * 1. nonexisting device on local bus
54 * 2. where there's no device connected (no link)
55 */
56 if (bus == 0 && dev == 0)
57 return 1;
58
59 if (!orion_pcie_link_up(PCIE_BASE))
60 return 0;
61
62 if (bus == 0 && dev != 1)
63 return 0;
64
65 return 1;
66 }
67
68
69 /*
70 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
71 * and then reading the PCIE_CONF_DATA register. Need to make sure these
72 * transactions are atomic.
73 */
74 static DEFINE_SPINLOCK(orion5x_pcie_lock);
75
76 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
77 int size, u32 *val)
78 {
79 unsigned long flags;
80 int ret;
81
82 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
83 *val = 0xffffffff;
84 return PCIBIOS_DEVICE_NOT_FOUND;
85 }
86
87 spin_lock_irqsave(&orion5x_pcie_lock, flags);
88 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
89 spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
90
91 return ret;
92 }
93
94 static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
95 int where, int size, u32 *val)
96 {
97 int ret;
98
99 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
100 *val = 0xffffffff;
101 return PCIBIOS_DEVICE_NOT_FOUND;
102 }
103
104 /*
105 * We only support access to the non-extended configuration
106 * space when using the WA access method (or we would have to
107 * sacrifice 256M of CPU virtual address space.)
108 */
109 if (where >= 0x100) {
110 *val = 0xffffffff;
111 return PCIBIOS_DEVICE_NOT_FOUND;
112 }
113
114 ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE,
115 bus, devfn, where, size, val);
116
117 return ret;
118 }
119
120 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
121 int where, int size, u32 val)
122 {
123 unsigned long flags;
124 int ret;
125
126 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
127 return PCIBIOS_DEVICE_NOT_FOUND;
128
129 spin_lock_irqsave(&orion5x_pcie_lock, flags);
130 ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
131 spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
132
133 return ret;
134 }
135
136 static struct pci_ops pcie_ops = {
137 .read = pcie_rd_conf,
138 .write = pcie_wr_conf,
139 };
140
141
142 static int __init pcie_setup(struct pci_sys_data *sys)
143 {
144 struct resource *res;
145 int dev;
146
147 /*
148 * Generic PCIe unit setup.
149 */
150 orion_pcie_setup(PCIE_BASE);
151
152 /*
153 * Check whether to apply Orion-1/Orion-NAS PCIe config
154 * read transaction workaround.
155 */
156 dev = orion_pcie_dev_id(PCIE_BASE);
157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
158 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
159 "read transaction workaround\n");
160 mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET,
161 ORION_MBUS_PCIE_WA_ATTR,
162 ORION5X_PCIE_WA_PHYS_BASE,
163 ORION5X_PCIE_WA_SIZE);
164 pcie_ops.read = pcie_rd_conf_wa;
165 }
166
167 pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);
168
169 /*
170 * Request resources.
171 */
172 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
173 if (!res)
174 panic("pcie_setup unable to alloc resources");
175
176 /*
177 * IORESOURCE_MEM
178 */
179 res->name = "PCIe Memory Space";
180 res->flags = IORESOURCE_MEM;
181 res->start = ORION5X_PCIE_MEM_PHYS_BASE;
182 res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1;
183 if (request_resource(&iomem_resource, res))
184 panic("Request PCIe Memory resource failed\n");
185 pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
186
187 return 1;
188 }
189
190 /*****************************************************************************
191 * PCI controller
192 ****************************************************************************/
193 #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x))
194 #define PCI_MODE ORION5X_PCI_REG(0xd00)
195 #define PCI_CMD ORION5X_PCI_REG(0xc00)
196 #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
197 #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78)
198 #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c)
199
200 /*
201 * PCI_MODE bits
202 */
203 #define PCI_MODE_64BIT (1 << 2)
204 #define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
205
206 /*
207 * PCI_CMD bits
208 */
209 #define PCI_CMD_HOST_REORDER (1 << 29)
210
211 /*
212 * PCI_P2P_CONF bits
213 */
214 #define PCI_P2P_BUS_OFFS 16
215 #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
216 #define PCI_P2P_DEV_OFFS 24
217 #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
218
219 /*
220 * PCI_CONF_ADDR bits
221 */
222 #define PCI_CONF_REG(reg) ((reg) & 0xfc)
223 #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
224 #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
225 #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
226 #define PCI_CONF_ADDR_EN (1 << 31)
227
228 /*
229 * Internal configuration space
230 */
231 #define PCI_CONF_FUNC_STAT_CMD 0
232 #define PCI_CONF_REG_STAT_CMD 4
233 #define PCIX_STAT 0x64
234 #define PCIX_STAT_BUS_OFFS 8
235 #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
236
237 /*
238 * PCI Address Decode Windows registers
239 */
240 #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
241 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
242 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
243 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : NULL)
244 #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
245 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
246 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
247 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : NULL)
248 #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
249 #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)
250
251 /*
252 * PCI configuration helpers for BAR settings
253 */
254 #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
255 #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
256 #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
257
258 /*
259 * PCI config cycles are done by programming the PCI_CONF_ADDR register
260 * and then reading the PCI_CONF_DATA register. Need to make sure these
261 * transactions are atomic.
262 */
263 static DEFINE_SPINLOCK(orion5x_pci_lock);
264
265 static int orion5x_pci_cardbus_mode;
266
267 static int orion5x_pci_local_bus_nr(void)
268 {
269 u32 conf = readl(PCI_P2P_CONF);
270 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
271 }
272
273 static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
274 u32 where, u32 size, u32 *val)
275 {
276 unsigned long flags;
277 spin_lock_irqsave(&orion5x_pci_lock, flags);
278
279 writel(PCI_CONF_BUS(bus) |
280 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
281 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
282
283 *val = readl(PCI_CONF_DATA);
284
285 if (size == 1)
286 *val = (*val >> (8*(where & 0x3))) & 0xff;
287 else if (size == 2)
288 *val = (*val >> (8*(where & 0x3))) & 0xffff;
289
290 spin_unlock_irqrestore(&orion5x_pci_lock, flags);
291
292 return PCIBIOS_SUCCESSFUL;
293 }
294
295 static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
296 u32 where, u32 size, u32 val)
297 {
298 unsigned long flags;
299 int ret = PCIBIOS_SUCCESSFUL;
300
301 spin_lock_irqsave(&orion5x_pci_lock, flags);
302
303 writel(PCI_CONF_BUS(bus) |
304 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
305 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
306
307 if (size == 4) {
308 __raw_writel(val, PCI_CONF_DATA);
309 } else if (size == 2) {
310 __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
311 } else if (size == 1) {
312 __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
313 } else {
314 ret = PCIBIOS_BAD_REGISTER_NUMBER;
315 }
316
317 spin_unlock_irqrestore(&orion5x_pci_lock, flags);
318
319 return ret;
320 }
321
322 static int orion5x_pci_valid_config(int bus, u32 devfn)
323 {
324 if (bus == orion5x_pci_local_bus_nr()) {
325 /*
326 * Don't go out for local device
327 */
328 if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
329 return 0;
330
331 /*
332 * When the PCI signals are directly connected to a
333 * Cardbus slot, ignore all but device IDs 0 and 1.
334 */
335 if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
336 return 0;
337 }
338
339 return 1;
340 }
341
342 static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
343 int where, int size, u32 *val)
344 {
345 if (!orion5x_pci_valid_config(bus->number, devfn)) {
346 *val = 0xffffffff;
347 return PCIBIOS_DEVICE_NOT_FOUND;
348 }
349
350 return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
351 PCI_FUNC(devfn), where, size, val);
352 }
353
354 static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
355 int where, int size, u32 val)
356 {
357 if (!orion5x_pci_valid_config(bus->number, devfn))
358 return PCIBIOS_DEVICE_NOT_FOUND;
359
360 return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
361 PCI_FUNC(devfn), where, size, val);
362 }
363
364 static struct pci_ops pci_ops = {
365 .read = orion5x_pci_rd_conf,
366 .write = orion5x_pci_wr_conf,
367 };
368
369 static void __init orion5x_pci_set_bus_nr(int nr)
370 {
371 u32 p2p = readl(PCI_P2P_CONF);
372
373 if (readl(PCI_MODE) & PCI_MODE_PCIX) {
374 /*
375 * PCI-X mode
376 */
377 u32 pcix_status, bus, dev;
378 bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
379 dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
380 orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
381 pcix_status &= ~PCIX_STAT_BUS_MASK;
382 pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
383 orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
384 } else {
385 /*
386 * PCI Conventional mode
387 */
388 p2p &= ~PCI_P2P_BUS_MASK;
389 p2p |= (nr << PCI_P2P_BUS_OFFS);
390 writel(p2p, PCI_P2P_CONF);
391 }
392 }
393
394 static void __init orion5x_pci_master_slave_enable(void)
395 {
396 int bus_nr, func, reg;
397 u32 val;
398
399 bus_nr = orion5x_pci_local_bus_nr();
400 func = PCI_CONF_FUNC_STAT_CMD;
401 reg = PCI_CONF_REG_STAT_CMD;
402 orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
403 val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
404 orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
405 }
406
407 static void __init orion5x_setup_pci_wins(void)
408 {
409 const struct mbus_dram_target_info *dram = mv_mbus_dram_info();
410 u32 win_enable;
411 int bus;
412 int i;
413
414 /*
415 * First, disable windows.
416 */
417 win_enable = 0xffffffff;
418 writel(win_enable, PCI_BAR_ENABLE);
419
420 /*
421 * Setup windows for DDR banks.
422 */
423 bus = orion5x_pci_local_bus_nr();
424
425 for (i = 0; i < dram->num_cs; i++) {
426 const struct mbus_dram_window *cs = dram->cs + i;
427 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
428 u32 reg;
429 u32 val;
430
431 /*
432 * Write DRAM bank base address register.
433 */
434 reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
435 orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
436 val = (cs->base & 0xfffff000) | (val & 0xfff);
437 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
438
439 /*
440 * Write DRAM bank size register.
441 */
442 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
443 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
444 writel((cs->size - 1) & 0xfffff000,
445 PCI_BAR_SIZE_DDR_CS(cs->cs_index));
446 writel(cs->base & 0xfffff000,
447 PCI_BAR_REMAP_DDR_CS(cs->cs_index));
448
449 /*
450 * Enable decode window for this chip select.
451 */
452 win_enable &= ~(1 << cs->cs_index);
453 }
454
455 /*
456 * Re-enable decode windows.
457 */
458 writel(win_enable, PCI_BAR_ENABLE);
459
460 /*
461 * Disable automatic update of address remapping when writing to BARs.
462 */
463 orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
464 }
465
466 static int __init pci_setup(struct pci_sys_data *sys)
467 {
468 struct resource *res;
469
470 /*
471 * Point PCI unit MBUS decode windows to DRAM space.
472 */
473 orion5x_setup_pci_wins();
474
475 /*
476 * Master + Slave enable
477 */
478 orion5x_pci_master_slave_enable();
479
480 /*
481 * Force ordering
482 */
483 orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
484
485 pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE);
486
487 /*
488 * Request resources
489 */
490 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
491 if (!res)
492 panic("pci_setup unable to alloc resources");
493
494 /*
495 * IORESOURCE_MEM
496 */
497 res->name = "PCI Memory Space";
498 res->flags = IORESOURCE_MEM;
499 res->start = ORION5X_PCI_MEM_PHYS_BASE;
500 res->end = res->start + ORION5X_PCI_MEM_SIZE - 1;
501 if (request_resource(&iomem_resource, res))
502 panic("Request PCI Memory resource failed\n");
503 pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
504
505 return 1;
506 }
507
508
509 /*****************************************************************************
510 * General PCIe + PCI
511 ****************************************************************************/
512 static void rc_pci_fixup(struct pci_dev *dev)
513 {
514 /*
515 * Prevent enumeration of root complex.
516 */
517 if (dev->bus->parent == NULL && dev->devfn == 0) {
518 int i;
519
520 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
521 dev->resource[i].start = 0;
522 dev->resource[i].end = 0;
523 dev->resource[i].flags = 0;
524 }
525 }
526 }
527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
528
529 static int orion5x_pci_disabled __initdata;
530
531 void __init orion5x_pci_disable(void)
532 {
533 orion5x_pci_disabled = 1;
534 }
535
536 void __init orion5x_pci_set_cardbus_mode(void)
537 {
538 orion5x_pci_cardbus_mode = 1;
539 }
540
541 int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
542 {
543 vga_base = ORION5X_PCIE_MEM_PHYS_BASE;
544
545 if (nr == 0) {
546 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
547 return pcie_setup(sys);
548 }
549
550 if (nr == 1 && !orion5x_pci_disabled) {
551 orion5x_pci_set_bus_nr(sys->busnr);
552 return pci_setup(sys);
553 }
554
555 return 0;
556 }
557
558 struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
559 {
560 if (nr == 0)
561 return pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
562 &sys->resources);
563
564 if (nr == 1 && !orion5x_pci_disabled)
565 return pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys,
566 &sys->resources);
567
568 BUG();
569 return NULL;
570 }
571
572 int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
573 {
574 int bus = dev->bus->number;
575
576 /*
577 * PCIe endpoint?
578 */
579 if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr())
580 return IRQ_ORION5X_PCIE0_INT;
581
582 return -1;
583 }
Linux kernel - Deliverables
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