arch/arm/mach-pxa/cpufreq-pxa2xx.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/cpufreq-pxa2xx.c
   3  *
   4  *  Copyright (C) 2002,2003 Intrinsyc Software
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  *
  20  * History:
  21  *   31-Jul-2002 : Initial version [FB]
  22  *   29-Jan-2003 : added PXA255 support [FB]
  23  *   20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
  24  *
  25  * Note:
  26  *   This driver may change the memory bus clock rate, but will not do any
  27  *   platform specific access timing changes... for example if you have flash
  28  *   memory connected to CS0, you will need to register a platform specific
  29  *   notifier which will adjust the memory access strobes to maintain a
  30  *   minimum strobe width.
  31  *
  32  */
  33
  34 #include <linux/kernel.h>
  35 #include <linux/module.h>
  36 #include <linux/sched.h>
  37 #include <linux/init.h>
  38 #include <linux/cpufreq.h>
  39
  40 #include <mach/pxa2xx-regs.h>
  41
  42 #ifdef DEBUG
  43 static unsigned int freq_debug;
  44 module_param(freq_debug, uint, 0);
  45 MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
  46 #else
  47 #define freq_debug  0
  48 #endif
  49
  50 static unsigned int pxa27x_maxfreq;
  51 module_param(pxa27x_maxfreq, uint, 0);
  52 MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
  53                  "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
  54
  55 typedef struct {
  56         unsigned int khz;
  57         unsigned int membus;
  58         unsigned int cccr;
  59         unsigned int div2;
  60         unsigned int cclkcfg;
  61 } pxa_freqs_t;
  62
  63 /* Define the refresh period in mSec for the SDRAM and the number of rows */
  64 #define SDRAM_TREF      64      /* standard 64ms SDRAM */
  65 static unsigned int sdram_rows;
  66
  67 #define CCLKCFG_TURBO           0x1
  68 #define CCLKCFG_FCS             0x2
  69 #define CCLKCFG_HALFTURBO       0x4
  70 #define CCLKCFG_FASTBUS         0x8
  71 #define MDREFR_DB2_MASK         (MDREFR_K2DB2 | MDREFR_K1DB2)
  72 #define MDREFR_DRI_MASK         0xFFF
  73
  74 #define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
  75 #define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
  76
  77 /*
  78  * PXA255 definitions
  79  */
  80 /* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
  81 #define CCLKCFG                 CCLKCFG_TURBO | CCLKCFG_FCS
  82
  83 static pxa_freqs_t pxa255_run_freqs[] =
  84 {
  85         /* CPU   MEMBUS  CCCR  DIV2 CCLKCFG        run  turbo PXbus SDRAM */
  86         { 99500,  99500, 0x121, 1,  CCLKCFG},   /*  99,   99,   50,   50  */
  87         {132700, 132700, 0x123, 1,  CCLKCFG},   /* 133,  133,   66,   66  */
  88         {199100,  99500, 0x141, 0,  CCLKCFG},   /* 199,  199,   99,   99  */
  89         {265400, 132700, 0x143, 1,  CCLKCFG},   /* 265,  265,  133,   66  */
  90         {331800, 165900, 0x145, 1,  CCLKCFG},   /* 331,  331,  166,   83  */
  91         {398100,  99500, 0x161, 0,  CCLKCFG},   /* 398,  398,  196,   99  */
  92 };
  93
  94 /* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
  95 static pxa_freqs_t pxa255_turbo_freqs[] =
  96 {
  97         /* CPU   MEMBUS  CCCR  DIV2 CCLKCFG        run  turbo PXbus SDRAM */
  98         { 99500, 99500,  0x121, 1,  CCLKCFG},   /*  99,   99,   50,   50  */
  99         {199100, 99500,  0x221, 0,  CCLKCFG},   /*  99,  199,   50,   99  */
 100         {298500, 99500,  0x321, 0,  CCLKCFG},   /*  99,  287,   50,   99  */
 101         {298600, 99500,  0x1c1, 0,  CCLKCFG},   /* 199,  287,   99,   99  */
 102         {398100, 99500,  0x241, 0,  CCLKCFG},   /* 199,  398,   99,   99  */
 103 };
 104
 105 #define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
 106 #define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
 107
 108 static struct cpufreq_frequency_table
 109         pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
 110 static struct cpufreq_frequency_table
 111         pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
 112
 113 static unsigned int pxa255_turbo_table;
 114 module_param(pxa255_turbo_table, uint, 0);
 115 MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
 116
 117 /*
 118  * PXA270 definitions
 119  *
 120  * For the PXA27x:
 121  * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
 122  *
 123  * A = 0 => memory controller clock from table 3-7,
 124  * A = 1 => memory controller clock = system bus clock
 125  * Run mode frequency   = 13 MHz * L
 126  * Turbo mode frequency = 13 MHz * L * N
 127  * System bus frequency = 13 MHz * L / (B + 1)
 128  *
 129  * In CCCR:
 130  * A = 1
 131  * L = 16         oscillator to run mode ratio
 132  * 2N = 6         2 * (turbo mode to run mode ratio)
 133  *
 134  * In CCLKCFG:
 135  * B = 1          Fast bus mode
 136  * HT = 0         Half-Turbo mode
 137  * T = 1          Turbo mode
 138  *
 139  * For now, just support some of the combinations in table 3-7 of
 140  * PXA27x Processor Family Developer's Manual to simplify frequency
 141  * change sequences.
 142  */
 143 #define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
 144 #define CCLKCFG2(B, HT, T) \
 145   (CCLKCFG_FCS | \
 146    ((B)  ? CCLKCFG_FASTBUS : 0) | \
 147    ((HT) ? CCLKCFG_HALFTURBO : 0) | \
 148    ((T)  ? CCLKCFG_TURBO : 0))
 149
 150 static pxa_freqs_t pxa27x_freqs[] = {
 151         {104000, 104000, PXA27x_CCCR(1,  8, 2), 0, CCLKCFG2(1, 0, 1)},
 152         {156000, 104000, PXA27x_CCCR(1,  8, 6), 0, CCLKCFG2(1, 1, 1)},
 153         {208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1)},
 154         {312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1)},
 155         {416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1)},
 156         {520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1)},
 157         {624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1)}
 158 };
 159
 160 #define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
 161 static struct cpufreq_frequency_table
 162         pxa27x_freq_table[NUM_PXA27x_FREQS+1];
 163
 164 extern unsigned get_clk_frequency_khz(int info);
 165
 166 static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
 167                              pxa_freqs_t **pxa_freqs)
 168 {
 169         if (cpu_is_pxa25x()) {
 170                 if (!pxa255_turbo_table) {
 171                         *pxa_freqs = pxa255_run_freqs;
 172                         *freq_table = pxa255_run_freq_table;
 173                 } else {
 174                         *pxa_freqs = pxa255_turbo_freqs;
 175                         *freq_table = pxa255_turbo_freq_table;
 176                 }
 177         }
 178         if (cpu_is_pxa27x()) {
 179                 *pxa_freqs = pxa27x_freqs;
 180                 *freq_table = pxa27x_freq_table;
 181         }
 182 }
 183
 184 static void pxa27x_guess_max_freq(void)
 185 {
 186         if (!pxa27x_maxfreq) {
 187                 pxa27x_maxfreq = 416000;
 188                 printk(KERN_INFO "PXA CPU 27x max frequency not defined "
 189                        "(pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
 190                        pxa27x_maxfreq);
 191         } else {
 192                 pxa27x_maxfreq *= 1000;
 193         }
 194 }
 195
 196 static void init_sdram_rows(void)
 197 {
 198         uint32_t mdcnfg = MDCNFG;
 199         unsigned int drac2 = 0, drac0 = 0;
 200
 201         if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
 202                 drac2 = MDCNFG_DRAC2(mdcnfg);
 203
 204         if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
 205                 drac0 = MDCNFG_DRAC0(mdcnfg);
 206
 207         sdram_rows = 1 << (11 + max(drac0, drac2));
 208 }
 209
 210 static u32 mdrefr_dri(unsigned int freq)
 211 {
 212         u32 dri = 0;
 213
 214         if (cpu_is_pxa25x())
 215                 dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
 216         if (cpu_is_pxa27x())
 217                 dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
 218         return dri;
 219 }
 220
 221 /* find a valid frequency point */
 222 static int pxa_verify_policy(struct cpufreq_policy *policy)
 223 {
 224         struct cpufreq_frequency_table *pxa_freqs_table;
 225         pxa_freqs_t *pxa_freqs;
 226         int ret;
 227
 228         find_freq_tables(&pxa_freqs_table, &pxa_freqs);
 229         ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
 230
 231         if (freq_debug)
 232                 pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n",
 233                          policy->min, policy->max);
 234
 235         return ret;
 236 }
 237
 238 static unsigned int pxa_cpufreq_get(unsigned int cpu)
 239 {
 240         return get_clk_frequency_khz(0);
 241 }
 242
 243 static int pxa_set_target(struct cpufreq_policy *policy,
 244                           unsigned int target_freq,
 245                           unsigned int relation)
 246 {
 247         struct cpufreq_frequency_table *pxa_freqs_table;
 248         pxa_freqs_t *pxa_freq_settings;
 249         struct cpufreq_freqs freqs;
 250         unsigned int idx;
 251         unsigned long flags;
 252         unsigned int new_freq_cpu, new_freq_mem;
 253         unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
 254
 255         /* Get the current policy */
 256         find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
 257
 258         /* Lookup the next frequency */
 259         if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
 260                                            target_freq, relation, &idx)) {
 261                 return -EINVAL;
 262         }
 263
 264         new_freq_cpu = pxa_freq_settings[idx].khz;
 265         new_freq_mem = pxa_freq_settings[idx].membus;
 266         freqs.old = policy->cur;
 267         freqs.new = new_freq_cpu;
 268         freqs.cpu = policy->cpu;
 269
 270         if (freq_debug)
 271                 pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, "
 272                          "(SDRAM %d Mhz)\n",
 273                          freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
 274                          (new_freq_mem / 2000) : (new_freq_mem / 1000));
 275
 276         /*
 277          * Tell everyone what we're about to do...
 278          * you should add a notify client with any platform specific
 279          * Vcc changing capability
 280          */
 281         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 282
 283         /* Calculate the next MDREFR.  If we're slowing down the SDRAM clock
 284          * we need to preset the smaller DRI before the change.  If we're
 285          * speeding up we need to set the larger DRI value after the change.
 286          */
 287         preset_mdrefr = postset_mdrefr = MDREFR;
 288         if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
 289                 preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
 290                 preset_mdrefr |= mdrefr_dri(new_freq_mem);
 291         }
 292         postset_mdrefr =
 293                 (postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem);
 294
 295         /* If we're dividing the memory clock by two for the SDRAM clock, this
 296          * must be set prior to the change.  Clearing the divide must be done
 297          * after the change.
 298          */
 299         if (pxa_freq_settings[idx].div2) {
 300                 preset_mdrefr  |= MDREFR_DB2_MASK;
 301                 postset_mdrefr |= MDREFR_DB2_MASK;
 302         } else {
 303                 postset_mdrefr &= ~MDREFR_DB2_MASK;
 304         }
 305
 306         local_irq_save(flags);
 307
 308         /* Set new the CCCR and prepare CCLKCFG */
 309         CCCR = pxa_freq_settings[idx].cccr;
 310         cclkcfg = pxa_freq_settings[idx].cclkcfg;
 311
 312         asm volatile("                                                  \n\
 313                 ldr     r4, [%1]                /* load MDREFR */       \n\
 314                 b       2f                                              \n\
 315                 .align  5                                               \n\
 316 1:                                                                      \n\
 317                 str     %3, [%1]                /* preset the MDREFR */ \n\
 318                 mcr     p14, 0, %2, c6, c0, 0   /* set CCLKCFG[FCS] */  \n\
 319                 str     %4, [%1]                /* postset the MDREFR */ \n\
 320                                                                         \n\
 321                 b       3f                                              \n\
 322 2:              b       1b                                              \n\
 323 3:              nop                                                     \n\
 324           "
 325                      : "=&r" (unused)
 326                      : "r" (&MDREFR), "r" (cclkcfg),
 327                        "r" (preset_mdrefr), "r" (postset_mdrefr)
 328                      : "r4", "r5");
 329         local_irq_restore(flags);
 330
 331         /*
 332          * Tell everyone what we've just done...
 333          * you should add a notify client with any platform specific
 334          * SDRAM refresh timer adjustments
 335          */
 336         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 337
 338         return 0;
 339 }
 340
 341 static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
 342 {
 343         int i;
 344         unsigned int freq;
 345         struct cpufreq_frequency_table *pxa255_freq_table;
 346         pxa_freqs_t *pxa255_freqs;
 347
 348         /* try to guess pxa27x cpu */
 349         if (cpu_is_pxa27x())
 350                 pxa27x_guess_max_freq();
 351
 352         init_sdram_rows();
 353
 354         /* set default policy and cpuinfo */
 355         policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
 356         policy->cur = get_clk_frequency_khz(0);    /* current freq */
 357         policy->min = policy->max = policy->cur;
 358
 359         /* Generate pxa25x the run cpufreq_frequency_table struct */
 360         for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
 361                 pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
 362                 pxa255_run_freq_table[i].index = i;
 363         }
 364         pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
 365
 366         /* Generate pxa25x the turbo cpufreq_frequency_table struct */
 367         for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
 368                 pxa255_turbo_freq_table[i].frequency =
 369                         pxa255_turbo_freqs[i].khz;
 370                 pxa255_turbo_freq_table[i].index = i;
 371         }
 372         pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
 373
 374         pxa255_turbo_table = !!pxa255_turbo_table;
 375
 376         /* Generate the pxa27x cpufreq_frequency_table struct */
 377         for (i = 0; i < NUM_PXA27x_FREQS; i++) {
 378                 freq = pxa27x_freqs[i].khz;
 379                 if (freq > pxa27x_maxfreq)
 380                         break;
 381                 pxa27x_freq_table[i].frequency = freq;
 382                 pxa27x_freq_table[i].index = i;
 383         }
 384         pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
 385
 386         /*
 387          * Set the policy's minimum and maximum frequencies from the tables
 388          * just constructed.  This sets cpuinfo.mxx_freq, min and max.
 389          */
 390         if (cpu_is_pxa25x()) {
 391                 find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
 392                 pr_info("PXA255 cpufreq using %s frequency table\n",
 393                         pxa255_turbo_table ? "turbo" : "run");
 394                 cpufreq_frequency_table_cpuinfo(policy, pxa255_freq_table);
 395         }
 396         else if (cpu_is_pxa27x())
 397                 cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table);
 398
 399         printk(KERN_INFO "PXA CPU frequency change support initialized\n");
 400
 401         return 0;
 402 }
 403
 404 static struct cpufreq_driver pxa_cpufreq_driver = {
 405         .verify = pxa_verify_policy,
 406         .target = pxa_set_target,
 407         .init   = pxa_cpufreq_init,
 408         .get    = pxa_cpufreq_get,
 409         .name   = "PXA2xx",
 410 };
 411
 412 static int __init pxa_cpu_init(void)
 413 {
 414         int ret = -ENODEV;
 415         if (cpu_is_pxa25x() || cpu_is_pxa27x())
 416                 ret = cpufreq_register_driver(&pxa_cpufreq_driver);
 417         return ret;
 418 }
 419
 420 static void __exit pxa_cpu_exit(void)
 421 {
 422         cpufreq_unregister_driver(&pxa_cpufreq_driver);
 423 }
 424
 425
 426 MODULE_AUTHOR("Intrinsyc Software Inc.");
 427 MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
 428 MODULE_LICENSE("GPL");
 429 module_init(pxa_cpu_init);
 430 module_exit(pxa_cpu_exit);