arch/arm/mach-pxa/include/mach/pxa3xx-regs.h

   1 /*
   2  * arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
   3  *
   4  * PXA3xx specific register definitions
   5  *
   6  * Copyright (C) 2007 Marvell International Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ASM_ARCH_PXA3XX_REGS_H
  14 #define __ASM_ARCH_PXA3XX_REGS_H
  15
  16 /*
  17  * Oscillator Configuration Register (OSCC)
  18  */
  19 #define OSCC           __REG(0x41350000)  /* Oscillator Configuration Register */
  20
  21 #define OSCC_PEN       (1 << 11)       /* 13MHz POUT */
  22
  23
  24 /*
  25  * Service Power Management Unit (MPMU)
  26  */
  27 #define PMCR            __REG(0x40F50000)       /* Power Manager Control Register */
  28 #define PSR             __REG(0x40F50004)       /* Power Manager S2 Status Register */
  29 #define PSPR            __REG(0x40F50008)       /* Power Manager Scratch Pad Register */
  30 #define PCFR            __REG(0x40F5000C)       /* Power Manager General Configuration Register */
  31 #define PWER            __REG(0x40F50010)       /* Power Manager Wake-up Enable Register */
  32 #define PWSR            __REG(0x40F50014)       /* Power Manager Wake-up Status Register */
  33 #define PECR            __REG(0x40F50018)       /* Power Manager EXT_WAKEUP[1:0] Control Register */
  34 #define DCDCSR          __REG(0x40F50080)       /* DC-DC Controller Status Register */
  35 #define PVCR            __REG(0x40F50100)       /* Power Manager Voltage Change Control Register */
  36 #define PCMD(x)         __REG(0x40F50110 + ((x) << 2))
  37
  38 /*
  39  * Slave Power Managment Unit
  40  */
  41 #define ASCR            __REG(0x40f40000)       /* Application Subsystem Power Status/Configuration */
  42 #define ARSR            __REG(0x40f40004)       /* Application Subsystem Reset Status */
  43 #define AD3ER           __REG(0x40f40008)       /* Application Subsystem Wake-Up from D3 Enable */
  44 #define AD3SR           __REG(0x40f4000c)       /* Application Subsystem Wake-Up from D3 Status */
  45 #define AD2D0ER         __REG(0x40f40010)       /* Application Subsystem Wake-Up from D2 to D0 Enable */
  46 #define AD2D0SR         __REG(0x40f40014)       /* Application Subsystem Wake-Up from D2 to D0 Status */
  47 #define AD2D1ER         __REG(0x40f40018)       /* Application Subsystem Wake-Up from D2 to D1 Enable */
  48 #define AD2D1SR         __REG(0x40f4001c)       /* Application Subsystem Wake-Up from D2 to D1 Status */
  49 #define AD1D0ER         __REG(0x40f40020)       /* Application Subsystem Wake-Up from D1 to D0 Enable */
  50 #define AD1D0SR         __REG(0x40f40024)       /* Application Subsystem Wake-Up from D1 to D0 Status */
  51 #define AGENP           __REG(0x40f4002c)       /* Application Subsystem General Purpose */
  52 #define AD3R            __REG(0x40f40030)       /* Application Subsystem D3 Configuration */
  53 #define AD2R            __REG(0x40f40034)       /* Application Subsystem D2 Configuration */
  54 #define AD1R            __REG(0x40f40038)       /* Application Subsystem D1 Configuration */
  55
  56 /*
  57  * Application Subsystem Configuration bits.
  58  */
  59 #define ASCR_RDH                (1 << 31)
  60 #define ASCR_D1S                (1 << 2)
  61 #define ASCR_D2S                (1 << 1)
  62 #define ASCR_D3S                (1 << 0)
  63
  64 /*
  65  * Application Reset Status bits.
  66  */
  67 #define ARSR_GPR                (1 << 3)
  68 #define ARSR_LPMR               (1 << 2)
  69 #define ARSR_WDT                (1 << 1)
  70 #define ARSR_HWR                (1 << 0)
  71
  72 /*
  73  * Application Subsystem Wake-Up bits.
  74  */
  75 #define ADXER_WRTC              (1 << 31)       /* RTC */
  76 #define ADXER_WOST              (1 << 30)       /* OS Timer */
  77 #define ADXER_WTSI              (1 << 29)       /* Touchscreen */
  78 #define ADXER_WUSBH             (1 << 28)       /* USB host */
  79 #define ADXER_WUSB2             (1 << 26)       /* USB client 2.0 */
  80 #define ADXER_WMSL0             (1 << 24)       /* MSL port 0*/
  81 #define ADXER_WDMUX3            (1 << 23)       /* USB EDMUX3 */
  82 #define ADXER_WDMUX2            (1 << 22)       /* USB EDMUX2 */
  83 #define ADXER_WKP               (1 << 21)       /* Keypad */
  84 #define ADXER_WUSIM1            (1 << 20)       /* USIM Port 1 */
  85 #define ADXER_WUSIM0            (1 << 19)       /* USIM Port 0 */
  86 #define ADXER_WOTG              (1 << 16)       /* USBOTG input */
  87 #define ADXER_MFP_WFLASH        (1 << 15)       /* MFP: Data flash busy */
  88 #define ADXER_MFP_GEN12         (1 << 14)       /* MFP: MMC3/GPIO/OST inputs */
  89 #define ADXER_MFP_WMMC2         (1 << 13)       /* MFP: MMC2 */
  90 #define ADXER_MFP_WMMC1         (1 << 12)       /* MFP: MMC1 */
  91 #define ADXER_MFP_WI2C          (1 << 11)       /* MFP: I2C */
  92 #define ADXER_MFP_WSSP4         (1 << 10)       /* MFP: SSP4 */
  93 #define ADXER_MFP_WSSP3         (1 << 9)        /* MFP: SSP3 */
  94 #define ADXER_MFP_WMAXTRIX      (1 << 8)        /* MFP: matrix keypad */
  95 #define ADXER_MFP_WUART3        (1 << 7)        /* MFP: UART3 */
  96 #define ADXER_MFP_WUART2        (1 << 6)        /* MFP: UART2 */
  97 #define ADXER_MFP_WUART1        (1 << 5)        /* MFP: UART1 */
  98 #define ADXER_MFP_WSSP2         (1 << 4)        /* MFP: SSP2 */
  99 #define ADXER_MFP_WSSP1         (1 << 3)        /* MFP: SSP1 */
 100 #define ADXER_MFP_WAC97         (1 << 2)        /* MFP: AC97 */
 101 #define ADXER_WEXTWAKE1         (1 << 1)        /* External Wake 1 */
 102 #define ADXER_WEXTWAKE0         (1 << 0)        /* External Wake 0 */
 103
 104 /*
 105  * AD3R/AD2R/AD1R bits.  R2-R5 are only defined for PXA320.
 106  */
 107 #define ADXR_L2                 (1 << 8)
 108 #define ADXR_R5                 (1 << 5)
 109 #define ADXR_R4                 (1 << 4)
 110 #define ADXR_R3                 (1 << 3)
 111 #define ADXR_R2                 (1 << 2)
 112 #define ADXR_R1                 (1 << 1)
 113 #define ADXR_R0                 (1 << 0)
 114
 115 /*
 116  * Values for PWRMODE CP15 register
 117  */
 118 #define PXA3xx_PM_S3D4C4        0x07    /* aka deep sleep */
 119 #define PXA3xx_PM_S2D3C4        0x06    /* aka sleep */
 120 #define PXA3xx_PM_S0D2C2        0x03    /* aka standby */
 121 #define PXA3xx_PM_S0D1C2        0x02    /* aka LCD refresh */
 122 #define PXA3xx_PM_S0D0C1        0x01
 123
 124 /*
 125  * Application Subsystem Clock
 126  */
 127 #define ACCR            __REG(0x41340000)       /* Application Subsystem Clock Configuration Register */
 128 #define ACSR            __REG(0x41340004)       /* Application Subsystem Clock Status Register */
 129 #define AICSR           __REG(0x41340008)       /* Application Subsystem Interrupt Control/Status Register */
 130 #define CKENA           __REG(0x4134000C)       /* A Clock Enable Register */
 131 #define CKENB           __REG(0x41340010)       /* B Clock Enable Register */
 132 #define AC97_DIV        __REG(0x41340014)       /* AC97 clock divisor value register */
 133
 134 #define ACCR_XPDIS              (1 << 31)       /* Core PLL Output Disable */
 135 #define ACCR_SPDIS              (1 << 30)       /* System PLL Output Disable */
 136 #define ACCR_D0CS               (1 << 26)       /* D0 Mode Clock Select */
 137 #define ACCR_PCCE               (1 << 11)       /* Power Mode Change Clock Enable */
 138 #define ACCR_DDR_D0CS           (1 << 7)        /* DDR SDRAM clock frequency in D0CS (PXA31x only) */
 139
 140 #define ACCR_SMCFS_MASK         (0x7 << 23)     /* Static Memory Controller Frequency Select */
 141 #define ACCR_SFLFS_MASK         (0x3 << 18)     /* Frequency Select for Internal Memory Controller */
 142 #define ACCR_XSPCLK_MASK        (0x3 << 16)     /* Core Frequency during Frequency Change */
 143 #define ACCR_HSS_MASK           (0x3 << 14)     /* System Bus-Clock Frequency Select */
 144 #define ACCR_DMCFS_MASK         (0x3 << 12)     /* Dynamic Memory Controller Clock Frequency Select */
 145 #define ACCR_XN_MASK            (0x7 << 8)      /* Core PLL Turbo-Mode-to-Run-Mode Ratio */
 146 #define ACCR_XL_MASK            (0x1f)          /* Core PLL Run-Mode-to-Oscillator Ratio */
 147
 148 #define ACCR_SMCFS(x)           (((x) & 0x7) << 23)
 149 #define ACCR_SFLFS(x)           (((x) & 0x3) << 18)
 150 #define ACCR_XSPCLK(x)          (((x) & 0x3) << 16)
 151 #define ACCR_HSS(x)             (((x) & 0x3) << 14)
 152 #define ACCR_DMCFS(x)           (((x) & 0x3) << 12)
 153 #define ACCR_XN(x)              (((x) & 0x7) << 8)
 154 #define ACCR_XL(x)              ((x) & 0x1f)
 155
 156 /*
 157  * Clock Enable Bit
 158  */
 159 #define CKEN_LCD        1       /* < LCD Clock Enable */
 160 #define CKEN_USBH       2       /* < USB host clock enable */
 161 #define CKEN_CAMERA     3       /* < Camera interface clock enable */
 162 #define CKEN_NAND       4       /* < NAND Flash Controller Clock Enable */
 163 #define CKEN_USB2       6       /* < USB 2.0 client clock enable. */
 164 #define CKEN_DMC        8       /* < Dynamic Memory Controller clock enable */
 165 #define CKEN_SMC        9       /* < Static Memory Controller clock enable */
 166 #define CKEN_ISC        10      /* < Internal SRAM Controller clock enable */
 167 #define CKEN_BOOT       11      /* < Boot rom clock enable */
 168 #define CKEN_MMC1       12      /* < MMC1 Clock enable */
 169 #define CKEN_MMC2       13      /* < MMC2 clock enable */
 170 #define CKEN_KEYPAD     14      /* < Keypand Controller Clock Enable */
 171 #define CKEN_CIR        15      /* < Consumer IR Clock Enable */
 172 #define CKEN_USIM0      17      /* < USIM[0] Clock Enable */
 173 #define CKEN_USIM1      18      /* < USIM[1] Clock Enable */
 174 #define CKEN_TPM        19      /* < TPM clock enable */
 175 #define CKEN_UDC        20      /* < UDC clock enable */
 176 #define CKEN_BTUART     21      /* < BTUART clock enable */
 177 #define CKEN_FFUART     22      /* < FFUART clock enable */
 178 #define CKEN_STUART     23      /* < STUART clock enable */
 179 #define CKEN_AC97       24      /* < AC97 clock enable */
 180 #define CKEN_TOUCH      25      /* < Touch screen Interface Clock Enable */
 181 #define CKEN_SSP1       26      /* < SSP1 clock enable */
 182 #define CKEN_SSP2       27      /* < SSP2 clock enable */
 183 #define CKEN_SSP3       28      /* < SSP3 clock enable */
 184 #define CKEN_SSP4       29      /* < SSP4 clock enable */
 185 #define CKEN_MSL0       30      /* < MSL0 clock enable */
 186 #define CKEN_PWM0       32      /* < PWM[0] clock enable */
 187 #define CKEN_PWM1       33      /* < PWM[1] clock enable */
 188 #define CKEN_I2C        36      /* < I2C clock enable */
 189 #define CKEN_INTC       38      /* < Interrupt controller clock enable */
 190 #define CKEN_GPIO       39      /* < GPIO clock enable */
 191 #define CKEN_1WIRE      40      /* < 1-wire clock enable */
 192 #define CKEN_HSIO2      41      /* < HSIO2 clock enable */
 193 #define CKEN_MINI_IM    48      /* < Mini-IM */
 194 #define CKEN_MINI_LCD   49      /* < Mini LCD */
 195
 196 #if defined(CONFIG_CPU_PXA310)
 197 #define CKEN_MMC3       5       /* < MMC3 Clock Enable */
 198 #define CKEN_MVED       43      /* < MVED clock enable */
 199 #endif
 200
 201 /* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
 202 #define PXA300_CKEN_GRAPHICS    42      /* Graphics controller clock enable */
 203 #define PXA320_CKEN_GRAPHICS    7       /* Graphics controller clock enable */
 204
 205 #endif /* __ASM_ARCH_PXA3XX_REGS_H */