arch/arm/mach-pxa/irq.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/irq.c
   3  *
   4  *  Generic PXA IRQ handling
   5  *
   6  *  Author:     Nicolas Pitre
   7  *  Created:    Jun 15, 2001
   8  *  Copyright:  MontaVista Software Inc.
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License version 2 as
  12  *  published by the Free Software Foundation.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/syscore_ops.h>
  18 #include <linux/io.h>
  19 #include <linux/irq.h>
  20
  21 #include <asm/exception.h>
  22
  23 #include <mach/hardware.h>
  24 #include <mach/irqs.h>
  25
  26 #include "generic.h"
  27
  28 #define IRQ_BASE                io_p2v(0x40d00000)
  29
  30 #define ICIP                    (0x000)
  31 #define ICMR                    (0x004)
  32 #define ICLR                    (0x008)
  33 #define ICFR                    (0x00c)
  34 #define ICPR                    (0x010)
  35 #define ICCR                    (0x014)
  36 #define ICHP                    (0x018)
  37 #define IPR(i)                  (((i) < 32) ? (0x01c + ((i) << 2)) :            \
  38                                 ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) :      \
  39                                       (0x144 + (((i) - 64) << 2)))
  40 #define ICHP_VAL_IRQ            (1 << 31)
  41 #define ICHP_IRQ(i)             (((i) >> 16) & 0x7fff)
  42 #define IPR_VALID               (1 << 31)
  43 #define IRQ_BIT(n)              (((n) - PXA_IRQ(0)) & 0x1f)
  44
  45 #define MAX_INTERNAL_IRQS       128
  46
  47 /*
  48  * This is for peripheral IRQs internal to the PXA chip.
  49  */
  50
  51 static int pxa_internal_irq_nr;
  52
  53 static inline int cpu_has_ipr(void)
  54 {
  55         return !cpu_is_pxa25x();
  56 }
  57
  58 static inline void __iomem *irq_base(int i)
  59 {
  60         static unsigned long phys_base[] = {
  61                 0x40d00000,
  62                 0x40d0009c,
  63                 0x40d00130,
  64         };
  65
  66         return io_p2v(phys_base[i]);
  67 }
  68
  69 void pxa_mask_irq(struct irq_data *d)
  70 {
  71         void __iomem *base = irq_data_get_irq_chip_data(d);
  72         uint32_t icmr = __raw_readl(base + ICMR);
  73
  74         icmr &= ~(1 << IRQ_BIT(d->irq));
  75         __raw_writel(icmr, base + ICMR);
  76 }
  77
  78 void pxa_unmask_irq(struct irq_data *d)
  79 {
  80         void __iomem *base = irq_data_get_irq_chip_data(d);
  81         uint32_t icmr = __raw_readl(base + ICMR);
  82
  83         icmr |= 1 << IRQ_BIT(d->irq);
  84         __raw_writel(icmr, base + ICMR);
  85 }
  86
  87 static struct irq_chip pxa_internal_irq_chip = {
  88         .name           = "SC",
  89         .irq_ack        = pxa_mask_irq,
  90         .irq_mask       = pxa_mask_irq,
  91         .irq_unmask     = pxa_unmask_irq,
  92 };
  93
  94 asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
  95 {
  96         uint32_t icip, icmr, mask;
  97
  98         do {
  99                 icip = __raw_readl(IRQ_BASE + ICIP);
 100                 icmr = __raw_readl(IRQ_BASE + ICMR);
 101                 mask = icip & icmr;
 102
 103                 if (mask == 0)
 104                         break;
 105
 106                 handle_IRQ(PXA_IRQ(fls(mask) - 1), regs);
 107         } while (1);
 108 }
 109
 110 asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
 111 {
 112         uint32_t ichp;
 113
 114         do {
 115                 __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp));
 116
 117                 if ((ichp & ICHP_VAL_IRQ) == 0)
 118                         break;
 119
 120                 handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs);
 121         } while (1);
 122 }
 123
 124 void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
 125 {
 126         int irq, i, n;
 127
 128         BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
 129
 130         pxa_internal_irq_nr = irq_nr;
 131
 132         for (n = 0; n < irq_nr; n += 32) {
 133                 void __iomem *base = irq_base(n >> 5);
 134
 135                 __raw_writel(0, base + ICMR);   /* disable all IRQs */
 136                 __raw_writel(0, base + ICLR);   /* all IRQs are IRQ, not FIQ */
 137                 for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
 138                         /* initialize interrupt priority */
 139                         if (cpu_has_ipr())
 140                                 __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
 141
 142                         irq = PXA_IRQ(i);
 143                         irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
 144                                                  handle_level_irq);
 145                         irq_set_chip_data(irq, base);
 146                         set_irq_flags(irq, IRQF_VALID);
 147                 }
 148         }
 149
 150         /* only unmasked interrupts kick us out of idle */
 151         __raw_writel(1, irq_base(0) + ICCR);
 152
 153         pxa_internal_irq_chip.irq_set_wake = fn;
 154 }
 155
 156 #ifdef CONFIG_PM
 157 static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
 158 static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
 159
 160 static int pxa_irq_suspend(void)
 161 {
 162         int i;
 163
 164         for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
 165                 void __iomem *base = irq_base(i);
 166
 167                 saved_icmr[i] = __raw_readl(base + ICMR);
 168                 __raw_writel(0, base + ICMR);
 169         }
 170
 171         if (cpu_has_ipr()) {
 172                 for (i = 0; i < pxa_internal_irq_nr; i++)
 173                         saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i));
 174         }
 175
 176         return 0;
 177 }
 178
 179 static void pxa_irq_resume(void)
 180 {
 181         int i;
 182
 183         for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
 184                 void __iomem *base = irq_base(i);
 185
 186                 __raw_writel(saved_icmr[i], base + ICMR);
 187                 __raw_writel(0, base + ICLR);
 188         }
 189
 190         if (cpu_has_ipr())
 191                 for (i = 0; i < pxa_internal_irq_nr; i++)
 192                         __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i));
 193
 194         __raw_writel(1, IRQ_BASE + ICCR);
 195 }
 196 #else
 197 #define pxa_irq_suspend         NULL
 198 #define pxa_irq_resume          NULL
 199 #endif
 200
 201 struct syscore_ops pxa_irq_syscore_ops = {
 202         .suspend        = pxa_irq_suspend,
 203         .resume         = pxa_irq_resume,
 204 };