arch/arm/mach-pxa/irq.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/irq.c
   3  *
   4  *  Generic PXA IRQ handling
   5  *
   6  *  Author:     Nicolas Pitre
   7  *  Created:    Jun 15, 2001
   8  *  Copyright:  MontaVista Software Inc.
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License version 2 as
  12  *  published by the Free Software Foundation.
  13  */
  14 #include <linux/gpio.h>
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/io.h>
  20 #include <linux/irq.h>
  21
  22 #include <mach/hardware.h>
  23 #include <mach/irqs.h>
  24
  25 #include "generic.h"
  26
  27 #define IRQ_BASE                (void __iomem *)io_p2v(0x40d00000)
  28
  29 #define ICIP                    (0x000)
  30 #define ICMR                    (0x004)
  31 #define ICLR                    (0x008)
  32 #define ICFR                    (0x00c)
  33 #define ICPR                    (0x010)
  34 #define ICCR                    (0x014)
  35 #define ICHP                    (0x018)
  36 #define IPR(i)                  (((i) < 32) ? (0x01c + ((i) << 2)) :            \
  37                                 ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) :      \
  38                                       (0x144 + (((i) - 64) << 2)))
  39 #define ICHP_VAL_IRQ            (1 << 31)
  40 #define ICHP_IRQ(i)             (((i) >> 16) & 0x7fff)
  41 #define IPR_VALID               (1 << 31)
  42 #define IRQ_BIT(n)              (((n) - PXA_IRQ(0)) & 0x1f)
  43
  44 #define MAX_INTERNAL_IRQS       128
  45
  46 /*
  47  * This is for peripheral IRQs internal to the PXA chip.
  48  */
  49
  50 static int pxa_internal_irq_nr;
  51
  52 static inline int cpu_has_ipr(void)
  53 {
  54         return !cpu_is_pxa25x();
  55 }
  56
  57 static inline void __iomem *irq_base(int i)
  58 {
  59         static unsigned long phys_base[] = {
  60                 0x40d00000,
  61                 0x40d0009c,
  62                 0x40d00130,
  63         };
  64
  65         return (void __iomem *)io_p2v(phys_base[i]);
  66 }
  67
  68 void pxa_mask_irq(struct irq_data *d)
  69 {
  70         void __iomem *base = irq_data_get_irq_chip_data(d);
  71         uint32_t icmr = __raw_readl(base + ICMR);
  72
  73         icmr &= ~(1 << IRQ_BIT(d->irq));
  74         __raw_writel(icmr, base + ICMR);
  75 }
  76
  77 void pxa_unmask_irq(struct irq_data *d)
  78 {
  79         void __iomem *base = irq_data_get_irq_chip_data(d);
  80         uint32_t icmr = __raw_readl(base + ICMR);
  81
  82         icmr |= 1 << IRQ_BIT(d->irq);
  83         __raw_writel(icmr, base + ICMR);
  84 }
  85
  86 static struct irq_chip pxa_internal_irq_chip = {
  87         .name           = "SC",
  88         .irq_ack        = pxa_mask_irq,
  89         .irq_mask       = pxa_mask_irq,
  90         .irq_unmask     = pxa_unmask_irq,
  91 };
  92
  93 /*
  94  * GPIO IRQs for GPIO 0 and 1
  95  */
  96 static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type)
  97 {
  98         int gpio = d->irq - IRQ_GPIO0;
  99
 100         if (__gpio_is_occupied(gpio)) {
 101                 pr_err("%s failed: GPIO is configured\n", __func__);
 102                 return -EINVAL;
 103         }
 104
 105         if (type & IRQ_TYPE_EDGE_RISING)
 106                 GRER0 |= GPIO_bit(gpio);
 107         else
 108                 GRER0 &= ~GPIO_bit(gpio);
 109
 110         if (type & IRQ_TYPE_EDGE_FALLING)
 111                 GFER0 |= GPIO_bit(gpio);
 112         else
 113                 GFER0 &= ~GPIO_bit(gpio);
 114
 115         return 0;
 116 }
 117
 118 static void pxa_ack_low_gpio(struct irq_data *d)
 119 {
 120         GEDR0 = (1 << (d->irq - IRQ_GPIO0));
 121 }
 122
 123 static struct irq_chip pxa_low_gpio_chip = {
 124         .name           = "GPIO-l",
 125         .irq_ack        = pxa_ack_low_gpio,
 126         .irq_mask       = pxa_mask_irq,
 127         .irq_unmask     = pxa_unmask_irq,
 128         .irq_set_type   = pxa_set_low_gpio_type,
 129 };
 130
 131 asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
 132 {
 133         uint32_t icip, icmr, mask;
 134
 135         do {
 136                 icip = __raw_readl(IRQ_BASE + ICIP);
 137                 icmr = __raw_readl(IRQ_BASE + ICMR);
 138                 mask = icip & icmr;
 139
 140                 if (mask == 0)
 141                         break;
 142
 143                 handle_IRQ(PXA_IRQ(fls(mask) - 1), regs);
 144         } while (1);
 145 }
 146
 147 asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
 148 {
 149         uint32_t ichp;
 150
 151         do {
 152                 __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp));
 153
 154                 if ((ichp & ICHP_VAL_IRQ) == 0)
 155                         break;
 156
 157                 handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs);
 158         } while (1);
 159 }
 160
 161 static void __init pxa_init_low_gpio_irq(set_wake_t fn)
 162 {
 163         int irq;
 164
 165         /* clear edge detection on GPIO 0 and 1 */
 166         GFER0 &= ~0x3;
 167         GRER0 &= ~0x3;
 168         GEDR0 = 0x3;
 169
 170         for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
 171                 irq_set_chip_and_handler(irq, &pxa_low_gpio_chip,
 172                                          handle_edge_irq);
 173                 irq_set_chip_data(irq, irq_base(0));
 174                 set_irq_flags(irq, IRQF_VALID);
 175         }
 176
 177         pxa_low_gpio_chip.irq_set_wake = fn;
 178 }
 179
 180 void __init pxa_init_irq(int irq_nr, set_wake_t fn)
 181 {
 182         int irq, i, n;
 183
 184         BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
 185
 186         pxa_internal_irq_nr = irq_nr;
 187
 188         for (n = 0; n < irq_nr; n += 32) {
 189                 void __iomem *base = irq_base(n >> 5);
 190
 191                 __raw_writel(0, base + ICMR);   /* disable all IRQs */
 192                 __raw_writel(0, base + ICLR);   /* all IRQs are IRQ, not FIQ */
 193                 for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
 194                         /* initialize interrupt priority */
 195                         if (cpu_has_ipr())
 196                                 __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
 197
 198                         irq = PXA_IRQ(i);
 199                         irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
 200                                                  handle_level_irq);
 201                         irq_set_chip_data(irq, base);
 202                         set_irq_flags(irq, IRQF_VALID);
 203                 }
 204         }
 205
 206         /* only unmasked interrupts kick us out of idle */
 207         __raw_writel(1, irq_base(0) + ICCR);
 208
 209         pxa_internal_irq_chip.irq_set_wake = fn;
 210         pxa_init_low_gpio_irq(fn);
 211 }
 212
 213 #ifdef CONFIG_PM
 214 static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
 215 static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
 216
 217 static int pxa_irq_suspend(void)
 218 {
 219         int i;
 220
 221         for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
 222                 void __iomem *base = irq_base(i);
 223
 224                 saved_icmr[i] = __raw_readl(base + ICMR);
 225                 __raw_writel(0, base + ICMR);
 226         }
 227
 228         if (cpu_has_ipr()) {
 229                 for (i = 0; i < pxa_internal_irq_nr; i++)
 230                         saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i));
 231         }
 232
 233         return 0;
 234 }
 235
 236 static void pxa_irq_resume(void)
 237 {
 238         int i;
 239
 240         for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
 241                 void __iomem *base = irq_base(i);
 242
 243                 __raw_writel(saved_icmr[i], base + ICMR);
 244                 __raw_writel(0, base + ICLR);
 245         }
 246
 247         if (cpu_has_ipr())
 248                 for (i = 0; i < pxa_internal_irq_nr; i++)
 249                         __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i));
 250
 251         __raw_writel(1, IRQ_BASE + ICCR);
 252 }
 253 #else
 254 #define pxa_irq_suspend         NULL
 255 #define pxa_irq_resume          NULL
 256 #endif
 257
 258 struct syscore_ops pxa_irq_syscore_ops = {
 259         .suspend        = pxa_irq_suspend,
 260         .resume         = pxa_irq_resume,
 261 };