arch/arm/mach-pxa/pxa25x.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/pxa25x.c
   3  *
   4  *  Author:     Nicolas Pitre
   5  *  Created:    Jun 15, 2001
   6  *  Copyright:  MontaVista Software Inc.
   7  *
   8  * Code specific to PXA21x/25x/26x variants.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * Since this file should be linked before any other machine specific file,
  15  * the __initcall() here will be executed first.  This serves as default
  16  * initialization stuff for PXA machines which can be overridden later if
  17  * need be.
  18  */
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/suspend.h>
  24 #include <linux/sysdev.h>
  25
  26 #include <mach/hardware.h>
  27 #include <mach/irqs.h>
  28 #include <mach/pxa25x.h>
  29 #include <mach/reset.h>
  30 #include <mach/pm.h>
  31 #include <mach/dma.h>
  32
  33 #include "generic.h"
  34 #include "devices.h"
  35 #include "clock.h"
  36
  37 /*
  38  * Various clock factors driven by the CCCR register.
  39  */
  40
  41 /* Crystal Frequency to Memory Frequency Multiplier (L) */
  42 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
  43
  44 /* Memory Frequency to Run Mode Frequency Multiplier (M) */
  45 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
  46
  47 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
  48 /* Note: we store the value N * 2 here. */
  49 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
  50
  51 /* Crystal clock */
  52 #define BASE_CLK        3686400
  53
  54 /*
  55  * Get the clock frequency as reflected by CCCR and the turbo flag.
  56  * We assume these values have been applied via a fcs.
  57  * If info is not 0 we also display the current settings.
  58  */
  59 unsigned int pxa25x_get_clk_frequency_khz(int info)
  60 {
  61         unsigned long cccr, turbo;
  62         unsigned int l, L, m, M, n2, N;
  63
  64         cccr = CCCR;
  65         asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
  66
  67         l  =  L_clk_mult[(cccr >> 0) & 0x1f];
  68         m  =  M_clk_mult[(cccr >> 5) & 0x03];
  69         n2 = N2_clk_mult[(cccr >> 7) & 0x07];
  70
  71         L = l * BASE_CLK;
  72         M = m * L;
  73         N = n2 * M / 2;
  74
  75         if(info)
  76         {
  77                 L += 5000;
  78                 printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
  79                         L / 1000000, (L % 1000000) / 10000, l );
  80                 M += 5000;
  81                 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
  82                         M / 1000000, (M % 1000000) / 10000, m );
  83                 N += 5000;
  84                 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
  85                         N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
  86                         (turbo & 1) ? "" : "in" );
  87         }
  88
  89         return (turbo & 1) ? (N/1000) : (M/1000);
  90 }
  91
  92 /*
  93  * Return the current memory clock frequency in units of 10kHz
  94  */
  95 unsigned int pxa25x_get_memclk_frequency_10khz(void)
  96 {
  97         return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
  98 }
  99
 100 static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
 101 {
 102         return pxa25x_get_memclk_frequency_10khz() * 10000;
 103 }
 104
 105 static const struct clkops clk_pxa25x_lcd_ops = {
 106         .enable         = clk_cken_enable,
 107         .disable        = clk_cken_disable,
 108         .getrate        = clk_pxa25x_lcd_getrate,
 109 };
 110
 111 static unsigned long gpio12_config_32k[] = {
 112         GPIO12_32KHz,
 113 };
 114
 115 static unsigned long gpio12_config_gpio[] = {
 116         GPIO12_GPIO,
 117 };
 118
 119 static void clk_gpio12_enable(struct clk *clk)
 120 {
 121         pxa2xx_mfp_config(gpio12_config_32k, 1);
 122 }
 123
 124 static void clk_gpio12_disable(struct clk *clk)
 125 {
 126         pxa2xx_mfp_config(gpio12_config_gpio, 1);
 127 }
 128
 129 static const struct clkops clk_pxa25x_gpio12_ops = {
 130         .enable         = clk_gpio12_enable,
 131         .disable        = clk_gpio12_disable,
 132 };
 133
 134 static unsigned long gpio11_config_3m6[] = {
 135         GPIO11_3_6MHz,
 136 };
 137
 138 static unsigned long gpio11_config_gpio[] = {
 139         GPIO11_GPIO,
 140 };
 141
 142 static void clk_gpio11_enable(struct clk *clk)
 143 {
 144         pxa2xx_mfp_config(gpio11_config_3m6, 1);
 145 }
 146
 147 static void clk_gpio11_disable(struct clk *clk)
 148 {
 149         pxa2xx_mfp_config(gpio11_config_gpio, 1);
 150 }
 151
 152 static const struct clkops clk_pxa25x_gpio11_ops = {
 153         .enable         = clk_gpio11_enable,
 154         .disable        = clk_gpio11_disable,
 155 };
 156
 157 /*
 158  * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
 159  * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
 160  * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
 161  */
 162 static DEFINE_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
 163
 164 static struct clk_lookup pxa25x_hwuart_clkreg =
 165         INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
 166
 167 /*
 168  * PXA 2xx clock declarations.
 169  */
 170 static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
 171 static DEFINE_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
 172 static DEFINE_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
 173 static DEFINE_CKEN(pxa25x_stuart, STUART, 14745600, 1);
 174 static DEFINE_CKEN(pxa25x_usb, USB, 47923000, 5);
 175 static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
 176 static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
 177 static DEFINE_CKEN(pxa25x_mmc, MMC, 19169000, 0);
 178 static DEFINE_CKEN(pxa25x_i2c, I2C, 31949000, 0);
 179 static DEFINE_CKEN(pxa25x_ssp, SSP, 3686400, 0);
 180 static DEFINE_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
 181 static DEFINE_CKEN(pxa25x_assp, ASSP, 3686400, 0);
 182 static DEFINE_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
 183 static DEFINE_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
 184 static DEFINE_CKEN(pxa25x_ac97, AC97, 24576000, 0);
 185 static DEFINE_CKEN(pxa25x_i2s, I2S, 14745600, 0);
 186 static DEFINE_CKEN(pxa25x_ficp, FICP, 47923000, 0);
 187
 188 static struct clk_lookup pxa25x_clkregs[] = {
 189         INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
 190         INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL),
 191         INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL),
 192         INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL),
 193         INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL),
 194         INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL),
 195         INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL),
 196         INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL),
 197         INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL),
 198         INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL),
 199         INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL),
 200         INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL),
 201         INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL),
 202         INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"),
 203         INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"),
 204         INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
 205         INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
 206         INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
 207 };
 208
 209 #ifdef CONFIG_PM
 210
 211 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
 212 #define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
 213
 214 /*
 215  * List of global PXA peripheral registers to preserve.
 216  * More ones like CP and general purpose register values are preserved
 217  * with the stack pointer in sleep.S.
 218  */
 219 enum {
 220         SLEEP_SAVE_PSTR,
 221         SLEEP_SAVE_CKEN,
 222         SLEEP_SAVE_COUNT
 223 };
 224
 225
 226 static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
 227 {
 228         SAVE(CKEN);
 229         SAVE(PSTR);
 230 }
 231
 232 static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
 233 {
 234         RESTORE(CKEN);
 235         RESTORE(PSTR);
 236 }
 237
 238 static void pxa25x_cpu_pm_enter(suspend_state_t state)
 239 {
 240         /* Clear reset status */
 241         RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
 242
 243         switch (state) {
 244         case PM_SUSPEND_MEM:
 245                 pxa25x_cpu_suspend(PWRMODE_SLEEP);
 246                 break;
 247         }
 248 }
 249
 250 static int pxa25x_cpu_pm_prepare(void)
 251 {
 252         /* set resume return address */
 253         PSPR = virt_to_phys(pxa_cpu_resume);
 254         return 0;
 255 }
 256
 257 static void pxa25x_cpu_pm_finish(void)
 258 {
 259         /* ensure not to come back here if it wasn't intended */
 260         PSPR = 0;
 261 }
 262
 263 static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
 264         .save_count     = SLEEP_SAVE_COUNT,
 265         .valid          = suspend_valid_only_mem,
 266         .save           = pxa25x_cpu_pm_save,
 267         .restore        = pxa25x_cpu_pm_restore,
 268         .enter          = pxa25x_cpu_pm_enter,
 269         .prepare        = pxa25x_cpu_pm_prepare,
 270         .finish         = pxa25x_cpu_pm_finish,
 271 };
 272
 273 static void __init pxa25x_init_pm(void)
 274 {
 275         pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
 276 }
 277 #else
 278 static inline void pxa25x_init_pm(void) {}
 279 #endif
 280
 281 /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
 282  */
 283
 284 static int pxa25x_set_wake(unsigned int irq, unsigned int on)
 285 {
 286         int gpio = IRQ_TO_GPIO(irq);
 287         uint32_t mask = 0;
 288
 289         if (gpio >= 0 && gpio < 85)
 290                 return gpio_set_wake(gpio, on);
 291
 292         if (irq == IRQ_RTCAlrm) {
 293                 mask = PWER_RTC;
 294                 goto set_pwer;
 295         }
 296
 297         return -EINVAL;
 298
 299 set_pwer:
 300         if (on)
 301                 PWER |= mask;
 302         else
 303                 PWER &=~mask;
 304
 305         return 0;
 306 }
 307
 308 void __init pxa25x_init_irq(void)
 309 {
 310         pxa_init_irq(32, pxa25x_set_wake);
 311         pxa_init_gpio(85, pxa25x_set_wake);
 312 }
 313
 314 #ifdef CONFIG_CPU_PXA26x
 315 void __init pxa26x_init_irq(void)
 316 {
 317         pxa_init_irq(32, pxa25x_set_wake);
 318         pxa_init_gpio(90, pxa25x_set_wake);
 319 }
 320 #endif
 321
 322 static struct platform_device *pxa25x_devices[] __initdata = {
 323         &pxa25x_device_udc,
 324         &pxa_device_ffuart,
 325         &pxa_device_btuart,
 326         &pxa_device_stuart,
 327         &pxa_device_i2s,
 328         &sa1100_device_rtc,
 329         &pxa25x_device_ssp,
 330         &pxa25x_device_nssp,
 331         &pxa25x_device_assp,
 332         &pxa25x_device_pwm0,
 333         &pxa25x_device_pwm1,
 334 };
 335
 336 static struct sys_device pxa25x_sysdev[] = {
 337         {
 338                 .cls    = &pxa_irq_sysclass,
 339         }, {
 340                 .cls    = &pxa2xx_mfp_sysclass,
 341         }, {
 342                 .cls    = &pxa_gpio_sysclass,
 343         },
 344 };
 345
 346 static int __init pxa25x_init(void)
 347 {
 348         int i, ret = 0;
 349
 350         if (cpu_is_pxa25x()) {
 351
 352                 reset_status = RCSR;
 353
 354                 clks_register(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
 355
 356                 if ((ret = pxa_init_dma(16)))
 357                         return ret;
 358
 359                 pxa25x_init_pm();
 360
 361                 for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) {
 362                         ret = sysdev_register(&pxa25x_sysdev[i]);
 363                         if (ret)
 364                                 pr_err("failed to register sysdev[%d]\n", i);
 365                 }
 366
 367                 ret = platform_add_devices(pxa25x_devices,
 368                                            ARRAY_SIZE(pxa25x_devices));
 369                 if (ret)
 370                         return ret;
 371         }
 372
 373         /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
 374         if (cpu_is_pxa255()) {
 375                 clks_register(&pxa25x_hwuart_clkreg, 1);
 376                 ret = platform_device_register(&pxa_device_hwuart);
 377         }
 378
 379         return ret;
 380 }
 381
 382 postcore_initcall(pxa25x_init);