2 * linux/arch/arm/mach-pxa/pxa25x.c
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
8 * Code specific to PXA21x/25x/26x variants.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * Since this file should be linked before any other machine specific file,
15 * the __initcall() here will be executed first. This serves as default
16 * initialization stuff for PXA machines which can be overridden later if
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/suspend.h>
25 #include <asm/hardware.h>
26 #include <asm/arch/irqs.h>
27 #include <asm/arch/pxa-regs.h>
28 #include <asm/arch/pm.h>
29 #include <asm/arch/dma.h>
36 * Various clock factors driven by the CCCR register.
39 /* Crystal Frequency to Memory Frequency Multiplier (L) */
40 static unsigned char L_clk_mult
[32] = { 0, 27, 32, 36, 40, 45, 0, };
42 /* Memory Frequency to Run Mode Frequency Multiplier (M) */
43 static unsigned char M_clk_mult
[4] = { 0, 1, 2, 4 };
45 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
46 /* Note: we store the value N * 2 here. */
47 static unsigned char N2_clk_mult
[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
50 #define BASE_CLK 3686400
53 * Get the clock frequency as reflected by CCCR and the turbo flag.
54 * We assume these values have been applied via a fcs.
55 * If info is not 0 we also display the current settings.
57 unsigned int pxa25x_get_clk_frequency_khz(int info
)
59 unsigned long cccr
, turbo
;
60 unsigned int l
, L
, m
, M
, n2
, N
;
63 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo
) );
65 l
= L_clk_mult
[(cccr
>> 0) & 0x1f];
66 m
= M_clk_mult
[(cccr
>> 5) & 0x03];
67 n2
= N2_clk_mult
[(cccr
>> 7) & 0x07];
76 printk( KERN_INFO
"Memory clock: %d.%02dMHz (*%d)\n",
77 L
/ 1000000, (L
% 1000000) / 10000, l
);
79 printk( KERN_INFO
"Run Mode clock: %d.%02dMHz (*%d)\n",
80 M
/ 1000000, (M
% 1000000) / 10000, m
);
82 printk( KERN_INFO
"Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
83 N
/ 1000000, (N
% 1000000) / 10000, n2
/ 2, (n2
% 2) * 5,
84 (turbo
& 1) ? "" : "in" );
87 return (turbo
& 1) ? (N
/1000) : (M
/1000);
91 * Return the current memory clock frequency in units of 10kHz
93 unsigned int pxa25x_get_memclk_frequency_10khz(void)
95 return L_clk_mult
[(CCCR
>> 0) & 0x1f] * BASE_CLK
/ 10000;
98 static unsigned long clk_pxa25x_lcd_getrate(struct clk
*clk
)
100 return pxa25x_get_memclk_frequency_10khz() * 10000;
103 static const struct clkops clk_pxa25x_lcd_ops
= {
104 .enable
= clk_cken_enable
,
105 .disable
= clk_cken_disable
,
106 .getrate
= clk_pxa25x_lcd_getrate
,
110 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
111 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
112 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
114 static struct clk pxa25x_hwuart_clk
=
115 INIT_CKEN("UARTCLK", HWUART
, 14745600, 1, &pxa_device_hwuart
.dev
)
118 static struct clk pxa25x_clks
[] = {
119 INIT_CK("LCDCLK", LCD
, &clk_pxa25x_lcd_ops
, &pxa_device_fb
.dev
),
120 INIT_CKEN("UARTCLK", FFUART
, 14745600, 1, &pxa_device_ffuart
.dev
),
121 INIT_CKEN("UARTCLK", BTUART
, 14745600, 1, &pxa_device_btuart
.dev
),
122 INIT_CKEN("UARTCLK", STUART
, 14745600, 1, NULL
),
123 INIT_CKEN("UDCCLK", USB
, 47923000, 5, &pxa_device_udc
.dev
),
124 INIT_CKEN("MMCCLK", MMC
, 19169000, 0, &pxa_device_mci
.dev
),
125 INIT_CKEN("I2CCLK", I2C
, 31949000, 0, &pxa_device_i2c
.dev
),
127 INIT_CKEN("SSPCLK", SSP
, 3686400, 0, &pxa25x_device_ssp
.dev
),
128 INIT_CKEN("SSPCLK", NSSP
, 3686400, 0, &pxa25x_device_nssp
.dev
),
129 INIT_CKEN("SSPCLK", ASSP
, 3686400, 0, &pxa25x_device_assp
.dev
),
132 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
133 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
134 INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL),
136 INIT_CKEN("FICPCLK", FICP
, 47923000, 0, NULL
),
141 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
142 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
144 #define RESTORE_GPLEVEL(n) do { \
145 GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
146 GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
150 * List of global PXA peripheral registers to preserve.
151 * More ones like CP and general purpose register values are preserved
152 * with the stack pointer in sleep.S.
154 enum { SLEEP_SAVE_START
= 0,
156 SLEEP_SAVE_GPLR0
, SLEEP_SAVE_GPLR1
, SLEEP_SAVE_GPLR2
,
157 SLEEP_SAVE_GPDR0
, SLEEP_SAVE_GPDR1
, SLEEP_SAVE_GPDR2
,
158 SLEEP_SAVE_GRER0
, SLEEP_SAVE_GRER1
, SLEEP_SAVE_GRER2
,
159 SLEEP_SAVE_GFER0
, SLEEP_SAVE_GFER1
, SLEEP_SAVE_GFER2
,
160 SLEEP_SAVE_PGSR0
, SLEEP_SAVE_PGSR1
, SLEEP_SAVE_PGSR2
,
162 SLEEP_SAVE_GAFR0_L
, SLEEP_SAVE_GAFR0_U
,
163 SLEEP_SAVE_GAFR1_L
, SLEEP_SAVE_GAFR1_U
,
164 SLEEP_SAVE_GAFR2_L
, SLEEP_SAVE_GAFR2_U
,
175 static void pxa25x_cpu_pm_save(unsigned long *sleep_save
)
177 SAVE(GPLR0
); SAVE(GPLR1
); SAVE(GPLR2
);
178 SAVE(GPDR0
); SAVE(GPDR1
); SAVE(GPDR2
);
179 SAVE(GRER0
); SAVE(GRER1
); SAVE(GRER2
);
180 SAVE(GFER0
); SAVE(GFER1
); SAVE(GFER2
);
181 SAVE(PGSR0
); SAVE(PGSR1
); SAVE(PGSR2
);
183 SAVE(GAFR0_L
); SAVE(GAFR0_U
);
184 SAVE(GAFR1_L
); SAVE(GAFR1_U
);
185 SAVE(GAFR2_L
); SAVE(GAFR2_U
);
187 SAVE(ICMR
); ICMR
= 0;
191 /* Clear GPIO transition detect bits */
192 GEDR0
= GEDR0
; GEDR1
= GEDR1
; GEDR2
= GEDR2
;
195 static void pxa25x_cpu_pm_restore(unsigned long *sleep_save
)
197 /* ensure not to come back here if it wasn't intended */
200 /* restore registers */
201 RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
202 RESTORE(GPDR0
); RESTORE(GPDR1
); RESTORE(GPDR2
);
203 RESTORE(GAFR0_L
); RESTORE(GAFR0_U
);
204 RESTORE(GAFR1_L
); RESTORE(GAFR1_U
);
205 RESTORE(GAFR2_L
); RESTORE(GAFR2_U
);
206 RESTORE(GRER0
); RESTORE(GRER1
); RESTORE(GRER2
);
207 RESTORE(GFER0
); RESTORE(GFER1
); RESTORE(GFER2
);
208 RESTORE(PGSR0
); RESTORE(PGSR1
); RESTORE(PGSR2
);
210 PSSR
= PSSR_RDH
| PSSR_PH
;
220 static void pxa25x_cpu_pm_enter(suspend_state_t state
)
224 /* set resume return address */
225 PSPR
= virt_to_phys(pxa_cpu_resume
);
226 pxa25x_cpu_suspend(PWRMODE_SLEEP
);
231 static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns
= {
232 .save_size
= SLEEP_SAVE_SIZE
,
233 .valid
= suspend_valid_only_mem
,
234 .save
= pxa25x_cpu_pm_save
,
235 .restore
= pxa25x_cpu_pm_restore
,
236 .enter
= pxa25x_cpu_pm_enter
,
239 static void __init
pxa25x_init_pm(void)
241 pxa_cpu_pm_fns
= &pxa25x_cpu_pm_fns
;
244 static inline void pxa25x_init_pm(void) {}
247 /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
250 static int pxa25x_set_wake(unsigned int irq
, unsigned int on
)
252 int gpio
= IRQ_TO_GPIO(irq
);
253 uint32_t gpio_bit
, mask
= 0;
255 if (gpio
>= 0 && gpio
<= 15) {
256 gpio_bit
= GPIO_bit(gpio
);
259 if (GRER(gpio
) | gpio_bit
)
264 if (GFER(gpio
) | gpio_bit
)
272 if (irq
== IRQ_RTCAlrm
) {
288 void __init
pxa25x_init_irq(void)
291 pxa_init_irq_gpio(85);
292 pxa_init_irq_set_wake(pxa25x_set_wake
);
295 static struct platform_device
*pxa25x_devices
[] __initdata
= {
307 static int __init
pxa25x_init(void)
311 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
313 clks_register(&pxa25x_hwuart_clk
, 1);
315 if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
316 clks_register(pxa25x_clks
, ARRAY_SIZE(pxa25x_clks
));
318 if ((ret
= pxa_init_dma(16)))
323 ret
= platform_add_devices(pxa25x_devices
,
324 ARRAY_SIZE(pxa25x_devices
));
326 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
328 ret
= platform_device_register(&pxa_device_hwuart
);
333 subsys_initcall(pxa25x_init
);