arch/arm/mach-pxa/pxa25x.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/pxa25x.c
   3  *
   4  *  Author:     Nicolas Pitre
   5  *  Created:    Jun 15, 2001
   6  *  Copyright:  MontaVista Software Inc.
   7  *
   8  * Code specific to PXA21x/25x/26x variants.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * Since this file should be linked before any other machine specific file,
  15  * the __initcall() here will be executed first.  This serves as default
  16  * initialization stuff for PXA machines which can be overridden later if
  17  * need be.
  18  */
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/suspend.h>
  24 #include <linux/sysdev.h>
  25
  26 #include <asm/hardware.h>
  27 #include <asm/arch/irqs.h>
  28 #include <asm/arch/pxa-regs.h>
  29 #include <asm/arch/pxa2xx-regs.h>
  30 #include <asm/arch/mfp-pxa25x.h>
  31 #include <asm/arch/pm.h>
  32 #include <asm/arch/dma.h>
  33
  34 #include "generic.h"
  35 #include "devices.h"
  36 #include "clock.h"
  37
  38 /*
  39  * Various clock factors driven by the CCCR register.
  40  */
  41
  42 /* Crystal Frequency to Memory Frequency Multiplier (L) */
  43 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
  44
  45 /* Memory Frequency to Run Mode Frequency Multiplier (M) */
  46 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
  47
  48 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
  49 /* Note: we store the value N * 2 here. */
  50 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
  51
  52 /* Crystal clock */
  53 #define BASE_CLK        3686400
  54
  55 /*
  56  * Get the clock frequency as reflected by CCCR and the turbo flag.
  57  * We assume these values have been applied via a fcs.
  58  * If info is not 0 we also display the current settings.
  59  */
  60 unsigned int pxa25x_get_clk_frequency_khz(int info)
  61 {
  62         unsigned long cccr, turbo;
  63         unsigned int l, L, m, M, n2, N;
  64
  65         cccr = CCCR;
  66         asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
  67
  68         l  =  L_clk_mult[(cccr >> 0) & 0x1f];
  69         m  =  M_clk_mult[(cccr >> 5) & 0x03];
  70         n2 = N2_clk_mult[(cccr >> 7) & 0x07];
  71
  72         L = l * BASE_CLK;
  73         M = m * L;
  74         N = n2 * M / 2;
  75
  76         if(info)
  77         {
  78                 L += 5000;
  79                 printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
  80                         L / 1000000, (L % 1000000) / 10000, l );
  81                 M += 5000;
  82                 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
  83                         M / 1000000, (M % 1000000) / 10000, m );
  84                 N += 5000;
  85                 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
  86                         N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
  87                         (turbo & 1) ? "" : "in" );
  88         }
  89
  90         return (turbo & 1) ? (N/1000) : (M/1000);
  91 }
  92
  93 /*
  94  * Return the current memory clock frequency in units of 10kHz
  95  */
  96 unsigned int pxa25x_get_memclk_frequency_10khz(void)
  97 {
  98         return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
  99 }
 100
 101 static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
 102 {
 103         return pxa25x_get_memclk_frequency_10khz() * 10000;
 104 }
 105
 106 static const struct clkops clk_pxa25x_lcd_ops = {
 107         .enable         = clk_cken_enable,
 108         .disable        = clk_cken_disable,
 109         .getrate        = clk_pxa25x_lcd_getrate,
 110 };
 111
 112 /*
 113  * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
 114  * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
 115  * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
 116  */
 117 static struct clk pxa25x_hwuart_clk =
 118         INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev)
 119 ;
 120
 121 /*
 122  * PXA 2xx clock declarations. Order is important (see aliases below)
 123  * Please be careful not to disrupt the ordering.
 124  */
 125 static struct clk pxa25x_clks[] = {
 126         INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
 127         INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
 128         INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
 129         INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
 130         INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa25x_device_udc.dev),
 131         INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
 132         INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
 133
 134         INIT_CKEN("SSPCLK",  SSP, 3686400, 0, &pxa25x_device_ssp.dev),
 135         INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
 136         INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),
 137         INIT_CKEN("PWMCLK", PWM0, 3686400, 0, &pxa25x_device_pwm0.dev),
 138         INIT_CKEN("PWMCLK", PWM1, 3686400, 0, &pxa25x_device_pwm1.dev),
 139
 140         INIT_CKEN("AC97CLK",     AC97,     24576000, 0, NULL),
 141
 142         /*
 143         INIT_CKEN("I2SCLK",  I2S,  14745600, 0, NULL),
 144         */
 145         INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
 146 };
 147
 148 static struct clk gpio7_clk = INIT_CKOTHER("GPIO7_CK", &pxa25x_clks[4], NULL);
 149
 150 #ifdef CONFIG_PM
 151
 152 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
 153 #define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
 154
 155 /*
 156  * List of global PXA peripheral registers to preserve.
 157  * More ones like CP and general purpose register values are preserved
 158  * with the stack pointer in sleep.S.
 159  */
 160 enum {  SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
 161
 162         SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
 163         SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
 164         SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
 165
 166         SLEEP_SAVE_PSTR,
 167
 168         SLEEP_SAVE_CKEN,
 169
 170         SLEEP_SAVE_COUNT
 171 };
 172
 173
 174 static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
 175 {
 176         SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
 177
 178         SAVE(GAFR0_L); SAVE(GAFR0_U);
 179         SAVE(GAFR1_L); SAVE(GAFR1_U);
 180         SAVE(GAFR2_L); SAVE(GAFR2_U);
 181
 182         SAVE(CKEN);
 183         SAVE(PSTR);
 184
 185         /* Clear GPIO transition detect bits */
 186         GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
 187 }
 188
 189 static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
 190 {
 191         /* ensure not to come back here if it wasn't intended */
 192         PSPR = 0;
 193
 194         /* restore registers */
 195         RESTORE(GAFR0_L); RESTORE(GAFR0_U);
 196         RESTORE(GAFR1_L); RESTORE(GAFR1_U);
 197         RESTORE(GAFR2_L); RESTORE(GAFR2_U);
 198         RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
 199
 200         PSSR = PSSR_RDH | PSSR_PH;
 201
 202         RESTORE(CKEN);
 203         RESTORE(PSTR);
 204 }
 205
 206 static void pxa25x_cpu_pm_enter(suspend_state_t state)
 207 {
 208         /* Clear reset status */
 209         RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
 210
 211         switch (state) {
 212         case PM_SUSPEND_MEM:
 213                 /* set resume return address */
 214                 PSPR = virt_to_phys(pxa_cpu_resume);
 215                 pxa25x_cpu_suspend(PWRMODE_SLEEP);
 216                 break;
 217         }
 218 }
 219
 220 static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
 221         .save_count     = SLEEP_SAVE_COUNT,
 222         .valid          = suspend_valid_only_mem,
 223         .save           = pxa25x_cpu_pm_save,
 224         .restore        = pxa25x_cpu_pm_restore,
 225         .enter          = pxa25x_cpu_pm_enter,
 226 };
 227
 228 static void __init pxa25x_init_pm(void)
 229 {
 230         pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
 231 }
 232 #else
 233 static inline void pxa25x_init_pm(void) {}
 234 #endif
 235
 236 /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
 237  */
 238
 239 static int pxa25x_set_wake(unsigned int irq, unsigned int on)
 240 {
 241         int gpio = IRQ_TO_GPIO(irq);
 242         uint32_t mask = 0;
 243
 244         if (gpio >= 0 && gpio < 85)
 245                 return gpio_set_wake(gpio, on);
 246
 247         if (irq == IRQ_RTCAlrm) {
 248                 mask = PWER_RTC;
 249                 goto set_pwer;
 250         }
 251
 252         return -EINVAL;
 253
 254 set_pwer:
 255         if (on)
 256                 PWER |= mask;
 257         else
 258                 PWER &=~mask;
 259
 260         return 0;
 261 }
 262
 263 void __init pxa25x_init_irq(void)
 264 {
 265         pxa_init_irq(32, pxa25x_set_wake);
 266         pxa_init_gpio(85, pxa25x_set_wake);
 267 }
 268
 269 static struct platform_device *pxa25x_devices[] __initdata = {
 270         &pxa25x_device_udc,
 271         &pxa_device_ffuart,
 272         &pxa_device_btuart,
 273         &pxa_device_stuart,
 274         &pxa_device_i2s,
 275         &pxa_device_rtc,
 276         &pxa25x_device_ssp,
 277         &pxa25x_device_nssp,
 278         &pxa25x_device_assp,
 279         &pxa25x_device_pwm0,
 280         &pxa25x_device_pwm1,
 281 };
 282
 283 static struct sys_device pxa25x_sysdev[] = {
 284         {
 285                 .cls    = &pxa_irq_sysclass,
 286         }, {
 287                 .cls    = &pxa_gpio_sysclass,
 288         },
 289 };
 290
 291 static int __init pxa25x_init(void)
 292 {
 293         int i, ret = 0;
 294
 295         /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
 296         if (cpu_is_pxa25x())
 297                 clks_register(&pxa25x_hwuart_clk, 1);
 298
 299         if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
 300                 clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));
 301
 302                 if ((ret = pxa_init_dma(16)))
 303                         return ret;
 304
 305                 pxa25x_init_pm();
 306
 307                 for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) {
 308                         ret = sysdev_register(&pxa25x_sysdev[i]);
 309                         if (ret)
 310                                 pr_err("failed to register sysdev[%d]\n", i);
 311                 }
 312
 313                 ret = platform_add_devices(pxa25x_devices,
 314                                            ARRAY_SIZE(pxa25x_devices));
 315                 if (ret)
 316                         return ret;
 317         }
 318
 319         /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
 320         if (cpu_is_pxa25x())
 321                 ret = platform_device_register(&pxa_device_hwuart);
 322
 323         clks_register(&gpio7_clk, 1);
 324
 325         return ret;
 326 }
 327
 328 postcore_initcall(pxa25x_init);