arch/arm/mach-pxa/pxa27x.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/pxa27x.c
   3  *
   4  *  Author:     Nicolas Pitre
   5  *  Created:    Nov 05, 2002
   6  *  Copyright:  MontaVista Software Inc.
   7  *
   8  * Code specific to PXA27x aka Bulverde.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/gpio.h>
  15 #include <linux/gpio-pxa.h>
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/suspend.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/syscore_ops.h>
  22 #include <linux/io.h>
  23 #include <linux/irq.h>
  24 #include <linux/i2c/pxa-i2c.h>
  25
  26 #include <asm/mach/map.h>
  27 #include <mach/hardware.h>
  28 #include <asm/irq.h>
  29 #include <asm/suspend.h>
  30 #include <mach/irqs.h>
  31 #include <mach/pxa27x.h>
  32 #include <mach/reset.h>
  33 #include <linux/platform_data/usb-ohci-pxa27x.h>
  34 #include <mach/pm.h>
  35 #include <mach/dma.h>
  36 #include <mach/smemc.h>
  37
  38 #include "generic.h"
  39 #include "devices.h"
  40 #include "clock.h"
  41
  42 void pxa27x_clear_otgph(void)
  43 {
  44         if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
  45                 PSSR |= PSSR_OTGPH;
  46 }
  47 EXPORT_SYMBOL(pxa27x_clear_otgph);
  48
  49 static unsigned long ac97_reset_config[] = {
  50         GPIO113_AC97_nRESET_GPIO_HIGH,
  51         GPIO113_AC97_nRESET,
  52         GPIO95_AC97_nRESET_GPIO_HIGH,
  53         GPIO95_AC97_nRESET,
  54 };
  55
  56 void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio)
  57 {
  58         /*
  59          * This helper function is used to work around a bug in the pxa27x's
  60          * ac97 controller during a warm reset.  The configuration of the
  61          * reset_gpio is changed as follows:
  62          * to_gpio == true: configured to generic output gpio and driven high
  63          * to_gpio == false: configured to ac97 controller alt fn AC97_nRESET
  64          */
  65
  66         if (reset_gpio == 113)
  67                 pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] :
  68                                   &ac97_reset_config[1], 1);
  69
  70         if (reset_gpio == 95)
  71                 pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] :
  72                                   &ac97_reset_config[3], 1);
  73 }
  74 EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);
  75
  76 /* Crystal clock: 13MHz */
  77 #define BASE_CLK        13000000
  78
  79 /*
  80  * Get the clock frequency as reflected by CCSR and the turbo flag.
  81  * We assume these values have been applied via a fcs.
  82  * If info is not 0 we also display the current settings.
  83  */
  84 unsigned int pxa27x_get_clk_frequency_khz(int info)
  85 {
  86         unsigned long ccsr, clkcfg;
  87         unsigned int l, L, m, M, n2, N, S;
  88         int cccr_a, t, ht, b;
  89
  90         ccsr = CCSR;
  91         cccr_a = CCCR & (1 << 25);
  92
  93         /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
  94         asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
  95         t  = clkcfg & (1 << 0);
  96         ht = clkcfg & (1 << 2);
  97         b  = clkcfg & (1 << 3);
  98
  99         l  = ccsr & 0x1f;
 100         n2 = (ccsr>>7) & 0xf;
 101         m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
 102
 103         L  = l * BASE_CLK;
 104         N  = (L * n2) / 2;
 105         M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
 106         S  = (b) ? L : (L/2);
 107
 108         if (info) {
 109                 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
 110                         L / 1000000, (L % 1000000) / 10000, l );
 111                 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
 112                         N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
 113                         (t) ? "" : "in" );
 114                 printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
 115                         M / 1000000, (M % 1000000) / 10000, m );
 116                 printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
 117                         S / 1000000, (S % 1000000) / 10000 );
 118         }
 119
 120         return (t) ? (N/1000) : (L/1000);
 121 }
 122
 123 /*
 124  * Return the current mem clock frequency as reflected by CCCR[A], B, and L
 125  */
 126 static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
 127 {
 128         unsigned long ccsr, clkcfg;
 129         unsigned int l, L, m, M;
 130         int cccr_a, b;
 131
 132         ccsr = CCSR;
 133         cccr_a = CCCR & (1 << 25);
 134
 135         /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
 136         asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
 137         b = clkcfg & (1 << 3);
 138
 139         l = ccsr & 0x1f;
 140         m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
 141
 142         L = l * BASE_CLK;
 143         M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
 144
 145         return M;
 146 }
 147
 148 static const struct clkops clk_pxa27x_mem_ops = {
 149         .enable         = clk_dummy_enable,
 150         .disable        = clk_dummy_disable,
 151         .getrate        = clk_pxa27x_mem_getrate,
 152 };
 153
 154 /*
 155  * Return the current LCD clock frequency in units of 10kHz as
 156  */
 157 static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
 158 {
 159         unsigned long ccsr;
 160         unsigned int l, L, k, K;
 161
 162         ccsr = CCSR;
 163
 164         l = ccsr & 0x1f;
 165         k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
 166
 167         L = l * BASE_CLK;
 168         K = L / k;
 169
 170         return (K / 10000);
 171 }
 172
 173 static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
 174 {
 175         return pxa27x_get_lcdclk_frequency_10khz() * 10000;
 176 }
 177
 178 static const struct clkops clk_pxa27x_lcd_ops = {
 179         .enable         = clk_pxa2xx_cken_enable,
 180         .disable        = clk_pxa2xx_cken_disable,
 181         .getrate        = clk_pxa27x_lcd_getrate,
 182 };
 183
 184 static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
 185 static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
 186 static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
 187 static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
 188 static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
 189 static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
 190 static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
 191 static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
 192 static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
 193 static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
 194 static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
 195 static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
 196 static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
 197 static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
 198 static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
 199 static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
 200 static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
 201 static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
 202 static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
 203 static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
 204 static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
 205 static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
 206 static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
 207
 208 static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
 209 static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
 210 static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
 211
 212 static struct clk_lookup pxa27x_clkregs[] = {
 213         INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
 214         INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
 215         INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
 216         INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
 217         INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
 218         INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
 219         INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
 220         INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
 221         INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
 222         INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
 223         INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
 224         INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
 225         INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
 226         INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
 227         INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
 228         INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
 229         INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
 230         INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
 231         INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
 232         INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
 233         INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
 234         INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
 235         INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
 236         INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
 237         INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
 238         INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
 239         INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
 240         INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
 241 };
 242
 243 #ifdef CONFIG_PM
 244
 245 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
 246 #define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
 247
 248 /*
 249  * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
 250  */
 251 static unsigned int pwrmode = PWRMODE_SLEEP;
 252
 253 int __init pxa27x_set_pwrmode(unsigned int mode)
 254 {
 255         switch (mode) {
 256         case PWRMODE_SLEEP:
 257         case PWRMODE_DEEPSLEEP:
 258                 pwrmode = mode;
 259                 return 0;
 260         }
 261
 262         return -EINVAL;
 263 }
 264
 265 /*
 266  * List of global PXA peripheral registers to preserve.
 267  * More ones like CP and general purpose register values are preserved
 268  * with the stack pointer in sleep.S.
 269  */
 270 enum {
 271         SLEEP_SAVE_PSTR,
 272         SLEEP_SAVE_MDREFR,
 273         SLEEP_SAVE_PCFR,
 274         SLEEP_SAVE_COUNT
 275 };
 276
 277 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
 278 {
 279         sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
 280         SAVE(PCFR);
 281
 282         SAVE(PSTR);
 283 }
 284
 285 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
 286 {
 287         __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
 288         RESTORE(PCFR);
 289
 290         PSSR = PSSR_RDH | PSSR_PH;
 291
 292         RESTORE(PSTR);
 293 }
 294
 295 void pxa27x_cpu_pm_enter(suspend_state_t state)
 296 {
 297         extern void pxa_cpu_standby(void);
 298 #ifndef CONFIG_IWMMXT
 299         u64 acc0;
 300
 301         asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
 302 #endif
 303
 304         /* ensure voltage-change sequencer not initiated, which hangs */
 305         PCFR &= ~PCFR_FVC;
 306
 307         /* Clear edge-detect status register. */
 308         PEDR = 0xDF12FE1B;
 309
 310         /* Clear reset status */
 311         RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
 312
 313         switch (state) {
 314         case PM_SUSPEND_STANDBY:
 315                 pxa_cpu_standby();
 316                 break;
 317         case PM_SUSPEND_MEM:
 318                 cpu_suspend(pwrmode, pxa27x_finish_suspend);
 319 #ifndef CONFIG_IWMMXT
 320                 asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
 321 #endif
 322                 break;
 323         }
 324 }
 325
 326 static int pxa27x_cpu_pm_valid(suspend_state_t state)
 327 {
 328         return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
 329 }
 330
 331 static int pxa27x_cpu_pm_prepare(void)
 332 {
 333         /* set resume return address */
 334         PSPR = virt_to_phys(cpu_resume);
 335         return 0;
 336 }
 337
 338 static void pxa27x_cpu_pm_finish(void)
 339 {
 340         /* ensure not to come back here if it wasn't intended */
 341         PSPR = 0;
 342 }
 343
 344 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
 345         .save_count     = SLEEP_SAVE_COUNT,
 346         .save           = pxa27x_cpu_pm_save,
 347         .restore        = pxa27x_cpu_pm_restore,
 348         .valid          = pxa27x_cpu_pm_valid,
 349         .enter          = pxa27x_cpu_pm_enter,
 350         .prepare        = pxa27x_cpu_pm_prepare,
 351         .finish         = pxa27x_cpu_pm_finish,
 352 };
 353
 354 static void __init pxa27x_init_pm(void)
 355 {
 356         pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
 357 }
 358 #else
 359 static inline void pxa27x_init_pm(void) {}
 360 #endif
 361
 362 /* PXA27x:  Various gpios can issue wakeup events.  This logic only
 363  * handles the simple cases, not the WEMUX2 and WEMUX3 options
 364  */
 365 static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
 366 {
 367         int gpio = pxa_irq_to_gpio(d->irq);
 368         uint32_t mask;
 369
 370         if (gpio >= 0 && gpio < 128)
 371                 return gpio_set_wake(gpio, on);
 372
 373         if (d->irq == IRQ_KEYPAD)
 374                 return keypad_set_wake(on);
 375
 376         switch (d->irq) {
 377         case IRQ_RTCAlrm:
 378                 mask = PWER_RTC;
 379                 break;
 380         case IRQ_USB:
 381                 mask = 1u << 26;
 382                 break;
 383         default:
 384                 return -EINVAL;
 385         }
 386
 387         if (on)
 388                 PWER |= mask;
 389         else
 390                 PWER &=~mask;
 391
 392         return 0;
 393 }
 394
 395 void __init pxa27x_init_irq(void)
 396 {
 397         pxa_init_irq(34, pxa27x_set_wake);
 398 }
 399
 400 static struct map_desc pxa27x_io_desc[] __initdata = {
 401         {       /* Mem Ctl */
 402                 .virtual        = (unsigned long)SMEMC_VIRT,
 403                 .pfn            = __phys_to_pfn(PXA2XX_SMEMC_BASE),
 404                 .length         = 0x00200000,
 405                 .type           = MT_DEVICE
 406         }, {    /* IMem ctl */
 407                 .virtual        =  0xfe000000,
 408                 .pfn            = __phys_to_pfn(0x58000000),
 409                 .length         = 0x00100000,
 410                 .type           = MT_DEVICE
 411         },
 412 };
 413
 414 void __init pxa27x_map_io(void)
 415 {
 416         pxa_map_io();
 417         iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
 418         pxa27x_get_clk_frequency_khz(1);
 419 }
 420
 421 /*
 422  * device registration specific to PXA27x.
 423  */
 424 void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 425 {
 426         local_irq_disable();
 427         PCFR |= PCFR_PI2CEN;
 428         local_irq_enable();
 429         pxa_register_device(&pxa27x_device_i2c_power, info);
 430 }
 431
 432 static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
 433         .gpio_set_wake = gpio_set_wake,
 434 };
 435
 436 static struct platform_device *devices[] __initdata = {
 437         &pxa27x_device_udc,
 438         &pxa_device_pmu,
 439         &pxa_device_i2s,
 440         &pxa_device_asoc_ssp1,
 441         &pxa_device_asoc_ssp2,
 442         &pxa_device_asoc_ssp3,
 443         &pxa_device_asoc_platform,
 444         &sa1100_device_rtc,
 445         &pxa_device_rtc,
 446         &pxa27x_device_ssp1,
 447         &pxa27x_device_ssp2,
 448         &pxa27x_device_ssp3,
 449         &pxa27x_device_pwm0,
 450         &pxa27x_device_pwm1,
 451 };
 452
 453 static int __init pxa27x_init(void)
 454 {
 455         int ret = 0;
 456
 457         if (cpu_is_pxa27x()) {
 458
 459                 reset_status = RCSR;
 460
 461                 clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
 462
 463                 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
 464                         return ret;
 465
 466                 pxa27x_init_pm();
 467
 468                 register_syscore_ops(&pxa_irq_syscore_ops);
 469                 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
 470                 register_syscore_ops(&pxa2xx_clock_syscore_ops);
 471
 472                 pxa_register_device(&pxa_device_gpio, &pxa27x_gpio_info);
 473                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
 474         }
 475
 476         return ret;
 477 }
 478
 479 postcore_initcall(pxa27x_init);