arch/arm/mach-pxa/pxa3xx.c

   1 /*
   2  * linux/arch/arm/mach-pxa/pxa3xx.c
   3  *
   4  * code specific to pxa3xx aka Monahans
   5  *
   6  * Copyright (C) 2006 Marvell International Ltd.
   7  *
   8  * 2007-09-02: eric miao <eric.miao@marvell.com>
   9  *             initial version
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/pm.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/irq.h>
  21 #include <linux/io.h>
  22 #include <linux/syscore_ops.h>
  23 #include <linux/i2c/pxa-i2c.h>
  24
  25 #include <asm/mach/map.h>
  26 #include <asm/suspend.h>
  27 #include <mach/hardware.h>
  28 #include <mach/pxa3xx-regs.h>
  29 #include <mach/reset.h>
  30 #include <mach/ohci.h>
  31 #include <mach/pm.h>
  32 #include <mach/dma.h>
  33 #include <mach/smemc.h>
  34
  35 #include "generic.h"
  36 #include "devices.h"
  37 #include "clock.h"
  38
  39 #define PECR_IE(n)      ((1 << ((n) * 2)) << 28)
  40 #define PECR_IS(n)      ((1 << ((n) * 2)) << 29)
  41
  42 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
  43 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
  44 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
  45 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
  46 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
  47 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
  48 static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
  49 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
  50 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
  51 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
  52 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
  53 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
  54 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
  55 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
  56 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
  57 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
  58 static DEFINE_PXA3_CKEN(pxa3xx_gpio, GPIO, 13000000, 0);
  59
  60 static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
  61 static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
  62 static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
  63 static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
  64 static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
  65
  66 static struct clk_lookup pxa3xx_clkregs[] = {
  67         INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
  68         /* Power I2C clock is always on */
  69         INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
  70         INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
  71         INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
  72         INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
  73         INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
  74         INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
  75         INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
  76         INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
  77         INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
  78         INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
  79         INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
  80         INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
  81         INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
  82         INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
  83         INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
  84         INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
  85         INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
  86         INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
  87         INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
  88         INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
  89         INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
  90         INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
  91         INIT_CLKREG(&clk_pxa3xx_gpio, "pxa-gpio", NULL),
  92         INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
  93 };
  94
  95 #ifdef CONFIG_PM
  96
  97 #define ISRAM_START     0x5c000000
  98 #define ISRAM_SIZE      SZ_256K
  99
 100 static void __iomem *sram;
 101 static unsigned long wakeup_src;
 102
 103 /*
 104  * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
 105  * memory controller has to be reinitialised, so we place some code
 106  * in the SRAM to perform this function.
 107  *
 108  * We disable FIQs across the standby - otherwise, we might receive a
 109  * FIQ while the SDRAM is unavailable.
 110  */
 111 static void pxa3xx_cpu_standby(unsigned int pwrmode)
 112 {
 113         extern const char pm_enter_standby_start[], pm_enter_standby_end[];
 114         void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
 115
 116         memcpy_toio(sram + 0x8000, pm_enter_standby_start,
 117                     pm_enter_standby_end - pm_enter_standby_start);
 118
 119         AD2D0SR = ~0;
 120         AD2D1SR = ~0;
 121         AD2D0ER = wakeup_src;
 122         AD2D1ER = 0;
 123         ASCR = ASCR;
 124         ARSR = ARSR;
 125
 126         local_fiq_disable();
 127         fn(pwrmode);
 128         local_fiq_enable();
 129
 130         AD2D0ER = 0;
 131         AD2D1ER = 0;
 132 }
 133
 134 /*
 135  * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
 136  * PXA3xx development kits assumes that the resuming process continues
 137  * with the address stored within the first 4 bytes of SDRAM. The PSPR
 138  * register is used privately by BootROM and OBM, and _must_ be set to
 139  * 0x5c014000 for the moment.
 140  */
 141 static void pxa3xx_cpu_pm_suspend(void)
 142 {
 143         volatile unsigned long *p = (volatile void *)0xc0000000;
 144         unsigned long saved_data = *p;
 145 #ifndef CONFIG_IWMMXT
 146         u64 acc0;
 147
 148         asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
 149 #endif
 150
 151         extern int pxa3xx_finish_suspend(unsigned long);
 152
 153         /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
 154         CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
 155         CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
 156
 157         /* clear and setup wakeup source */
 158         AD3SR = ~0;
 159         AD3ER = wakeup_src;
 160         ASCR = ASCR;
 161         ARSR = ARSR;
 162
 163         PCFR |= (1u << 13);                     /* L1_DIS */
 164         PCFR &= ~((1u << 12) | (1u << 1));      /* L0_EN | SL_ROD */
 165
 166         PSPR = 0x5c014000;
 167
 168         /* overwrite with the resume address */
 169         *p = virt_to_phys(cpu_resume);
 170
 171         cpu_suspend(0, pxa3xx_finish_suspend);
 172
 173         *p = saved_data;
 174
 175         AD3ER = 0;
 176
 177 #ifndef CONFIG_IWMMXT
 178         asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
 179 #endif
 180 }
 181
 182 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
 183 {
 184         /*
 185          * Don't sleep if no wakeup sources are defined
 186          */
 187         if (wakeup_src == 0) {
 188                 printk(KERN_ERR "Not suspending: no wakeup sources\n");
 189                 return;
 190         }
 191
 192         switch (state) {
 193         case PM_SUSPEND_STANDBY:
 194                 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
 195                 break;
 196
 197         case PM_SUSPEND_MEM:
 198                 pxa3xx_cpu_pm_suspend();
 199                 break;
 200         }
 201 }
 202
 203 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
 204 {
 205         return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
 206 }
 207
 208 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
 209         .valid          = pxa3xx_cpu_pm_valid,
 210         .enter          = pxa3xx_cpu_pm_enter,
 211 };
 212
 213 static void __init pxa3xx_init_pm(void)
 214 {
 215         sram = ioremap(ISRAM_START, ISRAM_SIZE);
 216         if (!sram) {
 217                 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
 218                 return;
 219         }
 220
 221         /*
 222          * Since we copy wakeup code into the SRAM, we need to ensure
 223          * that it is preserved over the low power modes.  Note: bit 8
 224          * is undocumented in the developer manual, but must be set.
 225          */
 226         AD1R |= ADXR_L2 | ADXR_R0;
 227         AD2R |= ADXR_L2 | ADXR_R0;
 228         AD3R |= ADXR_L2 | ADXR_R0;
 229
 230         /*
 231          * Clear the resume enable registers.
 232          */
 233         AD1D0ER = 0;
 234         AD2D0ER = 0;
 235         AD2D1ER = 0;
 236         AD3ER = 0;
 237
 238         pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
 239 }
 240
 241 static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
 242 {
 243         unsigned long flags, mask = 0;
 244
 245         switch (d->irq) {
 246         case IRQ_SSP3:
 247                 mask = ADXER_MFP_WSSP3;
 248                 break;
 249         case IRQ_MSL:
 250                 mask = ADXER_WMSL0;
 251                 break;
 252         case IRQ_USBH2:
 253         case IRQ_USBH1:
 254                 mask = ADXER_WUSBH;
 255                 break;
 256         case IRQ_KEYPAD:
 257                 mask = ADXER_WKP;
 258                 break;
 259         case IRQ_AC97:
 260                 mask = ADXER_MFP_WAC97;
 261                 break;
 262         case IRQ_USIM:
 263                 mask = ADXER_WUSIM0;
 264                 break;
 265         case IRQ_SSP2:
 266                 mask = ADXER_MFP_WSSP2;
 267                 break;
 268         case IRQ_I2C:
 269                 mask = ADXER_MFP_WI2C;
 270                 break;
 271         case IRQ_STUART:
 272                 mask = ADXER_MFP_WUART3;
 273                 break;
 274         case IRQ_BTUART:
 275                 mask = ADXER_MFP_WUART2;
 276                 break;
 277         case IRQ_FFUART:
 278                 mask = ADXER_MFP_WUART1;
 279                 break;
 280         case IRQ_MMC:
 281                 mask = ADXER_MFP_WMMC1;
 282                 break;
 283         case IRQ_SSP:
 284                 mask = ADXER_MFP_WSSP1;
 285                 break;
 286         case IRQ_RTCAlrm:
 287                 mask = ADXER_WRTC;
 288                 break;
 289         case IRQ_SSP4:
 290                 mask = ADXER_MFP_WSSP4;
 291                 break;
 292         case IRQ_TSI:
 293                 mask = ADXER_WTSI;
 294                 break;
 295         case IRQ_USIM2:
 296                 mask = ADXER_WUSIM1;
 297                 break;
 298         case IRQ_MMC2:
 299                 mask = ADXER_MFP_WMMC2;
 300                 break;
 301         case IRQ_NAND:
 302                 mask = ADXER_MFP_WFLASH;
 303                 break;
 304         case IRQ_USB2:
 305                 mask = ADXER_WUSB2;
 306                 break;
 307         case IRQ_WAKEUP0:
 308                 mask = ADXER_WEXTWAKE0;
 309                 break;
 310         case IRQ_WAKEUP1:
 311                 mask = ADXER_WEXTWAKE1;
 312                 break;
 313         case IRQ_MMC3:
 314                 mask = ADXER_MFP_GEN12;
 315                 break;
 316         default:
 317                 return -EINVAL;
 318         }
 319
 320         local_irq_save(flags);
 321         if (on)
 322                 wakeup_src |= mask;
 323         else
 324                 wakeup_src &= ~mask;
 325         local_irq_restore(flags);
 326
 327         return 0;
 328 }
 329 #else
 330 static inline void pxa3xx_init_pm(void) {}
 331 #define pxa3xx_set_wake NULL
 332 #endif
 333
 334 static void pxa_ack_ext_wakeup(struct irq_data *d)
 335 {
 336         PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
 337 }
 338
 339 static void pxa_mask_ext_wakeup(struct irq_data *d)
 340 {
 341         pxa_mask_irq(d);
 342         PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
 343 }
 344
 345 static void pxa_unmask_ext_wakeup(struct irq_data *d)
 346 {
 347         pxa_unmask_irq(d);
 348         PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
 349 }
 350
 351 static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
 352 {
 353         if (flow_type & IRQ_TYPE_EDGE_RISING)
 354                 PWER |= 1 << (d->irq - IRQ_WAKEUP0);
 355
 356         if (flow_type & IRQ_TYPE_EDGE_FALLING)
 357                 PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);
 358
 359         return 0;
 360 }
 361
 362 static struct irq_chip pxa_ext_wakeup_chip = {
 363         .name           = "WAKEUP",
 364         .irq_ack        = pxa_ack_ext_wakeup,
 365         .irq_mask       = pxa_mask_ext_wakeup,
 366         .irq_unmask     = pxa_unmask_ext_wakeup,
 367         .irq_set_type   = pxa_set_ext_wakeup_type,
 368 };
 369
 370 static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
 371                                            unsigned int))
 372 {
 373         int irq;
 374
 375         for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
 376                 irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
 377                                          handle_edge_irq);
 378                 set_irq_flags(irq, IRQF_VALID);
 379         }
 380
 381         pxa_ext_wakeup_chip.irq_set_wake = fn;
 382 }
 383
 384 void __init pxa3xx_init_irq(void)
 385 {
 386         /* enable CP6 access */
 387         u32 value;
 388         __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
 389         value |= (1 << 6);
 390         __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
 391
 392         pxa_init_irq(56, pxa3xx_set_wake);
 393         pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
 394 }
 395
 396 static struct map_desc pxa3xx_io_desc[] __initdata = {
 397         {       /* Mem Ctl */
 398                 .virtual        = (unsigned long)SMEMC_VIRT,
 399                 .pfn            = __phys_to_pfn(PXA3XX_SMEMC_BASE),
 400                 .length         = 0x00200000,
 401                 .type           = MT_DEVICE
 402         }
 403 };
 404
 405 void __init pxa3xx_map_io(void)
 406 {
 407         pxa_map_io();
 408         iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
 409         pxa3xx_get_clk_frequency_khz(1);
 410 }
 411
 412 /*
 413  * device registration specific to PXA3xx.
 414  */
 415
 416 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 417 {
 418         pxa_register_device(&pxa3xx_device_i2c_power, info);
 419 }
 420
 421 static struct platform_device *devices[] __initdata = {
 422         &pxa_device_gpio,
 423         &pxa27x_device_udc,
 424         &pxa_device_pmu,
 425         &pxa_device_i2s,
 426         &pxa_device_asoc_ssp1,
 427         &pxa_device_asoc_ssp2,
 428         &pxa_device_asoc_ssp3,
 429         &pxa_device_asoc_ssp4,
 430         &pxa_device_asoc_platform,
 431         &sa1100_device_rtc,
 432         &pxa_device_rtc,
 433         &pxa27x_device_ssp1,
 434         &pxa27x_device_ssp2,
 435         &pxa27x_device_ssp3,
 436         &pxa3xx_device_ssp4,
 437         &pxa27x_device_pwm0,
 438         &pxa27x_device_pwm1,
 439 };
 440
 441 static int __init pxa3xx_init(void)
 442 {
 443         int ret = 0;
 444
 445         if (cpu_is_pxa3xx()) {
 446
 447                 reset_status = ARSR;
 448
 449                 /*
 450                  * clear RDH bit every time after reset
 451                  *
 452                  * Note: the last 3 bits DxS are write-1-to-clear so carefully
 453                  * preserve them here in case they will be referenced later
 454                  */
 455                 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
 456
 457                 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
 458
 459                 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
 460                         return ret;
 461
 462                 pxa3xx_init_pm();
 463
 464                 register_syscore_ops(&pxa_irq_syscore_ops);
 465                 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
 466                 register_syscore_ops(&pxa3xx_clock_syscore_ops);
 467
 468                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
 469         }
 470
 471         return ret;
 472 }
 473
 474 postcore_initcall(pxa3xx_init);