arch/arm/mach-pxa/pxa3xx.c

   1 /*
   2  * linux/arch/arm/mach-pxa/pxa3xx.c
   3  *
   4  * code specific to pxa3xx aka Monahans
   5  *
   6  * Copyright (C) 2006 Marvell International Ltd.
   7  *
   8  * 2007-09-02: eric miao <eric.miao@marvell.com>
   9  *             initial version
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/pm.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23 #include <linux/sysdev.h>
  24
  25 #include <mach/hardware.h>
  26 #include <mach/pxa3xx-regs.h>
  27 #include <mach/reset.h>
  28 #include <mach/ohci.h>
  29 #include <mach/pm.h>
  30 #include <mach/dma.h>
  31 #include <mach/ssp.h>
  32 #include <mach/i2c.h>
  33
  34 #include "generic.h"
  35 #include "devices.h"
  36 #include "clock.h"
  37
  38 /* Crystal clock: 13MHz */
  39 #define BASE_CLK        13000000
  40
  41 /* Ring Oscillator Clock: 60MHz */
  42 #define RO_CLK          60000000
  43
  44 #define ACCR_D0CS       (1 << 26)
  45 #define ACCR_PCCE       (1 << 11)
  46
  47 /* crystal frequency to static memory controller multiplier (SMCFS) */
  48 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
  49
  50 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
  51 static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
  52
  53 /*
  54  * Get the clock frequency as reflected by CCSR and the turbo flag.
  55  * We assume these values have been applied via a fcs.
  56  * If info is not 0 we also display the current settings.
  57  */
  58 unsigned int pxa3xx_get_clk_frequency_khz(int info)
  59 {
  60         unsigned long acsr, xclkcfg;
  61         unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
  62
  63         /* Read XCLKCFG register turbo bit */
  64         __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
  65         t = xclkcfg & 0x1;
  66
  67         acsr = ACSR;
  68
  69         xl  = acsr & 0x1f;
  70         xn  = (acsr >> 8) & 0x7;
  71         hss = (acsr >> 14) & 0x3;
  72
  73         XL = xl * BASE_CLK;
  74         XN = xn * XL;
  75
  76         ro = acsr & ACCR_D0CS;
  77
  78         CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
  79         HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
  80
  81         if (info) {
  82                 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
  83                         RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
  84                         (ro) ? "" : "in");
  85                 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
  86                         XL / 1000000, (XL % 1000000) / 10000, xl);
  87                 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
  88                         XN / 1000000, (XN % 1000000) / 10000, xn,
  89                         (t) ? "" : "in");
  90                 pr_info("HSIO bus clock: %d.%02dMHz\n",
  91                         HSS / 1000000, (HSS % 1000000) / 10000);
  92         }
  93
  94         return CLK / 1000;
  95 }
  96
  97 /*
  98  * Return the current static memory controller clock frequency
  99  * in units of 10kHz
 100  */
 101 unsigned int pxa3xx_get_memclk_frequency_10khz(void)
 102 {
 103         unsigned long acsr;
 104         unsigned int smcfs, clk = 0;
 105
 106         acsr = ACSR;
 107
 108         smcfs = (acsr >> 23) & 0x7;
 109         clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
 110
 111         return (clk / 10000);
 112 }
 113
 114 void pxa3xx_clear_reset_status(unsigned int mask)
 115 {
 116         /* RESET_STATUS_* has a 1:1 mapping with ARSR */
 117         ARSR = mask;
 118 }
 119
 120 /*
 121  * Return the current AC97 clock frequency.
 122  */
 123 static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
 124 {
 125         unsigned long rate = 312000000;
 126         unsigned long ac97_div;
 127
 128         ac97_div = AC97_DIV;
 129
 130         /* This may loose precision for some rates but won't for the
 131          * standard 24.576MHz.
 132          */
 133         rate /= (ac97_div >> 12) & 0x7fff;
 134         rate *= (ac97_div & 0xfff);
 135
 136         return rate;
 137 }
 138
 139 /*
 140  * Return the current HSIO bus clock frequency
 141  */
 142 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
 143 {
 144         unsigned long acsr;
 145         unsigned int hss, hsio_clk;
 146
 147         acsr = ACSR;
 148
 149         hss = (acsr >> 14) & 0x3;
 150         hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
 151
 152         return hsio_clk;
 153 }
 154
 155 void clk_pxa3xx_cken_enable(struct clk *clk)
 156 {
 157         unsigned long mask = 1ul << (clk->cken & 0x1f);
 158
 159         if (clk->cken < 32)
 160                 CKENA |= mask;
 161         else
 162                 CKENB |= mask;
 163 }
 164
 165 void clk_pxa3xx_cken_disable(struct clk *clk)
 166 {
 167         unsigned long mask = 1ul << (clk->cken & 0x1f);
 168
 169         if (clk->cken < 32)
 170                 CKENA &= ~mask;
 171         else
 172                 CKENB &= ~mask;
 173 }
 174
 175 const struct clkops clk_pxa3xx_cken_ops = {
 176         .enable         = clk_pxa3xx_cken_enable,
 177         .disable        = clk_pxa3xx_cken_disable,
 178 };
 179
 180 static const struct clkops clk_pxa3xx_hsio_ops = {
 181         .enable         = clk_pxa3xx_cken_enable,
 182         .disable        = clk_pxa3xx_cken_disable,
 183         .getrate        = clk_pxa3xx_hsio_getrate,
 184 };
 185
 186 static const struct clkops clk_pxa3xx_ac97_ops = {
 187         .enable         = clk_pxa3xx_cken_enable,
 188         .disable        = clk_pxa3xx_cken_disable,
 189         .getrate        = clk_pxa3xx_ac97_getrate,
 190 };
 191
 192 static void clk_pout_enable(struct clk *clk)
 193 {
 194         OSCC |= OSCC_PEN;
 195 }
 196
 197 static void clk_pout_disable(struct clk *clk)
 198 {
 199         OSCC &= ~OSCC_PEN;
 200 }
 201
 202 static const struct clkops clk_pout_ops = {
 203         .enable         = clk_pout_enable,
 204         .disable        = clk_pout_disable,
 205 };
 206
 207 static void clk_dummy_enable(struct clk *clk)
 208 {
 209 }
 210
 211 static void clk_dummy_disable(struct clk *clk)
 212 {
 213 }
 214
 215 static const struct clkops clk_dummy_ops = {
 216         .enable         = clk_dummy_enable,
 217         .disable        = clk_dummy_disable,
 218 };
 219
 220 static struct clk clk_pxa3xx_pout = {
 221         .ops            = &clk_pout_ops,
 222         .rate           = 13000000,
 223         .delay          = 70,
 224 };
 225
 226 static struct clk clk_dummy = {
 227         .ops            = &clk_dummy_ops,
 228 };
 229
 230 static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
 231 static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
 232 static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
 233 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
 234 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
 235 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
 236 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
 237 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
 238 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
 239 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
 240 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
 241 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
 242 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
 243 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
 244 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
 245 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
 246 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
 247 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
 248
 249 static struct clk_lookup pxa3xx_clkregs[] = {
 250         INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
 251         /* Power I2C clock is always on */
 252         INIT_CLKREG(&clk_dummy, "pxa2xx-i2c.1", NULL),
 253         INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
 254         INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
 255         INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
 256         INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
 257         INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
 258         INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
 259         INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
 260         INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
 261         INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
 262         INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
 263         INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
 264         INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
 265         INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
 266         INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
 267         INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
 268         INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
 269         INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
 270         INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
 271         INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
 272 };
 273
 274 #ifdef CONFIG_PM
 275
 276 #define ISRAM_START     0x5c000000
 277 #define ISRAM_SIZE      SZ_256K
 278
 279 static void __iomem *sram;
 280 static unsigned long wakeup_src;
 281
 282 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
 283 #define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
 284
 285 enum {  SLEEP_SAVE_CKENA,
 286         SLEEP_SAVE_CKENB,
 287         SLEEP_SAVE_ACCR,
 288
 289         SLEEP_SAVE_COUNT,
 290 };
 291
 292 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
 293 {
 294         SAVE(CKENA);
 295         SAVE(CKENB);
 296         SAVE(ACCR);
 297 }
 298
 299 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
 300 {
 301         RESTORE(ACCR);
 302         RESTORE(CKENA);
 303         RESTORE(CKENB);
 304 }
 305
 306 /*
 307  * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
 308  * memory controller has to be reinitialised, so we place some code
 309  * in the SRAM to perform this function.
 310  *
 311  * We disable FIQs across the standby - otherwise, we might receive a
 312  * FIQ while the SDRAM is unavailable.
 313  */
 314 static void pxa3xx_cpu_standby(unsigned int pwrmode)
 315 {
 316         extern const char pm_enter_standby_start[], pm_enter_standby_end[];
 317         void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
 318
 319         memcpy_toio(sram + 0x8000, pm_enter_standby_start,
 320                     pm_enter_standby_end - pm_enter_standby_start);
 321
 322         AD2D0SR = ~0;
 323         AD2D1SR = ~0;
 324         AD2D0ER = wakeup_src;
 325         AD2D1ER = 0;
 326         ASCR = ASCR;
 327         ARSR = ARSR;
 328
 329         local_fiq_disable();
 330         fn(pwrmode);
 331         local_fiq_enable();
 332
 333         AD2D0ER = 0;
 334         AD2D1ER = 0;
 335 }
 336
 337 /*
 338  * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
 339  * PXA3xx development kits assumes that the resuming process continues
 340  * with the address stored within the first 4 bytes of SDRAM. The PSPR
 341  * register is used privately by BootROM and OBM, and _must_ be set to
 342  * 0x5c014000 for the moment.
 343  */
 344 static void pxa3xx_cpu_pm_suspend(void)
 345 {
 346         volatile unsigned long *p = (volatile void *)0xc0000000;
 347         unsigned long saved_data = *p;
 348
 349         extern void pxa3xx_cpu_suspend(void);
 350         extern void pxa3xx_cpu_resume(void);
 351
 352         /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
 353         CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
 354         CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
 355
 356         /* clear and setup wakeup source */
 357         AD3SR = ~0;
 358         AD3ER = wakeup_src;
 359         ASCR = ASCR;
 360         ARSR = ARSR;
 361
 362         PCFR |= (1u << 13);                     /* L1_DIS */
 363         PCFR &= ~((1u << 12) | (1u << 1));      /* L0_EN | SL_ROD */
 364
 365         PSPR = 0x5c014000;
 366
 367         /* overwrite with the resume address */
 368         *p = virt_to_phys(pxa3xx_cpu_resume);
 369
 370         pxa3xx_cpu_suspend();
 371
 372         *p = saved_data;
 373
 374         AD3ER = 0;
 375 }
 376
 377 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
 378 {
 379         /*
 380          * Don't sleep if no wakeup sources are defined
 381          */
 382         if (wakeup_src == 0) {
 383                 printk(KERN_ERR "Not suspending: no wakeup sources\n");
 384                 return;
 385         }
 386
 387         switch (state) {
 388         case PM_SUSPEND_STANDBY:
 389                 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
 390                 break;
 391
 392         case PM_SUSPEND_MEM:
 393                 pxa3xx_cpu_pm_suspend();
 394                 break;
 395         }
 396 }
 397
 398 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
 399 {
 400         return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
 401 }
 402
 403 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
 404         .save_count     = SLEEP_SAVE_COUNT,
 405         .save           = pxa3xx_cpu_pm_save,
 406         .restore        = pxa3xx_cpu_pm_restore,
 407         .valid          = pxa3xx_cpu_pm_valid,
 408         .enter          = pxa3xx_cpu_pm_enter,
 409 };
 410
 411 static void __init pxa3xx_init_pm(void)
 412 {
 413         sram = ioremap(ISRAM_START, ISRAM_SIZE);
 414         if (!sram) {
 415                 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
 416                 return;
 417         }
 418
 419         /*
 420          * Since we copy wakeup code into the SRAM, we need to ensure
 421          * that it is preserved over the low power modes.  Note: bit 8
 422          * is undocumented in the developer manual, but must be set.
 423          */
 424         AD1R |= ADXR_L2 | ADXR_R0;
 425         AD2R |= ADXR_L2 | ADXR_R0;
 426         AD3R |= ADXR_L2 | ADXR_R0;
 427
 428         /*
 429          * Clear the resume enable registers.
 430          */
 431         AD1D0ER = 0;
 432         AD2D0ER = 0;
 433         AD2D1ER = 0;
 434         AD3ER = 0;
 435
 436         pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
 437 }
 438
 439 static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
 440 {
 441         unsigned long flags, mask = 0;
 442
 443         switch (irq) {
 444         case IRQ_SSP3:
 445                 mask = ADXER_MFP_WSSP3;
 446                 break;
 447         case IRQ_MSL:
 448                 mask = ADXER_WMSL0;
 449                 break;
 450         case IRQ_USBH2:
 451         case IRQ_USBH1:
 452                 mask = ADXER_WUSBH;
 453                 break;
 454         case IRQ_KEYPAD:
 455                 mask = ADXER_WKP;
 456                 break;
 457         case IRQ_AC97:
 458                 mask = ADXER_MFP_WAC97;
 459                 break;
 460         case IRQ_USIM:
 461                 mask = ADXER_WUSIM0;
 462                 break;
 463         case IRQ_SSP2:
 464                 mask = ADXER_MFP_WSSP2;
 465                 break;
 466         case IRQ_I2C:
 467                 mask = ADXER_MFP_WI2C;
 468                 break;
 469         case IRQ_STUART:
 470                 mask = ADXER_MFP_WUART3;
 471                 break;
 472         case IRQ_BTUART:
 473                 mask = ADXER_MFP_WUART2;
 474                 break;
 475         case IRQ_FFUART:
 476                 mask = ADXER_MFP_WUART1;
 477                 break;
 478         case IRQ_MMC:
 479                 mask = ADXER_MFP_WMMC1;
 480                 break;
 481         case IRQ_SSP:
 482                 mask = ADXER_MFP_WSSP1;
 483                 break;
 484         case IRQ_RTCAlrm:
 485                 mask = ADXER_WRTC;
 486                 break;
 487         case IRQ_SSP4:
 488                 mask = ADXER_MFP_WSSP4;
 489                 break;
 490         case IRQ_TSI:
 491                 mask = ADXER_WTSI;
 492                 break;
 493         case IRQ_USIM2:
 494                 mask = ADXER_WUSIM1;
 495                 break;
 496         case IRQ_MMC2:
 497                 mask = ADXER_MFP_WMMC2;
 498                 break;
 499         case IRQ_NAND:
 500                 mask = ADXER_MFP_WFLASH;
 501                 break;
 502         case IRQ_USB2:
 503                 mask = ADXER_WUSB2;
 504                 break;
 505         case IRQ_WAKEUP0:
 506                 mask = ADXER_WEXTWAKE0;
 507                 break;
 508         case IRQ_WAKEUP1:
 509                 mask = ADXER_WEXTWAKE1;
 510                 break;
 511         case IRQ_MMC3:
 512                 mask = ADXER_MFP_GEN12;
 513                 break;
 514         default:
 515                 return -EINVAL;
 516         }
 517
 518         local_irq_save(flags);
 519         if (on)
 520                 wakeup_src |= mask;
 521         else
 522                 wakeup_src &= ~mask;
 523         local_irq_restore(flags);
 524
 525         return 0;
 526 }
 527 #else
 528 static inline void pxa3xx_init_pm(void) {}
 529 #define pxa3xx_set_wake NULL
 530 #endif
 531
 532 void __init pxa3xx_init_irq(void)
 533 {
 534         /* enable CP6 access */
 535         u32 value;
 536         __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
 537         value |= (1 << 6);
 538         __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
 539
 540         pxa_init_irq(56, pxa3xx_set_wake);
 541         pxa_init_gpio(128, NULL);
 542 }
 543
 544 /*
 545  * device registration specific to PXA3xx.
 546  */
 547
 548 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 549 {
 550         pxa_register_device(&pxa3xx_device_i2c_power, info);
 551 }
 552
 553 static struct platform_device *devices[] __initdata = {
 554 /*      &pxa_device_udc,        The UDC driver is PXA25x only */
 555         &pxa_device_ffuart,
 556         &pxa_device_btuart,
 557         &pxa_device_stuart,
 558         &pxa_device_i2s,
 559         &sa1100_device_rtc,
 560         &pxa_device_rtc,
 561         &pxa27x_device_ssp1,
 562         &pxa27x_device_ssp2,
 563         &pxa27x_device_ssp3,
 564         &pxa3xx_device_ssp4,
 565         &pxa27x_device_pwm0,
 566         &pxa27x_device_pwm1,
 567 };
 568
 569 static struct sys_device pxa3xx_sysdev[] = {
 570         {
 571                 .cls    = &pxa_irq_sysclass,
 572         }, {
 573                 .cls    = &pxa3xx_mfp_sysclass,
 574         }, {
 575                 .cls    = &pxa_gpio_sysclass,
 576         },
 577 };
 578
 579 static int __init pxa3xx_init(void)
 580 {
 581         int i, ret = 0;
 582
 583         if (cpu_is_pxa3xx()) {
 584
 585                 reset_status = ARSR;
 586
 587                 /*
 588                  * clear RDH bit every time after reset
 589                  *
 590                  * Note: the last 3 bits DxS are write-1-to-clear so carefully
 591                  * preserve them here in case they will be referenced later
 592                  */
 593                 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
 594
 595                 clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
 596
 597                 if ((ret = pxa_init_dma(32)))
 598                         return ret;
 599
 600                 pxa3xx_init_pm();
 601
 602                 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
 603                         ret = sysdev_register(&pxa3xx_sysdev[i]);
 604                         if (ret)
 605                                 pr_err("failed to register sysdev[%d]\n", i);
 606                 }
 607
 608                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
 609         }
 610
 611         return ret;
 612 }
 613
 614 postcore_initcall(pxa3xx_init);