arch/arm/mach-pxa/pxa3xx.c

   1 /*
   2  * linux/arch/arm/mach-pxa/pxa3xx.c
   3  *
   4  * code specific to pxa3xx aka Monahans
   5  *
   6  * Copyright (C) 2006 Marvell International Ltd.
   7  *
   8  * 2007-09-02: eric miao <eric.miao@marvell.com>
   9  *             initial version
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/pm.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/irq.h>
  21 #include <linux/io.h>
  22 #include <linux/of.h>
  23 #include <linux/syscore_ops.h>
  24 #include <linux/i2c/pxa-i2c.h>
  25
  26 #include <asm/mach/map.h>
  27 #include <asm/suspend.h>
  28 #include <mach/hardware.h>
  29 #include <mach/pxa3xx-regs.h>
  30 #include <mach/reset.h>
  31 #include <linux/platform_data/usb-ohci-pxa27x.h>
  32 #include <mach/pm.h>
  33 #include <mach/dma.h>
  34 #include <mach/smemc.h>
  35 #include <mach/irqs.h>
  36
  37 #include "generic.h"
  38 #include "devices.h"
  39 #include "clock.h"
  40
  41 #define PECR_IE(n)      ((1 << ((n) * 2)) << 28)
  42 #define PECR_IS(n)      ((1 << ((n) * 2)) << 29)
  43
  44 extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
  45
  46 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
  47 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
  48 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
  49 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
  50 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
  51 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
  52 static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
  53 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
  54 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
  55 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
  56 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
  57 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
  58 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
  59 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
  60 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
  61 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
  62 static DEFINE_PXA3_CKEN(pxa3xx_gpio, GPIO, 13000000, 0);
  63
  64 static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
  65 static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
  66 static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
  67 static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
  68 static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
  69
  70 static struct clk_lookup pxa3xx_clkregs[] = {
  71         INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
  72         /* Power I2C clock is always on */
  73         INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
  74         INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
  75         INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
  76         INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
  77         INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
  78         INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
  79         INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
  80         INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
  81         INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
  82         INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
  83         INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
  84         INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
  85         INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
  86         INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
  87         INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
  88         INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
  89         INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
  90         INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
  91         INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
  92         INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
  93         INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
  94         INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
  95         INIT_CLKREG(&clk_pxa3xx_gpio, "pxa3xx-gpio", NULL),
  96         INIT_CLKREG(&clk_pxa3xx_gpio, "pxa93x-gpio", NULL),
  97         INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
  98 };
  99
 100 #ifdef CONFIG_PM
 101
 102 #define ISRAM_START     0x5c000000
 103 #define ISRAM_SIZE      SZ_256K
 104
 105 static void __iomem *sram;
 106 static unsigned long wakeup_src;
 107
 108 /*
 109  * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
 110  * memory controller has to be reinitialised, so we place some code
 111  * in the SRAM to perform this function.
 112  *
 113  * We disable FIQs across the standby - otherwise, we might receive a
 114  * FIQ while the SDRAM is unavailable.
 115  */
 116 static void pxa3xx_cpu_standby(unsigned int pwrmode)
 117 {
 118         extern const char pm_enter_standby_start[], pm_enter_standby_end[];
 119         void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
 120
 121         memcpy_toio(sram + 0x8000, pm_enter_standby_start,
 122                     pm_enter_standby_end - pm_enter_standby_start);
 123
 124         AD2D0SR = ~0;
 125         AD2D1SR = ~0;
 126         AD2D0ER = wakeup_src;
 127         AD2D1ER = 0;
 128         ASCR = ASCR;
 129         ARSR = ARSR;
 130
 131         local_fiq_disable();
 132         fn(pwrmode);
 133         local_fiq_enable();
 134
 135         AD2D0ER = 0;
 136         AD2D1ER = 0;
 137 }
 138
 139 /*
 140  * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
 141  * PXA3xx development kits assumes that the resuming process continues
 142  * with the address stored within the first 4 bytes of SDRAM. The PSPR
 143  * register is used privately by BootROM and OBM, and _must_ be set to
 144  * 0x5c014000 for the moment.
 145  */
 146 static void pxa3xx_cpu_pm_suspend(void)
 147 {
 148         volatile unsigned long *p = (volatile void *)0xc0000000;
 149         unsigned long saved_data = *p;
 150 #ifndef CONFIG_IWMMXT
 151         u64 acc0;
 152
 153         asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
 154 #endif
 155
 156         extern int pxa3xx_finish_suspend(unsigned long);
 157
 158         /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
 159         CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
 160         CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
 161
 162         /* clear and setup wakeup source */
 163         AD3SR = ~0;
 164         AD3ER = wakeup_src;
 165         ASCR = ASCR;
 166         ARSR = ARSR;
 167
 168         PCFR |= (1u << 13);                     /* L1_DIS */
 169         PCFR &= ~((1u << 12) | (1u << 1));      /* L0_EN | SL_ROD */
 170
 171         PSPR = 0x5c014000;
 172
 173         /* overwrite with the resume address */
 174         *p = virt_to_phys(cpu_resume);
 175
 176         cpu_suspend(0, pxa3xx_finish_suspend);
 177
 178         *p = saved_data;
 179
 180         AD3ER = 0;
 181
 182 #ifndef CONFIG_IWMMXT
 183         asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
 184 #endif
 185 }
 186
 187 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
 188 {
 189         /*
 190          * Don't sleep if no wakeup sources are defined
 191          */
 192         if (wakeup_src == 0) {
 193                 printk(KERN_ERR "Not suspending: no wakeup sources\n");
 194                 return;
 195         }
 196
 197         switch (state) {
 198         case PM_SUSPEND_STANDBY:
 199                 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
 200                 break;
 201
 202         case PM_SUSPEND_MEM:
 203                 pxa3xx_cpu_pm_suspend();
 204                 break;
 205         }
 206 }
 207
 208 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
 209 {
 210         return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
 211 }
 212
 213 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
 214         .valid          = pxa3xx_cpu_pm_valid,
 215         .enter          = pxa3xx_cpu_pm_enter,
 216 };
 217
 218 static void __init pxa3xx_init_pm(void)
 219 {
 220         sram = ioremap(ISRAM_START, ISRAM_SIZE);
 221         if (!sram) {
 222                 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
 223                 return;
 224         }
 225
 226         /*
 227          * Since we copy wakeup code into the SRAM, we need to ensure
 228          * that it is preserved over the low power modes.  Note: bit 8
 229          * is undocumented in the developer manual, but must be set.
 230          */
 231         AD1R |= ADXR_L2 | ADXR_R0;
 232         AD2R |= ADXR_L2 | ADXR_R0;
 233         AD3R |= ADXR_L2 | ADXR_R0;
 234
 235         /*
 236          * Clear the resume enable registers.
 237          */
 238         AD1D0ER = 0;
 239         AD2D0ER = 0;
 240         AD2D1ER = 0;
 241         AD3ER = 0;
 242
 243         pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
 244 }
 245
 246 static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
 247 {
 248         unsigned long flags, mask = 0;
 249
 250         switch (d->irq) {
 251         case IRQ_SSP3:
 252                 mask = ADXER_MFP_WSSP3;
 253                 break;
 254         case IRQ_MSL:
 255                 mask = ADXER_WMSL0;
 256                 break;
 257         case IRQ_USBH2:
 258         case IRQ_USBH1:
 259                 mask = ADXER_WUSBH;
 260                 break;
 261         case IRQ_KEYPAD:
 262                 mask = ADXER_WKP;
 263                 break;
 264         case IRQ_AC97:
 265                 mask = ADXER_MFP_WAC97;
 266                 break;
 267         case IRQ_USIM:
 268                 mask = ADXER_WUSIM0;
 269                 break;
 270         case IRQ_SSP2:
 271                 mask = ADXER_MFP_WSSP2;
 272                 break;
 273         case IRQ_I2C:
 274                 mask = ADXER_MFP_WI2C;
 275                 break;
 276         case IRQ_STUART:
 277                 mask = ADXER_MFP_WUART3;
 278                 break;
 279         case IRQ_BTUART:
 280                 mask = ADXER_MFP_WUART2;
 281                 break;
 282         case IRQ_FFUART:
 283                 mask = ADXER_MFP_WUART1;
 284                 break;
 285         case IRQ_MMC:
 286                 mask = ADXER_MFP_WMMC1;
 287                 break;
 288         case IRQ_SSP:
 289                 mask = ADXER_MFP_WSSP1;
 290                 break;
 291         case IRQ_RTCAlrm:
 292                 mask = ADXER_WRTC;
 293                 break;
 294         case IRQ_SSP4:
 295                 mask = ADXER_MFP_WSSP4;
 296                 break;
 297         case IRQ_TSI:
 298                 mask = ADXER_WTSI;
 299                 break;
 300         case IRQ_USIM2:
 301                 mask = ADXER_WUSIM1;
 302                 break;
 303         case IRQ_MMC2:
 304                 mask = ADXER_MFP_WMMC2;
 305                 break;
 306         case IRQ_NAND:
 307                 mask = ADXER_MFP_WFLASH;
 308                 break;
 309         case IRQ_USB2:
 310                 mask = ADXER_WUSB2;
 311                 break;
 312         case IRQ_WAKEUP0:
 313                 mask = ADXER_WEXTWAKE0;
 314                 break;
 315         case IRQ_WAKEUP1:
 316                 mask = ADXER_WEXTWAKE1;
 317                 break;
 318         case IRQ_MMC3:
 319                 mask = ADXER_MFP_GEN12;
 320                 break;
 321         default:
 322                 return -EINVAL;
 323         }
 324
 325         local_irq_save(flags);
 326         if (on)
 327                 wakeup_src |= mask;
 328         else
 329                 wakeup_src &= ~mask;
 330         local_irq_restore(flags);
 331
 332         return 0;
 333 }
 334 #else
 335 static inline void pxa3xx_init_pm(void) {}
 336 #define pxa3xx_set_wake NULL
 337 #endif
 338
 339 static void pxa_ack_ext_wakeup(struct irq_data *d)
 340 {
 341         PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
 342 }
 343
 344 static void pxa_mask_ext_wakeup(struct irq_data *d)
 345 {
 346         pxa_mask_irq(d);
 347         PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
 348 }
 349
 350 static void pxa_unmask_ext_wakeup(struct irq_data *d)
 351 {
 352         pxa_unmask_irq(d);
 353         PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
 354 }
 355
 356 static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
 357 {
 358         if (flow_type & IRQ_TYPE_EDGE_RISING)
 359                 PWER |= 1 << (d->irq - IRQ_WAKEUP0);
 360
 361         if (flow_type & IRQ_TYPE_EDGE_FALLING)
 362                 PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);
 363
 364         return 0;
 365 }
 366
 367 static struct irq_chip pxa_ext_wakeup_chip = {
 368         .name           = "WAKEUP",
 369         .irq_ack        = pxa_ack_ext_wakeup,
 370         .irq_mask       = pxa_mask_ext_wakeup,
 371         .irq_unmask     = pxa_unmask_ext_wakeup,
 372         .irq_set_type   = pxa_set_ext_wakeup_type,
 373 };
 374
 375 static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
 376                                            unsigned int))
 377 {
 378         int irq;
 379
 380         for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
 381                 irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
 382                                          handle_edge_irq);
 383                 set_irq_flags(irq, IRQF_VALID);
 384         }
 385
 386         pxa_ext_wakeup_chip.irq_set_wake = fn;
 387 }
 388
 389 static void __init __pxa3xx_init_irq(void)
 390 {
 391         /* enable CP6 access */
 392         u32 value;
 393         __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
 394         value |= (1 << 6);
 395         __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
 396
 397         pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
 398 }
 399
 400 void __init pxa3xx_init_irq(void)
 401 {
 402         __pxa3xx_init_irq();
 403         pxa_init_irq(56, pxa3xx_set_wake);
 404 }
 405
 406 #ifdef CONFIG_OF
 407 void __init pxa3xx_dt_init_irq(void)
 408 {
 409         __pxa3xx_init_irq();
 410         pxa_dt_irq_init(pxa3xx_set_wake);
 411 }
 412 #endif  /* CONFIG_OF */
 413
 414 static struct map_desc pxa3xx_io_desc[] __initdata = {
 415         {       /* Mem Ctl */
 416                 .virtual        = (unsigned long)SMEMC_VIRT,
 417                 .pfn            = __phys_to_pfn(PXA3XX_SMEMC_BASE),
 418                 .length         = 0x00200000,
 419                 .type           = MT_DEVICE
 420         }
 421 };
 422
 423 void __init pxa3xx_map_io(void)
 424 {
 425         pxa_map_io();
 426         iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
 427         pxa3xx_get_clk_frequency_khz(1);
 428 }
 429
 430 /*
 431  * device registration specific to PXA3xx.
 432  */
 433
 434 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 435 {
 436         pxa_register_device(&pxa3xx_device_i2c_power, info);
 437 }
 438
 439 static struct platform_device *devices[] __initdata = {
 440         &pxa27x_device_udc,
 441         &pxa_device_pmu,
 442         &pxa_device_i2s,
 443         &pxa_device_asoc_ssp1,
 444         &pxa_device_asoc_ssp2,
 445         &pxa_device_asoc_ssp3,
 446         &pxa_device_asoc_ssp4,
 447         &pxa_device_asoc_platform,
 448         &sa1100_device_rtc,
 449         &pxa_device_rtc,
 450         &pxa27x_device_ssp1,
 451         &pxa27x_device_ssp2,
 452         &pxa27x_device_ssp3,
 453         &pxa3xx_device_ssp4,
 454         &pxa27x_device_pwm0,
 455         &pxa27x_device_pwm1,
 456 };
 457
 458 static int __init pxa3xx_init(void)
 459 {
 460         int ret = 0;
 461
 462         if (cpu_is_pxa3xx()) {
 463
 464                 reset_status = ARSR;
 465
 466                 /*
 467                  * clear RDH bit every time after reset
 468                  *
 469                  * Note: the last 3 bits DxS are write-1-to-clear so carefully
 470                  * preserve them here in case they will be referenced later
 471                  */
 472                 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
 473
 474                 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
 475
 476                 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
 477                         return ret;
 478
 479                 pxa3xx_init_pm();
 480
 481                 register_syscore_ops(&pxa_irq_syscore_ops);
 482                 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
 483                 register_syscore_ops(&pxa3xx_clock_syscore_ops);
 484
 485                 if (of_have_populated_dt())
 486                         return 0;
 487
 488                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
 489                 if (ret)
 490                         return ret;
 491                 if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320())
 492                         ret = platform_device_register(&pxa3xx_device_gpio);
 493         }
 494
 495         return ret;
 496 }
 497
 498 postcore_initcall(pxa3xx_init);