arch/arm/mach-pxa/pxa3xx.c

   1 /*
   2  * linux/arch/arm/mach-pxa/pxa3xx.c
   3  *
   4  * code specific to pxa3xx aka Monahans
   5  *
   6  * Copyright (C) 2006 Marvell International Ltd.
   7  *
   8  * 2007-09-02: eric miao <eric.miao@marvell.com>
   9  *             initial version
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/pm.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23 #include <linux/sysdev.h>
  24
  25 #include <mach/hardware.h>
  26 #include <mach/pxa3xx-regs.h>
  27 #include <mach/reset.h>
  28 #include <mach/ohci.h>
  29 #include <mach/pm.h>
  30 #include <mach/dma.h>
  31 #include <mach/ssp.h>
  32 #include <mach/i2c.h>
  33
  34 #include "generic.h"
  35 #include "devices.h"
  36 #include "clock.h"
  37
  38 /* Crystal clock: 13MHz */
  39 #define BASE_CLK        13000000
  40
  41 /* Ring Oscillator Clock: 60MHz */
  42 #define RO_CLK          60000000
  43
  44 #define ACCR_D0CS       (1 << 26)
  45 #define ACCR_PCCE       (1 << 11)
  46
  47 /* crystal frequency to static memory controller multiplier (SMCFS) */
  48 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
  49
  50 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
  51 static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
  52
  53 /*
  54  * Get the clock frequency as reflected by CCSR and the turbo flag.
  55  * We assume these values have been applied via a fcs.
  56  * If info is not 0 we also display the current settings.
  57  */
  58 unsigned int pxa3xx_get_clk_frequency_khz(int info)
  59 {
  60         unsigned long acsr, xclkcfg;
  61         unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
  62
  63         /* Read XCLKCFG register turbo bit */
  64         __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
  65         t = xclkcfg & 0x1;
  66
  67         acsr = ACSR;
  68
  69         xl  = acsr & 0x1f;
  70         xn  = (acsr >> 8) & 0x7;
  71         hss = (acsr >> 14) & 0x3;
  72
  73         XL = xl * BASE_CLK;
  74         XN = xn * XL;
  75
  76         ro = acsr & ACCR_D0CS;
  77
  78         CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
  79         HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
  80
  81         if (info) {
  82                 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
  83                         RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
  84                         (ro) ? "" : "in");
  85                 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
  86                         XL / 1000000, (XL % 1000000) / 10000, xl);
  87                 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
  88                         XN / 1000000, (XN % 1000000) / 10000, xn,
  89                         (t) ? "" : "in");
  90                 pr_info("HSIO bus clock: %d.%02dMHz\n",
  91                         HSS / 1000000, (HSS % 1000000) / 10000);
  92         }
  93
  94         return CLK / 1000;
  95 }
  96
  97 /*
  98  * Return the current static memory controller clock frequency
  99  * in units of 10kHz
 100  */
 101 unsigned int pxa3xx_get_memclk_frequency_10khz(void)
 102 {
 103         unsigned long acsr;
 104         unsigned int smcfs, clk = 0;
 105
 106         acsr = ACSR;
 107
 108         smcfs = (acsr >> 23) & 0x7;
 109         clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
 110
 111         return (clk / 10000);
 112 }
 113
 114 void pxa3xx_clear_reset_status(unsigned int mask)
 115 {
 116         /* RESET_STATUS_* has a 1:1 mapping with ARSR */
 117         ARSR = mask;
 118 }
 119
 120 /*
 121  * Return the current AC97 clock frequency.
 122  */
 123 static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
 124 {
 125         unsigned long rate = 312000000;
 126         unsigned long ac97_div;
 127
 128         ac97_div = AC97_DIV;
 129
 130         /* This may loose precision for some rates but won't for the
 131          * standard 24.576MHz.
 132          */
 133         rate /= (ac97_div >> 12) & 0x7fff;
 134         rate *= (ac97_div & 0xfff);
 135
 136         return rate;
 137 }
 138
 139 /*
 140  * Return the current HSIO bus clock frequency
 141  */
 142 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
 143 {
 144         unsigned long acsr;
 145         unsigned int hss, hsio_clk;
 146
 147         acsr = ACSR;
 148
 149         hss = (acsr >> 14) & 0x3;
 150         hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
 151
 152         return hsio_clk;
 153 }
 154
 155 void clk_pxa3xx_cken_enable(struct clk *clk)
 156 {
 157         unsigned long mask = 1ul << (clk->cken & 0x1f);
 158
 159         if (clk->cken < 32)
 160                 CKENA |= mask;
 161         else
 162                 CKENB |= mask;
 163 }
 164
 165 void clk_pxa3xx_cken_disable(struct clk *clk)
 166 {
 167         unsigned long mask = 1ul << (clk->cken & 0x1f);
 168
 169         if (clk->cken < 32)
 170                 CKENA &= ~mask;
 171         else
 172                 CKENB &= ~mask;
 173 }
 174
 175 const struct clkops clk_pxa3xx_cken_ops = {
 176         .enable         = clk_pxa3xx_cken_enable,
 177         .disable        = clk_pxa3xx_cken_disable,
 178 };
 179
 180 static const struct clkops clk_pxa3xx_hsio_ops = {
 181         .enable         = clk_pxa3xx_cken_enable,
 182         .disable        = clk_pxa3xx_cken_disable,
 183         .getrate        = clk_pxa3xx_hsio_getrate,
 184 };
 185
 186 static const struct clkops clk_pxa3xx_ac97_ops = {
 187         .enable         = clk_pxa3xx_cken_enable,
 188         .disable        = clk_pxa3xx_cken_disable,
 189         .getrate        = clk_pxa3xx_ac97_getrate,
 190 };
 191
 192 static void clk_pout_enable(struct clk *clk)
 193 {
 194         OSCC |= OSCC_PEN;
 195 }
 196
 197 static void clk_pout_disable(struct clk *clk)
 198 {
 199         OSCC &= ~OSCC_PEN;
 200 }
 201
 202 static const struct clkops clk_pout_ops = {
 203         .enable         = clk_pout_enable,
 204         .disable        = clk_pout_disable,
 205 };
 206
 207 static void clk_dummy_enable(struct clk *clk)
 208 {
 209 }
 210
 211 static void clk_dummy_disable(struct clk *clk)
 212 {
 213 }
 214
 215 static const struct clkops clk_dummy_ops = {
 216         .enable         = clk_dummy_enable,
 217         .disable        = clk_dummy_disable,
 218 };
 219
 220 static struct clk pxa3xx_clks[] = {
 221         {
 222                 .name           = "CLK_POUT",
 223                 .ops            = &clk_pout_ops,
 224                 .rate           = 13000000,
 225                 .delay          = 70,
 226         },
 227
 228         /* Power I2C clock is always on */
 229         {
 230                 .name           = "I2CCLK",
 231                 .ops            = &clk_dummy_ops,
 232                 .dev            = &pxa3xx_device_i2c_power.dev,
 233         },
 234
 235         PXA3xx_CK("LCDCLK",  LCD,    &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
 236         PXA3xx_CK("CAMCLK",  CAMERA, &clk_pxa3xx_hsio_ops, NULL),
 237         PXA3xx_CK("AC97CLK", AC97,   &clk_pxa3xx_ac97_ops, NULL),
 238
 239         PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
 240         PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
 241         PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
 242
 243         PXA3xx_CKEN("I2CCLK", I2C,  32842000, 0, &pxa_device_i2c.dev),
 244         PXA3xx_CKEN("UDCCLK", UDC,  48000000, 5, &pxa27x_device_udc.dev),
 245         PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
 246         PXA3xx_CKEN("KBDCLK", KEYPAD,  32768, 0, &pxa27x_device_keypad.dev),
 247
 248         PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
 249         PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
 250         PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
 251         PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
 252         PXA3xx_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev),
 253         PXA3xx_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev),
 254
 255         PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
 256         PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
 257 };
 258
 259 #ifdef CONFIG_PM
 260
 261 #define ISRAM_START     0x5c000000
 262 #define ISRAM_SIZE      SZ_256K
 263
 264 static void __iomem *sram;
 265 static unsigned long wakeup_src;
 266
 267 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
 268 #define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
 269
 270 enum {  SLEEP_SAVE_CKENA,
 271         SLEEP_SAVE_CKENB,
 272         SLEEP_SAVE_ACCR,
 273
 274         SLEEP_SAVE_COUNT,
 275 };
 276
 277 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
 278 {
 279         SAVE(CKENA);
 280         SAVE(CKENB);
 281         SAVE(ACCR);
 282 }
 283
 284 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
 285 {
 286         RESTORE(ACCR);
 287         RESTORE(CKENA);
 288         RESTORE(CKENB);
 289 }
 290
 291 /*
 292  * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
 293  * memory controller has to be reinitialised, so we place some code
 294  * in the SRAM to perform this function.
 295  *
 296  * We disable FIQs across the standby - otherwise, we might receive a
 297  * FIQ while the SDRAM is unavailable.
 298  */
 299 static void pxa3xx_cpu_standby(unsigned int pwrmode)
 300 {
 301         extern const char pm_enter_standby_start[], pm_enter_standby_end[];
 302         void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
 303
 304         memcpy_toio(sram + 0x8000, pm_enter_standby_start,
 305                     pm_enter_standby_end - pm_enter_standby_start);
 306
 307         AD2D0SR = ~0;
 308         AD2D1SR = ~0;
 309         AD2D0ER = wakeup_src;
 310         AD2D1ER = 0;
 311         ASCR = ASCR;
 312         ARSR = ARSR;
 313
 314         local_fiq_disable();
 315         fn(pwrmode);
 316         local_fiq_enable();
 317
 318         AD2D0ER = 0;
 319         AD2D1ER = 0;
 320 }
 321
 322 /*
 323  * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
 324  * PXA3xx development kits assumes that the resuming process continues
 325  * with the address stored within the first 4 bytes of SDRAM. The PSPR
 326  * register is used privately by BootROM and OBM, and _must_ be set to
 327  * 0x5c014000 for the moment.
 328  */
 329 static void pxa3xx_cpu_pm_suspend(void)
 330 {
 331         volatile unsigned long *p = (volatile void *)0xc0000000;
 332         unsigned long saved_data = *p;
 333
 334         extern void pxa3xx_cpu_suspend(void);
 335         extern void pxa3xx_cpu_resume(void);
 336
 337         /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
 338         CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
 339         CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
 340
 341         /* clear and setup wakeup source */
 342         AD3SR = ~0;
 343         AD3ER = wakeup_src;
 344         ASCR = ASCR;
 345         ARSR = ARSR;
 346
 347         PCFR |= (1u << 13);                     /* L1_DIS */
 348         PCFR &= ~((1u << 12) | (1u << 1));      /* L0_EN | SL_ROD */
 349
 350         PSPR = 0x5c014000;
 351
 352         /* overwrite with the resume address */
 353         *p = virt_to_phys(pxa3xx_cpu_resume);
 354
 355         pxa3xx_cpu_suspend();
 356
 357         *p = saved_data;
 358
 359         AD3ER = 0;
 360 }
 361
 362 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
 363 {
 364         /*
 365          * Don't sleep if no wakeup sources are defined
 366          */
 367         if (wakeup_src == 0) {
 368                 printk(KERN_ERR "Not suspending: no wakeup sources\n");
 369                 return;
 370         }
 371
 372         switch (state) {
 373         case PM_SUSPEND_STANDBY:
 374                 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
 375                 break;
 376
 377         case PM_SUSPEND_MEM:
 378                 pxa3xx_cpu_pm_suspend();
 379                 break;
 380         }
 381 }
 382
 383 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
 384 {
 385         return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
 386 }
 387
 388 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
 389         .save_count     = SLEEP_SAVE_COUNT,
 390         .save           = pxa3xx_cpu_pm_save,
 391         .restore        = pxa3xx_cpu_pm_restore,
 392         .valid          = pxa3xx_cpu_pm_valid,
 393         .enter          = pxa3xx_cpu_pm_enter,
 394 };
 395
 396 static void __init pxa3xx_init_pm(void)
 397 {
 398         sram = ioremap(ISRAM_START, ISRAM_SIZE);
 399         if (!sram) {
 400                 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
 401                 return;
 402         }
 403
 404         /*
 405          * Since we copy wakeup code into the SRAM, we need to ensure
 406          * that it is preserved over the low power modes.  Note: bit 8
 407          * is undocumented in the developer manual, but must be set.
 408          */
 409         AD1R |= ADXR_L2 | ADXR_R0;
 410         AD2R |= ADXR_L2 | ADXR_R0;
 411         AD3R |= ADXR_L2 | ADXR_R0;
 412
 413         /*
 414          * Clear the resume enable registers.
 415          */
 416         AD1D0ER = 0;
 417         AD2D0ER = 0;
 418         AD2D1ER = 0;
 419         AD3ER = 0;
 420
 421         pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
 422 }
 423
 424 static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
 425 {
 426         unsigned long flags, mask = 0;
 427
 428         switch (irq) {
 429         case IRQ_SSP3:
 430                 mask = ADXER_MFP_WSSP3;
 431                 break;
 432         case IRQ_MSL:
 433                 mask = ADXER_WMSL0;
 434                 break;
 435         case IRQ_USBH2:
 436         case IRQ_USBH1:
 437                 mask = ADXER_WUSBH;
 438                 break;
 439         case IRQ_KEYPAD:
 440                 mask = ADXER_WKP;
 441                 break;
 442         case IRQ_AC97:
 443                 mask = ADXER_MFP_WAC97;
 444                 break;
 445         case IRQ_USIM:
 446                 mask = ADXER_WUSIM0;
 447                 break;
 448         case IRQ_SSP2:
 449                 mask = ADXER_MFP_WSSP2;
 450                 break;
 451         case IRQ_I2C:
 452                 mask = ADXER_MFP_WI2C;
 453                 break;
 454         case IRQ_STUART:
 455                 mask = ADXER_MFP_WUART3;
 456                 break;
 457         case IRQ_BTUART:
 458                 mask = ADXER_MFP_WUART2;
 459                 break;
 460         case IRQ_FFUART:
 461                 mask = ADXER_MFP_WUART1;
 462                 break;
 463         case IRQ_MMC:
 464                 mask = ADXER_MFP_WMMC1;
 465                 break;
 466         case IRQ_SSP:
 467                 mask = ADXER_MFP_WSSP1;
 468                 break;
 469         case IRQ_RTCAlrm:
 470                 mask = ADXER_WRTC;
 471                 break;
 472         case IRQ_SSP4:
 473                 mask = ADXER_MFP_WSSP4;
 474                 break;
 475         case IRQ_TSI:
 476                 mask = ADXER_WTSI;
 477                 break;
 478         case IRQ_USIM2:
 479                 mask = ADXER_WUSIM1;
 480                 break;
 481         case IRQ_MMC2:
 482                 mask = ADXER_MFP_WMMC2;
 483                 break;
 484         case IRQ_NAND:
 485                 mask = ADXER_MFP_WFLASH;
 486                 break;
 487         case IRQ_USB2:
 488                 mask = ADXER_WUSB2;
 489                 break;
 490         case IRQ_WAKEUP0:
 491                 mask = ADXER_WEXTWAKE0;
 492                 break;
 493         case IRQ_WAKEUP1:
 494                 mask = ADXER_WEXTWAKE1;
 495                 break;
 496         case IRQ_MMC3:
 497                 mask = ADXER_MFP_GEN12;
 498                 break;
 499         default:
 500                 return -EINVAL;
 501         }
 502
 503         local_irq_save(flags);
 504         if (on)
 505                 wakeup_src |= mask;
 506         else
 507                 wakeup_src &= ~mask;
 508         local_irq_restore(flags);
 509
 510         return 0;
 511 }
 512 #else
 513 static inline void pxa3xx_init_pm(void) {}
 514 #define pxa3xx_set_wake NULL
 515 #endif
 516
 517 void __init pxa3xx_init_irq(void)
 518 {
 519         /* enable CP6 access */
 520         u32 value;
 521         __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
 522         value |= (1 << 6);
 523         __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
 524
 525         pxa_init_irq(56, pxa3xx_set_wake);
 526         pxa_init_gpio(128, NULL);
 527 }
 528
 529 /*
 530  * device registration specific to PXA3xx.
 531  */
 532
 533 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 534 {
 535         pxa_register_device(&pxa3xx_device_i2c_power, info);
 536 }
 537
 538 static struct platform_device *devices[] __initdata = {
 539 /*      &pxa_device_udc,        The UDC driver is PXA25x only */
 540         &pxa_device_ffuart,
 541         &pxa_device_btuart,
 542         &pxa_device_stuart,
 543         &pxa_device_i2s,
 544         &pxa_device_rtc,
 545         &pxa27x_device_ssp1,
 546         &pxa27x_device_ssp2,
 547         &pxa27x_device_ssp3,
 548         &pxa3xx_device_ssp4,
 549         &pxa27x_device_pwm0,
 550         &pxa27x_device_pwm1,
 551 };
 552
 553 static struct sys_device pxa3xx_sysdev[] = {
 554         {
 555                 .cls    = &pxa_irq_sysclass,
 556         }, {
 557                 .cls    = &pxa3xx_mfp_sysclass,
 558         }, {
 559                 .cls    = &pxa_gpio_sysclass,
 560         },
 561 };
 562
 563 static int __init pxa3xx_init(void)
 564 {
 565         int i, ret = 0;
 566
 567         if (cpu_is_pxa3xx()) {
 568
 569                 reset_status = ARSR;
 570
 571                 /*
 572                  * clear RDH bit every time after reset
 573                  *
 574                  * Note: the last 3 bits DxS are write-1-to-clear so carefully
 575                  * preserve them here in case they will be referenced later
 576                  */
 577                 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
 578
 579                 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
 580
 581                 if ((ret = pxa_init_dma(32)))
 582                         return ret;
 583
 584                 pxa3xx_init_pm();
 585
 586                 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
 587                         ret = sysdev_register(&pxa3xx_sysdev[i]);
 588                         if (ret)
 589                                 pr_err("failed to register sysdev[%d]\n", i);
 590                 }
 591
 592                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
 593         }
 594
 595         return ret;
 596 }
 597
 598 postcore_initcall(pxa3xx_init);