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[deliverable/linux.git] / arch / arm / mach-realview / core.c
1 /*
2 * linux/arch/arm/mach-realview/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/device.h>
25 #include <linux/interrupt.h>
26 #include <linux/amba/bus.h>
27 #include <linux/amba/clcd.h>
28 #include <linux/io.h>
29 #include <linux/smsc911x.h>
30 #include <linux/ata_platform.h>
31 #include <linux/amba/mmci.h>
32 #include <linux/gfp.h>
33 #include <linux/clkdev.h>
34 #include <linux/mtd/physmap.h>
35
36 #include <mach/hardware.h>
37 #include <asm/irq.h>
38 #include <asm/mach-types.h>
39 #include <asm/hardware/arm_timer.h>
40 #include <asm/hardware/icst.h>
41
42 #include <asm/mach/arch.h>
43 #include <asm/mach/irq.h>
44 #include <asm/mach/map.h>
45
46 #include <asm/hardware/gic.h>
47
48 #include <mach/platform.h>
49 #include <mach/irqs.h>
50 #include <asm/hardware/timer-sp.h>
51
52 #include <plat/clcd.h>
53 #include <plat/sched_clock.h>
54
55 #include "core.h"
56
57 #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
58
59 static void realview_flash_set_vpp(struct platform_device *pdev, int on)
60 {
61 u32 val;
62
63 val = __raw_readl(REALVIEW_FLASHCTRL);
64 if (on)
65 val |= REALVIEW_FLASHPROG_FLVPPEN;
66 else
67 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
68 __raw_writel(val, REALVIEW_FLASHCTRL);
69 }
70
71 static struct physmap_flash_data realview_flash_data = {
72 .width = 4,
73 .set_vpp = realview_flash_set_vpp,
74 };
75
76 struct platform_device realview_flash_device = {
77 .name = "physmap-flash",
78 .id = 0,
79 .dev = {
80 .platform_data = &realview_flash_data,
81 },
82 };
83
84 int realview_flash_register(struct resource *res, u32 num)
85 {
86 realview_flash_device.resource = res;
87 realview_flash_device.num_resources = num;
88 return platform_device_register(&realview_flash_device);
89 }
90
91 static struct smsc911x_platform_config smsc911x_config = {
92 .flags = SMSC911X_USE_32BIT,
93 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
94 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
95 .phy_interface = PHY_INTERFACE_MODE_MII,
96 };
97
98 static struct platform_device realview_eth_device = {
99 .name = "smsc911x",
100 .id = 0,
101 .num_resources = 2,
102 };
103
104 int realview_eth_register(const char *name, struct resource *res)
105 {
106 if (name)
107 realview_eth_device.name = name;
108 realview_eth_device.resource = res;
109 if (strcmp(realview_eth_device.name, "smsc911x") == 0)
110 realview_eth_device.dev.platform_data = &smsc911x_config;
111
112 return platform_device_register(&realview_eth_device);
113 }
114
115 struct platform_device realview_usb_device = {
116 .name = "isp1760",
117 .num_resources = 2,
118 };
119
120 int realview_usb_register(struct resource *res)
121 {
122 realview_usb_device.resource = res;
123 return platform_device_register(&realview_usb_device);
124 }
125
126 static struct pata_platform_info pata_platform_data = {
127 .ioport_shift = 1,
128 };
129
130 static struct resource pata_resources[] = {
131 [0] = {
132 .start = REALVIEW_CF_BASE,
133 .end = REALVIEW_CF_BASE + 0xff,
134 .flags = IORESOURCE_MEM,
135 },
136 [1] = {
137 .start = REALVIEW_CF_BASE + 0x100,
138 .end = REALVIEW_CF_BASE + SZ_4K - 1,
139 .flags = IORESOURCE_MEM,
140 },
141 };
142
143 struct platform_device realview_cf_device = {
144 .name = "pata_platform",
145 .id = -1,
146 .num_resources = ARRAY_SIZE(pata_resources),
147 .resource = pata_resources,
148 .dev = {
149 .platform_data = &pata_platform_data,
150 },
151 };
152
153 static struct resource realview_i2c_resource = {
154 .start = REALVIEW_I2C_BASE,
155 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
156 .flags = IORESOURCE_MEM,
157 };
158
159 struct platform_device realview_i2c_device = {
160 .name = "versatile-i2c",
161 .id = 0,
162 .num_resources = 1,
163 .resource = &realview_i2c_resource,
164 };
165
166 static struct i2c_board_info realview_i2c_board_info[] = {
167 {
168 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
169 },
170 };
171
172 static int __init realview_i2c_init(void)
173 {
174 return i2c_register_board_info(0, realview_i2c_board_info,
175 ARRAY_SIZE(realview_i2c_board_info));
176 }
177 arch_initcall(realview_i2c_init);
178
179 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
180
181 /*
182 * This is only used if GPIOLIB support is disabled
183 */
184 static unsigned int realview_mmc_status(struct device *dev)
185 {
186 struct amba_device *adev = container_of(dev, struct amba_device, dev);
187 u32 mask;
188
189 if (machine_is_realview_pb1176()) {
190 static bool inserted = false;
191
192 /*
193 * The PB1176 does not have the status register,
194 * assume it is inserted at startup, then invert
195 * for each call so card insertion/removal will
196 * be detected anyway. This will not be called if
197 * GPIO on PL061 is active, which is the proper
198 * way to do this on the PB1176.
199 */
200 inserted = !inserted;
201 return inserted ? 0 : 1;
202 }
203
204 if (adev->res.start == REALVIEW_MMCI0_BASE)
205 mask = 1;
206 else
207 mask = 2;
208
209 return readl(REALVIEW_SYSMCI) & mask;
210 }
211
212 struct mmci_platform_data realview_mmc0_plat_data = {
213 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
214 .status = realview_mmc_status,
215 .gpio_wp = 17,
216 .gpio_cd = 16,
217 .cd_invert = true,
218 };
219
220 struct mmci_platform_data realview_mmc1_plat_data = {
221 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
222 .status = realview_mmc_status,
223 .gpio_wp = 19,
224 .gpio_cd = 18,
225 .cd_invert = true,
226 };
227
228 /*
229 * Clock handling
230 */
231 static const struct icst_params realview_oscvco_params = {
232 .ref = 24000000,
233 .vco_max = ICST307_VCO_MAX,
234 .vco_min = ICST307_VCO_MIN,
235 .vd_min = 4 + 8,
236 .vd_max = 511 + 8,
237 .rd_min = 1 + 2,
238 .rd_max = 127 + 2,
239 .s2div = icst307_s2div,
240 .idx2s = icst307_idx2s,
241 };
242
243 static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
244 {
245 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
246 u32 val;
247
248 val = readl(clk->vcoreg) & ~0x7ffff;
249 val |= vco.v | (vco.r << 9) | (vco.s << 16);
250
251 writel(0xa05f, sys_lock);
252 writel(val, clk->vcoreg);
253 writel(0, sys_lock);
254 }
255
256 static const struct clk_ops oscvco_clk_ops = {
257 .round = icst_clk_round,
258 .set = icst_clk_set,
259 .setvco = realview_oscvco_set,
260 };
261
262 static struct clk oscvco_clk = {
263 .ops = &oscvco_clk_ops,
264 .params = &realview_oscvco_params,
265 };
266
267 /*
268 * These are fixed clocks.
269 */
270 static struct clk ref24_clk = {
271 .rate = 24000000,
272 };
273
274 static struct clk sp804_clk = {
275 .rate = 1000000,
276 };
277
278 static struct clk dummy_apb_pclk;
279
280 static struct clk_lookup lookups[] = {
281 { /* Bus clock */
282 .con_id = "apb_pclk",
283 .clk = &dummy_apb_pclk,
284 }, { /* UART0 */
285 .dev_id = "dev:uart0",
286 .clk = &ref24_clk,
287 }, { /* UART1 */
288 .dev_id = "dev:uart1",
289 .clk = &ref24_clk,
290 }, { /* UART2 */
291 .dev_id = "dev:uart2",
292 .clk = &ref24_clk,
293 }, { /* UART3 */
294 .dev_id = "fpga:uart3",
295 .clk = &ref24_clk,
296 }, { /* UART3 is on the dev chip in PB1176 */
297 .dev_id = "dev:uart3",
298 .clk = &ref24_clk,
299 }, { /* UART4 only exists in PB1176 */
300 .dev_id = "fpga:uart4",
301 .clk = &ref24_clk,
302 }, { /* KMI0 */
303 .dev_id = "fpga:kmi0",
304 .clk = &ref24_clk,
305 }, { /* KMI1 */
306 .dev_id = "fpga:kmi1",
307 .clk = &ref24_clk,
308 }, { /* MMC0 */
309 .dev_id = "fpga:mmc0",
310 .clk = &ref24_clk,
311 }, { /* CLCD is in the PB1176 and EB DevChip */
312 .dev_id = "dev:clcd",
313 .clk = &oscvco_clk,
314 }, { /* PB:CLCD */
315 .dev_id = "issp:clcd",
316 .clk = &oscvco_clk,
317 }, { /* SSP */
318 .dev_id = "dev:ssp0",
319 .clk = &ref24_clk,
320 }, { /* SP804 timers */
321 .dev_id = "sp804",
322 .clk = &sp804_clk,
323 },
324 };
325
326 void __init realview_init_early(void)
327 {
328 void __iomem *sys = __io_address(REALVIEW_SYS_BASE);
329
330 if (machine_is_realview_pb1176())
331 oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC0_OFFSET;
332 else
333 oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC4_OFFSET;
334
335 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
336
337 versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000);
338 }
339
340 /*
341 * CLCD support.
342 */
343 #define SYS_CLCD_NLCDIOON (1 << 2)
344 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
345 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
346 #define SYS_CLCD_ID_MASK (0x1f << 8)
347 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
348 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
349 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
350 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
351 #define SYS_CLCD_ID_VGA (0x1f << 8)
352
353 /*
354 * Disable all display connectors on the interface module.
355 */
356 static void realview_clcd_disable(struct clcd_fb *fb)
357 {
358 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
359 u32 val;
360
361 val = readl(sys_clcd);
362 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
363 writel(val, sys_clcd);
364 }
365
366 /*
367 * Enable the relevant connector on the interface module.
368 */
369 static void realview_clcd_enable(struct clcd_fb *fb)
370 {
371 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
372 u32 val;
373
374 /*
375 * Enable the PSUs
376 */
377 val = readl(sys_clcd);
378 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
379 writel(val, sys_clcd);
380 }
381
382 /*
383 * Detect which LCD panel is connected, and return the appropriate
384 * clcd_panel structure. Note: we do not have any information on
385 * the required timings for the 8.4in panel, so we presently assume
386 * VGA timings.
387 */
388 static int realview_clcd_setup(struct clcd_fb *fb)
389 {
390 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
391 const char *panel_name, *vga_panel_name;
392 unsigned long framesize;
393 u32 val;
394
395 if (machine_is_realview_eb()) {
396 /* VGA, 16bpp */
397 framesize = 640 * 480 * 2;
398 vga_panel_name = "VGA";
399 } else {
400 /* XVGA, 16bpp */
401 framesize = 1024 * 768 * 2;
402 vga_panel_name = "XVGA";
403 }
404
405 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
406 if (val == SYS_CLCD_ID_SANYO_3_8)
407 panel_name = "Sanyo TM38QV67A02A";
408 else if (val == SYS_CLCD_ID_SANYO_2_5)
409 panel_name = "Sanyo QVGA Portrait";
410 else if (val == SYS_CLCD_ID_EPSON_2_2)
411 panel_name = "Epson L2F50113T00";
412 else if (val == SYS_CLCD_ID_VGA)
413 panel_name = vga_panel_name;
414 else {
415 pr_err("CLCD: unknown LCD panel ID 0x%08x, using VGA\n", val);
416 panel_name = vga_panel_name;
417 }
418
419 fb->panel = versatile_clcd_get_panel(panel_name);
420 if (!fb->panel)
421 return -EINVAL;
422
423 return versatile_clcd_setup_dma(fb, framesize);
424 }
425
426 struct clcd_board clcd_plat_data = {
427 .name = "RealView",
428 .caps = CLCD_CAP_ALL,
429 .check = clcdfb_check,
430 .decode = clcdfb_decode,
431 .disable = realview_clcd_disable,
432 .enable = realview_clcd_enable,
433 .setup = realview_clcd_setup,
434 .mmap = versatile_clcd_mmap_dma,
435 .remove = versatile_clcd_remove_dma,
436 };
437
438 /*
439 * Where is the timer (VA)?
440 */
441 void __iomem *timer0_va_base;
442 void __iomem *timer1_va_base;
443 void __iomem *timer2_va_base;
444 void __iomem *timer3_va_base;
445
446 /*
447 * Set up the clock source and clock events devices
448 */
449 void __init realview_timer_init(unsigned int timer_irq)
450 {
451 u32 val;
452
453 /*
454 * set clock frequency:
455 * REALVIEW_REFCLK is 32KHz
456 * REALVIEW_TIMCLK is 1MHz
457 */
458 val = readl(__io_address(REALVIEW_SCTL_BASE));
459 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
460 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
461 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
462 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
463 __io_address(REALVIEW_SCTL_BASE));
464
465 /*
466 * Initialise to a known state (all timers off)
467 */
468 writel(0, timer0_va_base + TIMER_CTRL);
469 writel(0, timer1_va_base + TIMER_CTRL);
470 writel(0, timer2_va_base + TIMER_CTRL);
471 writel(0, timer3_va_base + TIMER_CTRL);
472
473 sp804_clocksource_init(timer3_va_base, "timer3");
474 sp804_clockevents_init(timer0_va_base, timer_irq, "timer0");
475 }
476
477 /*
478 * Setup the memory banks.
479 */
480 void realview_fixup(struct tag *tags, char **from, struct meminfo *meminfo)
481 {
482 /*
483 * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
484 * Half of this is mirrored at 0.
485 */
486 #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
487 meminfo->bank[0].start = 0x70000000;
488 meminfo->bank[0].size = SZ_512M;
489 meminfo->nr_banks = 1;
490 #else
491 meminfo->bank[0].start = 0;
492 meminfo->bank[0].size = SZ_256M;
493 meminfo->nr_banks = 1;
494 #endif
495 }
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