2 * linux/arch/arm/mach-realview/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/amba/bus.h>
27 #include <linux/amba/clcd.h>
28 #include <linux/clocksource.h>
30 #include <asm/system.h>
31 #include <asm/hardware.h>
35 #include <asm/hardware/arm_timer.h>
36 #include <asm/hardware/icst307.h>
38 #include <asm/mach/arch.h>
39 #include <asm/mach/flash.h>
40 #include <asm/mach/irq.h>
41 #include <asm/mach/time.h>
42 #include <asm/mach/map.h>
43 #include <asm/mach/mmc.h>
45 #include <asm/hardware/gic.h>
50 #define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
53 * This is the RealView sched_clock implementation. This has
54 * a resolution of 41.7ns, and a maximum value of about 179s.
56 unsigned long long sched_clock(void)
60 v
= (unsigned long long)readl(REALVIEW_REFCOUNTER
) * 125;
67 #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
69 static int realview_flash_init(void)
73 val
= __raw_readl(REALVIEW_FLASHCTRL
);
74 val
&= ~REALVIEW_FLASHPROG_FLVPPEN
;
75 __raw_writel(val
, REALVIEW_FLASHCTRL
);
80 static void realview_flash_exit(void)
84 val
= __raw_readl(REALVIEW_FLASHCTRL
);
85 val
&= ~REALVIEW_FLASHPROG_FLVPPEN
;
86 __raw_writel(val
, REALVIEW_FLASHCTRL
);
89 static void realview_flash_set_vpp(int on
)
93 val
= __raw_readl(REALVIEW_FLASHCTRL
);
95 val
|= REALVIEW_FLASHPROG_FLVPPEN
;
97 val
&= ~REALVIEW_FLASHPROG_FLVPPEN
;
98 __raw_writel(val
, REALVIEW_FLASHCTRL
);
101 static struct flash_platform_data realview_flash_data
= {
102 .map_name
= "cfi_probe",
104 .init
= realview_flash_init
,
105 .exit
= realview_flash_exit
,
106 .set_vpp
= realview_flash_set_vpp
,
109 static struct resource realview_flash_resource
= {
110 .start
= REALVIEW_FLASH_BASE
,
111 .end
= REALVIEW_FLASH_BASE
+ REALVIEW_FLASH_SIZE
,
112 .flags
= IORESOURCE_MEM
,
115 struct platform_device realview_flash_device
= {
119 .platform_data
= &realview_flash_data
,
122 .resource
= &realview_flash_resource
,
125 static struct resource realview_smc91x_resources
[] = {
127 .start
= REALVIEW_ETH_BASE
,
128 .end
= REALVIEW_ETH_BASE
+ SZ_64K
- 1,
129 .flags
= IORESOURCE_MEM
,
134 .flags
= IORESOURCE_IRQ
,
138 struct platform_device realview_smc91x_device
= {
141 .num_resources
= ARRAY_SIZE(realview_smc91x_resources
),
142 .resource
= realview_smc91x_resources
,
145 static struct resource realview_i2c_resource
= {
146 .start
= REALVIEW_I2C_BASE
,
147 .end
= REALVIEW_I2C_BASE
+ SZ_4K
- 1,
148 .flags
= IORESOURCE_MEM
,
151 struct platform_device realview_i2c_device
= {
152 .name
= "versatile-i2c",
155 .resource
= &realview_i2c_resource
,
158 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
160 static unsigned int realview_mmc_status(struct device
*dev
)
162 struct amba_device
*adev
= container_of(dev
, struct amba_device
, dev
);
165 if (adev
->res
.start
== REALVIEW_MMCI0_BASE
)
170 return readl(REALVIEW_SYSMCI
) & mask
;
173 struct mmc_platform_data realview_mmc0_plat_data
= {
174 .ocr_mask
= MMC_VDD_32_33
|MMC_VDD_33_34
,
175 .status
= realview_mmc_status
,
178 struct mmc_platform_data realview_mmc1_plat_data
= {
179 .ocr_mask
= MMC_VDD_32_33
|MMC_VDD_33_34
,
180 .status
= realview_mmc_status
,
186 static const struct icst307_params realview_oscvco_params
= {
195 static void realview_oscvco_set(struct clk
*clk
, struct icst307_vco vco
)
197 void __iomem
*sys_lock
= __io_address(REALVIEW_SYS_BASE
) + REALVIEW_SYS_LOCK_OFFSET
;
198 void __iomem
*sys_osc
= __io_address(REALVIEW_SYS_BASE
) + REALVIEW_SYS_OSC4_OFFSET
;
201 val
= readl(sys_osc
) & ~0x7ffff;
202 val
|= vco
.v
| (vco
.r
<< 9) | (vco
.s
<< 16);
204 writel(0xa05f, sys_lock
);
205 writel(val
, sys_osc
);
209 struct clk realview_clcd_clk
= {
211 .params
= &realview_oscvco_params
,
212 .setvco
= realview_oscvco_set
,
218 #define SYS_CLCD_NLCDIOON (1 << 2)
219 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
220 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
221 #define SYS_CLCD_ID_MASK (0x1f << 8)
222 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
223 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
224 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
225 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
226 #define SYS_CLCD_ID_VGA (0x1f << 8)
228 static struct clcd_panel vga
= {
242 .vmode
= FB_VMODE_NONINTERLACED
,
246 .tim2
= TIM2_BCD
| TIM2_IPC
,
247 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
251 static struct clcd_panel sanyo_3_8_in
= {
253 .name
= "Sanyo QVGA",
265 .vmode
= FB_VMODE_NONINTERLACED
,
270 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
274 static struct clcd_panel sanyo_2_5_in
= {
276 .name
= "Sanyo QVGA Portrait",
287 .sync
= FB_SYNC_HOR_HIGH_ACT
| FB_SYNC_VERT_HIGH_ACT
,
288 .vmode
= FB_VMODE_NONINTERLACED
,
292 .tim2
= TIM2_IVS
| TIM2_IHS
| TIM2_IPC
,
293 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
297 static struct clcd_panel epson_2_2_in
= {
299 .name
= "Epson QCIF",
311 .vmode
= FB_VMODE_NONINTERLACED
,
315 .tim2
= TIM2_BCD
| TIM2_IPC
,
316 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
321 * Detect which LCD panel is connected, and return the appropriate
322 * clcd_panel structure. Note: we do not have any information on
323 * the required timings for the 8.4in panel, so we presently assume
326 static struct clcd_panel
*realview_clcd_panel(void)
328 void __iomem
*sys_clcd
= __io_address(REALVIEW_SYS_BASE
) + REALVIEW_SYS_CLCD_OFFSET
;
329 struct clcd_panel
*panel
= &vga
;
332 val
= readl(sys_clcd
) & SYS_CLCD_ID_MASK
;
333 if (val
== SYS_CLCD_ID_SANYO_3_8
)
334 panel
= &sanyo_3_8_in
;
335 else if (val
== SYS_CLCD_ID_SANYO_2_5
)
336 panel
= &sanyo_2_5_in
;
337 else if (val
== SYS_CLCD_ID_EPSON_2_2
)
338 panel
= &epson_2_2_in
;
339 else if (val
== SYS_CLCD_ID_VGA
)
342 printk(KERN_ERR
"CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
351 * Disable all display connectors on the interface module.
353 static void realview_clcd_disable(struct clcd_fb
*fb
)
355 void __iomem
*sys_clcd
= __io_address(REALVIEW_SYS_BASE
) + REALVIEW_SYS_CLCD_OFFSET
;
358 val
= readl(sys_clcd
);
359 val
&= ~SYS_CLCD_NLCDIOON
| SYS_CLCD_PWR3V5SWITCH
;
360 writel(val
, sys_clcd
);
364 * Enable the relevant connector on the interface module.
366 static void realview_clcd_enable(struct clcd_fb
*fb
)
368 void __iomem
*sys_clcd
= __io_address(REALVIEW_SYS_BASE
) + REALVIEW_SYS_CLCD_OFFSET
;
374 val
= readl(sys_clcd
);
375 val
|= SYS_CLCD_NLCDIOON
| SYS_CLCD_PWR3V5SWITCH
;
376 writel(val
, sys_clcd
);
379 static unsigned long framesize
= SZ_1M
;
381 static int realview_clcd_setup(struct clcd_fb
*fb
)
385 fb
->panel
= realview_clcd_panel();
387 fb
->fb
.screen_base
= dma_alloc_writecombine(&fb
->dev
->dev
, framesize
,
389 if (!fb
->fb
.screen_base
) {
390 printk(KERN_ERR
"CLCD: unable to map framebuffer\n");
394 fb
->fb
.fix
.smem_start
= dma
;
395 fb
->fb
.fix
.smem_len
= framesize
;
400 static int realview_clcd_mmap(struct clcd_fb
*fb
, struct vm_area_struct
*vma
)
402 return dma_mmap_writecombine(&fb
->dev
->dev
, vma
,
404 fb
->fb
.fix
.smem_start
,
405 fb
->fb
.fix
.smem_len
);
408 static void realview_clcd_remove(struct clcd_fb
*fb
)
410 dma_free_writecombine(&fb
->dev
->dev
, fb
->fb
.fix
.smem_len
,
411 fb
->fb
.screen_base
, fb
->fb
.fix
.smem_start
);
414 struct clcd_board clcd_plat_data
= {
416 .check
= clcdfb_check
,
417 .decode
= clcdfb_decode
,
418 .disable
= realview_clcd_disable
,
419 .enable
= realview_clcd_enable
,
420 .setup
= realview_clcd_setup
,
421 .mmap
= realview_clcd_mmap
,
422 .remove
= realview_clcd_remove
,
426 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
428 void realview_leds_event(led_event_t ledevt
)
433 local_irq_save(flags
);
434 val
= readl(VA_LEDS_BASE
);
438 val
= val
& ~REALVIEW_SYS_LED0
;
442 val
= val
| REALVIEW_SYS_LED0
;
446 val
= val
^ REALVIEW_SYS_LED1
;
457 writel(val
, VA_LEDS_BASE
);
458 local_irq_restore(flags
);
460 #endif /* CONFIG_LEDS */
463 * Where is the timer (VA)?
465 #define TIMER0_VA_BASE __io_address(REALVIEW_TIMER0_1_BASE)
466 #define TIMER1_VA_BASE (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20)
467 #define TIMER2_VA_BASE __io_address(REALVIEW_TIMER2_3_BASE)
468 #define TIMER3_VA_BASE (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20)
471 * How long is the timer interval?
473 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
474 #if TIMER_INTERVAL >= 0x100000
475 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
476 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
477 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
478 #elif TIMER_INTERVAL >= 0x10000
479 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
480 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
481 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
483 #define TIMER_RELOAD (TIMER_INTERVAL)
484 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
485 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
489 * IRQ handler for the timer
491 static irqreturn_t
realview_timer_interrupt(int irq
, void *dev_id
)
493 // ...clear the interrupt
494 writel(1, TIMER0_VA_BASE
+ TIMER_INTCLR
);
498 #if defined(CONFIG_SMP) && !defined(CONFIG_LOCAL_TIMERS)
500 update_process_times(user_mode(get_irq_regs()));
506 static struct irqaction realview_timer_irq
= {
507 .name
= "RealView Timer Tick",
508 .flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
,
509 .handler
= realview_timer_interrupt
,
512 static cycle_t
realview_get_cycles(void)
514 return ~readl(TIMER3_VA_BASE
+ TIMER_VALUE
);
517 static struct clocksource clocksource_realview
= {
520 .read
= realview_get_cycles
,
521 .mask
= CLOCKSOURCE_MASK(32),
523 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
526 static void __init
realview_clocksource_init(void)
528 /* setup timer 0 as free-running clocksource */
529 writel(0, TIMER3_VA_BASE
+ TIMER_CTRL
);
530 writel(0xffffffff, TIMER3_VA_BASE
+ TIMER_LOAD
);
531 writel(0xffffffff, TIMER3_VA_BASE
+ TIMER_VALUE
);
532 writel(TIMER_CTRL_32BIT
| TIMER_CTRL_ENABLE
| TIMER_CTRL_PERIODIC
,
533 TIMER3_VA_BASE
+ TIMER_CTRL
);
535 clocksource_realview
.mult
=
536 clocksource_khz2mult(1000, clocksource_realview
.shift
);
537 clocksource_register(&clocksource_realview
);
541 * Set up timer interrupt, and return the current time in seconds.
543 static void __init
realview_timer_init(void)
548 * set clock frequency:
549 * REALVIEW_REFCLK is 32KHz
550 * REALVIEW_TIMCLK is 1MHz
552 val
= readl(__io_address(REALVIEW_SCTL_BASE
));
553 writel((REALVIEW_TIMCLK
<< REALVIEW_TIMER1_EnSel
) |
554 (REALVIEW_TIMCLK
<< REALVIEW_TIMER2_EnSel
) |
555 (REALVIEW_TIMCLK
<< REALVIEW_TIMER3_EnSel
) |
556 (REALVIEW_TIMCLK
<< REALVIEW_TIMER4_EnSel
) | val
,
557 __io_address(REALVIEW_SCTL_BASE
));
560 * Initialise to a known state (all timers off)
562 writel(0, TIMER0_VA_BASE
+ TIMER_CTRL
);
563 writel(0, TIMER1_VA_BASE
+ TIMER_CTRL
);
564 writel(0, TIMER2_VA_BASE
+ TIMER_CTRL
);
565 writel(0, TIMER3_VA_BASE
+ TIMER_CTRL
);
567 writel(TIMER_RELOAD
, TIMER0_VA_BASE
+ TIMER_LOAD
);
568 writel(TIMER_RELOAD
, TIMER0_VA_BASE
+ TIMER_VALUE
);
569 writel(TIMER_DIVISOR
| TIMER_CTRL_ENABLE
| TIMER_CTRL_PERIODIC
|
570 TIMER_CTRL_IE
, TIMER0_VA_BASE
+ TIMER_CTRL
);
573 * Make irqs happen for the system timer
575 setup_irq(IRQ_TIMERINT0_1
, &realview_timer_irq
);
577 realview_clocksource_init();
580 struct sys_timer realview_timer
= {
581 .init
= realview_timer_init
,