2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/delay.h>
17 #include <linux/init.h>
18 #include <linux/smp.h>
21 #include <linux/of_address.h>
22 #include <linux/regmap.h>
23 #include <linux/mfd/syscon.h>
25 #include <linux/reset.h>
26 #include <linux/cpu.h>
27 #include <asm/cacheflush.h>
29 #include <asm/smp_scu.h>
30 #include <asm/smp_plat.h>
31 #include <asm/mach/map.h>
35 static void __iomem
*scu_base_addr
;
36 static void __iomem
*sram_base_addr
;
39 #define PMU_PWRDN_CON 0x08
40 #define PMU_PWRDN_ST 0x0c
42 #define PMU_PWRDN_SCU 4
44 static struct regmap
*pmu
;
46 static int pmu_power_domain_is_on(int pd
)
51 ret
= regmap_read(pmu
, PMU_PWRDN_ST
, &val
);
55 return !(val
& BIT(pd
));
58 static struct reset_control
*rockchip_get_core_reset(int cpu
)
60 struct device
*dev
= get_cpu_device(cpu
);
61 struct device_node
*np
;
63 /* The cpu device is only available after the initial core bringup */
67 np
= of_get_cpu_node(cpu
, 0);
69 return of_reset_control_get(np
, NULL
);
72 static int pmu_set_power_domain(int pd
, bool on
)
74 u32 val
= (on
) ? 0 : BIT(pd
);
75 struct reset_control
*rstc
= rockchip_get_core_reset(pd
);
78 if (IS_ERR(rstc
) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9
) {
79 pr_err("%s: could not get reset control for core %d\n",
85 * We need to soft reset the cpu when we turn off the cpu power domain,
86 * or else the active processors might be stalled when the individual
87 * processor is powered down.
89 if (!IS_ERR(rstc
) && !on
)
90 reset_control_assert(rstc
);
92 ret
= regmap_update_bits(pmu
, PMU_PWRDN_CON
, BIT(pd
), val
);
94 pr_err("%s: could not update power domain\n", __func__
);
100 ret
= pmu_power_domain_is_on(pd
);
102 pr_err("%s: could not read power domain state\n",
110 reset_control_deassert(rstc
);
111 reset_control_put(rstc
);
118 * Handling of CPU cores
121 static int rockchip_boot_secondary(unsigned int cpu
, struct task_struct
*idle
)
125 if (!sram_base_addr
|| !pmu
) {
126 pr_err("%s: sram or pmu missing for cpu boot\n", __func__
);
131 pr_err("%s: cpu %d outside maximum number of cpus %d\n",
132 __func__
, cpu
, ncores
);
137 ret
= pmu_set_power_domain(0 + cpu
, true);
141 if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9
) {
143 * We communicate with the bootrom to active the cpus other
144 * than cpu0, after a blob of initialize code, they will
145 * stay at wfe state, once they are actived, they will check
147 * sram_base_addr + 4: 0xdeadbeaf
148 * sram_base_addr + 8: start address for pc
149 * The cpu0 need to wait the other cpus other than cpu0 entering
150 * the wfe state.The wait time is affected by many aspects.
151 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...)
153 mdelay(1); /* ensure the cpus other than cpu0 to startup */
155 writel(virt_to_phys(rockchip_secondary_startup
),
157 writel(0xDEADBEAF, sram_base_addr
+ 4);
165 * rockchip_smp_prepare_sram - populate necessary sram block
166 * Starting cores execute the code residing at the start of the on-chip sram
167 * after power-on. Therefore make sure, this sram region is reserved and
168 * big enough. After this check, copy the trampoline code that directs the
169 * core to the real startup code in ram into the sram-region.
170 * @node: mmio-sram device node
172 static int __init
rockchip_smp_prepare_sram(struct device_node
*node
)
174 unsigned int trampoline_sz
= &rockchip_secondary_trampoline_end
-
175 &rockchip_secondary_trampoline
;
180 ret
= of_address_to_resource(node
, 0, &res
);
182 pr_err("%s: could not get address for node %s\n",
183 __func__
, node
->full_name
);
187 rsize
= resource_size(&res
);
188 if (rsize
< trampoline_sz
) {
189 pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n",
190 __func__
, rsize
, trampoline_sz
);
194 /* set the boot function for the sram code */
195 rockchip_boot_fn
= virt_to_phys(secondary_startup
);
197 /* copy the trampoline to sram, that runs during startup of the core */
198 memcpy(sram_base_addr
, &rockchip_secondary_trampoline
, trampoline_sz
);
200 outer_clean_range(0, trampoline_sz
);
207 static const struct regmap_config rockchip_pmu_regmap_config
= {
213 static int __init
rockchip_smp_prepare_pmu(void)
215 struct device_node
*node
;
216 void __iomem
*pmu_base
;
219 * This function is only called via smp_ops->smp_prepare_cpu().
220 * That only happens if a "/cpus" device tree node exists
221 * and has an "enable-method" property that selects the SMP
222 * operations defined herein.
224 node
= of_find_node_by_path("/cpus");
226 pmu
= syscon_regmap_lookup_by_phandle(node
, "rockchip,pmu");
231 pmu
= syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
235 /* fallback, create our own regmap for the pmu area */
237 node
= of_find_compatible_node(NULL
, NULL
, "rockchip,rk3066-pmu");
239 pr_err("%s: could not find pmu dt node\n", __func__
);
243 pmu_base
= of_iomap(node
, 0);
245 pr_err("%s: could not map pmu registers\n", __func__
);
249 pmu
= regmap_init_mmio(NULL
, pmu_base
, &rockchip_pmu_regmap_config
);
251 int ret
= PTR_ERR(pmu
);
255 pr_err("%s: regmap init failed\n", __func__
);
262 static void __init
rockchip_smp_prepare_cpus(unsigned int max_cpus
)
264 struct device_node
*node
;
267 node
= of_find_compatible_node(NULL
, NULL
, "rockchip,rk3066-smp-sram");
269 pr_err("%s: could not find sram dt node\n", __func__
);
273 sram_base_addr
= of_iomap(node
, 0);
274 if (!sram_base_addr
) {
275 pr_err("%s: could not map sram registers\n", __func__
);
279 if (rockchip_smp_prepare_pmu())
282 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9
) {
283 if (rockchip_smp_prepare_sram(node
))
286 /* enable the SCU power domain */
287 pmu_set_power_domain(PMU_PWRDN_SCU
, true);
289 node
= of_find_compatible_node(NULL
, NULL
, "arm,cortex-a9-scu");
291 pr_err("%s: missing scu\n", __func__
);
295 scu_base_addr
= of_iomap(node
, 0);
296 if (!scu_base_addr
) {
297 pr_err("%s: could not map scu registers\n", __func__
);
302 * While the number of cpus is gathered from dt, also get the
303 * number of cores from the scu to verify this value when
306 ncores
= scu_get_core_count(scu_base_addr
);
307 pr_err("%s: ncores %d\n", __func__
, ncores
);
309 scu_enable(scu_base_addr
);
313 asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr
));
314 ncores
= ((l2ctlr
>> 24) & 0x3) + 1;
317 /* Make sure that all cores except the first are really off */
318 for (i
= 1; i
< ncores
; i
++)
319 pmu_set_power_domain(0 + i
, false);
322 #ifdef CONFIG_HOTPLUG_CPU
323 static int rockchip_cpu_kill(unsigned int cpu
)
326 * We need a delay here to ensure that the dying CPU can finish
327 * executing v7_coherency_exit() and reach the WFI/WFE state
328 * prior to having the power domain disabled.
332 pmu_set_power_domain(0 + cpu
, false);
336 static void rockchip_cpu_die(unsigned int cpu
)
338 v7_exit_coherency_flush(louis
);
344 static struct smp_operations rockchip_smp_ops __initdata
= {
345 .smp_prepare_cpus
= rockchip_smp_prepare_cpus
,
346 .smp_boot_secondary
= rockchip_boot_secondary
,
347 #ifdef CONFIG_HOTPLUG_CPU
348 .cpu_kill
= rockchip_cpu_kill
,
349 .cpu_die
= rockchip_cpu_die
,
353 CPU_METHOD_OF_DECLARE(rk3066_smp
, "rockchip,rk3066-smp", &rockchip_smp_ops
);