arch/arm/mach-s3c2410/include/mach/dma.h

   1 /* arch/arm/mach-s3c2410/include/mach/dma.h
   2  *
   3  * Copyright (C) 2003,2004,2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * Samsung S3C24XX DMA support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ASM_ARCH_DMA_H
  14 #define __ASM_ARCH_DMA_H __FILE__
  15
  16 #include <plat/dma.h>
  17 #include <linux/sysdev.h>
  18 #include <mach/hardware.h>
  19
  20 #define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
  21
  22 /* We use `virtual` dma channels to hide the fact we have only a limited
  23  * number of DMA channels, and not of all of them (dependant on the device)
  24  * can be attached to any DMA source. We therefore let the DMA core handle
  25  * the allocation of hardware channels to clients.
  26 */
  27
  28 enum dma_ch {
  29         DMACH_XD0,
  30         DMACH_XD1,
  31         DMACH_SDI,
  32         DMACH_SPI0,
  33         DMACH_SPI1,
  34         DMACH_UART0,
  35         DMACH_UART1,
  36         DMACH_UART2,
  37         DMACH_TIMER,
  38         DMACH_I2S_IN,
  39         DMACH_I2S_OUT,
  40         DMACH_PCM_IN,
  41         DMACH_PCM_OUT,
  42         DMACH_MIC_IN,
  43         DMACH_USB_EP1,
  44         DMACH_USB_EP2,
  45         DMACH_USB_EP3,
  46         DMACH_USB_EP4,
  47         DMACH_UART0_SRC2,       /* s3c2412 second uart sources */
  48         DMACH_UART1_SRC2,
  49         DMACH_UART2_SRC2,
  50         DMACH_UART3,            /* s3c2443 has extra uart */
  51         DMACH_UART3_SRC2,
  52         DMACH_MAX,              /* the end entry */
  53 };
  54
  55 #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
  56
  57 /* we have 4 dma channels */
  58 #ifndef CONFIG_CPU_S3C2443
  59 #define S3C2410_DMA_CHANNELS            (4)
  60 #else
  61 #define S3C2410_DMA_CHANNELS            (6)
  62 #endif
  63
  64 /* types */
  65
  66 enum s3c2410_dma_state {
  67         S3C2410_DMA_IDLE,
  68         S3C2410_DMA_RUNNING,
  69         S3C2410_DMA_PAUSED
  70 };
  71
  72 /* enum s3c2410_dma_loadst
  73  *
  74  * This represents the state of the DMA engine, wrt to the loaded / running
  75  * transfers. Since we don't have any way of knowing exactly the state of
  76  * the DMA transfers, we need to know the state to make decisions on wether
  77  * we can
  78  *
  79  * S3C2410_DMA_NONE
  80  *
  81  * There are no buffers loaded (the channel should be inactive)
  82  *
  83  * S3C2410_DMA_1LOADED
  84  *
  85  * There is one buffer loaded, however it has not been confirmed to be
  86  * loaded by the DMA engine. This may be because the channel is not
  87  * yet running, or the DMA driver decided that it was too costly to
  88  * sit and wait for it to happen.
  89  *
  90  * S3C2410_DMA_1RUNNING
  91  *
  92  * The buffer has been confirmed running, and not finisged
  93  *
  94  * S3C2410_DMA_1LOADED_1RUNNING
  95  *
  96  * There is a buffer waiting to be loaded by the DMA engine, and one
  97  * currently running.
  98 */
  99
 100 enum s3c2410_dma_loadst {
 101         S3C2410_DMALOAD_NONE,
 102         S3C2410_DMALOAD_1LOADED,
 103         S3C2410_DMALOAD_1RUNNING,
 104         S3C2410_DMALOAD_1LOADED_1RUNNING,
 105 };
 106
 107
 108 /* flags */
 109
 110 #define S3C2410_DMAF_SLOW         (1<<0)   /* slow, so don't worry about
 111                                             * waiting for reloads */
 112 #define S3C2410_DMAF_AUTOSTART    (1<<1)   /* auto-start if buffer queued */
 113
 114 /* dma buffer */
 115
 116 struct s3c2410_dma_buf;
 117
 118 /* s3c2410_dma_buf
 119  *
 120  * internally used buffer structure to describe a queued or running
 121  * buffer.
 122 */
 123
 124 struct s3c2410_dma_buf {
 125         struct s3c2410_dma_buf  *next;
 126         int                      magic;         /* magic */
 127         int                      size;          /* buffer size in bytes */
 128         dma_addr_t               data;          /* start of DMA data */
 129         dma_addr_t               ptr;           /* where the DMA got to [1] */
 130         void                    *id;            /* client's id */
 131 };
 132
 133 /* [1] is this updated for both recv/send modes? */
 134
 135 struct s3c2410_dma_stats {
 136         unsigned long           loads;
 137         unsigned long           timeout_longest;
 138         unsigned long           timeout_shortest;
 139         unsigned long           timeout_avg;
 140         unsigned long           timeout_failed;
 141 };
 142
 143 struct s3c2410_dma_map;
 144
 145 /* struct s3c2410_dma_chan
 146  *
 147  * full state information for each DMA channel
 148 */
 149
 150 struct s3c2410_dma_chan {
 151         /* channel state flags and information */
 152         unsigned char            number;      /* number of this dma channel */
 153         unsigned char            in_use;      /* channel allocated */
 154         unsigned char            irq_claimed; /* irq claimed for channel */
 155         unsigned char            irq_enabled; /* irq enabled for channel */
 156         unsigned char            xfer_unit;   /* size of an transfer */
 157
 158         /* channel state */
 159
 160         enum s3c2410_dma_state   state;
 161         enum s3c2410_dma_loadst  load_state;
 162         struct s3c2410_dma_client *client;
 163
 164         /* channel configuration */
 165         enum s3c2410_dmasrc      source;
 166         enum dma_ch              req_ch;
 167         unsigned long            dev_addr;
 168         unsigned long            load_timeout;
 169         unsigned int             flags;         /* channel flags */
 170
 171         struct s3c24xx_dma_map  *map;           /* channel hw maps */
 172
 173         /* channel's hardware position and configuration */
 174         void __iomem            *regs;          /* channels registers */
 175         void __iomem            *addr_reg;      /* data address register */
 176         unsigned int             irq;           /* channel irq */
 177         unsigned long            dcon;          /* default value of DCON */
 178
 179         /* driver handles */
 180         s3c2410_dma_cbfn_t       callback_fn;   /* buffer done callback */
 181         s3c2410_dma_opfn_t       op_fn;         /* channel op callback */
 182
 183         /* stats gathering */
 184         struct s3c2410_dma_stats *stats;
 185         struct s3c2410_dma_stats  stats_store;
 186
 187         /* buffer list and information */
 188         struct s3c2410_dma_buf  *curr;          /* current dma buffer */
 189         struct s3c2410_dma_buf  *next;          /* next buffer to load */
 190         struct s3c2410_dma_buf  *end;           /* end of queue */
 191
 192         /* system device */
 193         struct sys_device       dev;
 194 };
 195
 196 /* the currently allocated channel information */
 197 extern struct s3c2410_dma_chan s3c2410_chans[];
 198
 199 /* note, we don't really use dma_device_t at the moment */
 200 typedef unsigned long dma_device_t;
 201
 202 #endif /* __ASM_ARCH_DMA_H */