arch/arm/mach-s3c2410/include/mach/dma.h

   1 /* arch/arm/mach-s3c2410/include/mach/dma.h
   2  *
   3  * Copyright (C) 2003,2004,2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * Samsung S3C24XX DMA support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ASM_ARCH_DMA_H
  14 #define __ASM_ARCH_DMA_H __FILE__
  15
  16 #include <linux/sysdev.h>
  17 #include <mach/hardware.h>
  18
  19 #define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
  20
  21 /* We use `virtual` dma channels to hide the fact we have only a limited
  22  * number of DMA channels, and not of all of them (dependant on the device)
  23  * can be attached to any DMA source. We therefore let the DMA core handle
  24  * the allocation of hardware channels to clients.
  25 */
  26
  27 enum dma_ch {
  28         DMACH_XD0,
  29         DMACH_XD1,
  30         DMACH_SDI,
  31         DMACH_SPI0,
  32         DMACH_SPI1,
  33         DMACH_UART0,
  34         DMACH_UART1,
  35         DMACH_UART2,
  36         DMACH_TIMER,
  37         DMACH_I2S_IN,
  38         DMACH_I2S_OUT,
  39         DMACH_PCM_IN,
  40         DMACH_PCM_OUT,
  41         DMACH_MIC_IN,
  42         DMACH_USB_EP1,
  43         DMACH_USB_EP2,
  44         DMACH_USB_EP3,
  45         DMACH_USB_EP4,
  46         DMACH_UART0_SRC2,       /* s3c2412 second uart sources */
  47         DMACH_UART1_SRC2,
  48         DMACH_UART2_SRC2,
  49         DMACH_UART3,            /* s3c2443 has extra uart */
  50         DMACH_UART3_SRC2,
  51         DMACH_MAX,              /* the end entry */
  52 };
  53
  54 #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
  55
  56 /* we have 4 dma channels */
  57 #ifndef CONFIG_CPU_S3C2443
  58 #define S3C2410_DMA_CHANNELS            (4)
  59 #else
  60 #define S3C2410_DMA_CHANNELS            (6)
  61 #endif
  62
  63 /* types */
  64
  65 enum s3c2410_dma_state {
  66         S3C2410_DMA_IDLE,
  67         S3C2410_DMA_RUNNING,
  68         S3C2410_DMA_PAUSED
  69 };
  70
  71 /* enum s3c2410_dma_loadst
  72  *
  73  * This represents the state of the DMA engine, wrt to the loaded / running
  74  * transfers. Since we don't have any way of knowing exactly the state of
  75  * the DMA transfers, we need to know the state to make decisions on wether
  76  * we can
  77  *
  78  * S3C2410_DMA_NONE
  79  *
  80  * There are no buffers loaded (the channel should be inactive)
  81  *
  82  * S3C2410_DMA_1LOADED
  83  *
  84  * There is one buffer loaded, however it has not been confirmed to be
  85  * loaded by the DMA engine. This may be because the channel is not
  86  * yet running, or the DMA driver decided that it was too costly to
  87  * sit and wait for it to happen.
  88  *
  89  * S3C2410_DMA_1RUNNING
  90  *
  91  * The buffer has been confirmed running, and not finisged
  92  *
  93  * S3C2410_DMA_1LOADED_1RUNNING
  94  *
  95  * There is a buffer waiting to be loaded by the DMA engine, and one
  96  * currently running.
  97 */
  98
  99 enum s3c2410_dma_loadst {
 100         S3C2410_DMALOAD_NONE,
 101         S3C2410_DMALOAD_1LOADED,
 102         S3C2410_DMALOAD_1RUNNING,
 103         S3C2410_DMALOAD_1LOADED_1RUNNING,
 104 };
 105
 106 enum s3c2410_dma_buffresult {
 107         S3C2410_RES_OK,
 108         S3C2410_RES_ERR,
 109         S3C2410_RES_ABORT
 110 };
 111
 112 enum s3c2410_dmasrc {
 113         S3C2410_DMASRC_HW,              /* source is memory */
 114         S3C2410_DMASRC_MEM              /* source is hardware */
 115 };
 116
 117 /* enum s3c2410_chan_op
 118  *
 119  * operation codes passed to the DMA code by the user, and also used
 120  * to inform the current channel owner of any changes to the system state
 121 */
 122
 123 enum s3c2410_chan_op {
 124         S3C2410_DMAOP_START,
 125         S3C2410_DMAOP_STOP,
 126         S3C2410_DMAOP_PAUSE,
 127         S3C2410_DMAOP_RESUME,
 128         S3C2410_DMAOP_FLUSH,
 129         S3C2410_DMAOP_TIMEOUT,          /* internal signal to handler */
 130         S3C2410_DMAOP_STARTED,          /* indicate channel started */
 131 };
 132
 133 /* flags */
 134
 135 #define S3C2410_DMAF_SLOW         (1<<0)   /* slow, so don't worry about
 136                                             * waiting for reloads */
 137 #define S3C2410_DMAF_AUTOSTART    (1<<1)   /* auto-start if buffer queued */
 138
 139 /* dma buffer */
 140
 141 struct s3c2410_dma_client {
 142         char                *name;
 143 };
 144
 145 /* s3c2410_dma_buf_s
 146  *
 147  * internally used buffer structure to describe a queued or running
 148  * buffer.
 149 */
 150
 151 struct s3c2410_dma_buf;
 152 struct s3c2410_dma_buf {
 153         struct s3c2410_dma_buf  *next;
 154         int                      magic;         /* magic */
 155         int                      size;          /* buffer size in bytes */
 156         dma_addr_t               data;          /* start of DMA data */
 157         dma_addr_t               ptr;           /* where the DMA got to [1] */
 158         void                    *id;            /* client's id */
 159 };
 160
 161 /* [1] is this updated for both recv/send modes? */
 162
 163 struct s3c2410_dma_chan;
 164
 165 /* s3c2410_dma_cbfn_t
 166  *
 167  * buffer callback routine type
 168 */
 169
 170 typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
 171                                    void *buf, int size,
 172                                    enum s3c2410_dma_buffresult result);
 173
 174 typedef int  (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
 175                                    enum s3c2410_chan_op );
 176
 177 struct s3c2410_dma_stats {
 178         unsigned long           loads;
 179         unsigned long           timeout_longest;
 180         unsigned long           timeout_shortest;
 181         unsigned long           timeout_avg;
 182         unsigned long           timeout_failed;
 183 };
 184
 185 struct s3c2410_dma_map;
 186
 187 /* struct s3c2410_dma_chan
 188  *
 189  * full state information for each DMA channel
 190 */
 191
 192 struct s3c2410_dma_chan {
 193         /* channel state flags and information */
 194         unsigned char            number;      /* number of this dma channel */
 195         unsigned char            in_use;      /* channel allocated */
 196         unsigned char            irq_claimed; /* irq claimed for channel */
 197         unsigned char            irq_enabled; /* irq enabled for channel */
 198         unsigned char            xfer_unit;   /* size of an transfer */
 199
 200         /* channel state */
 201
 202         enum s3c2410_dma_state   state;
 203         enum s3c2410_dma_loadst  load_state;
 204         struct s3c2410_dma_client *client;
 205
 206         /* channel configuration */
 207         enum s3c2410_dmasrc      source;
 208         enum dma_ch              req_ch;
 209         unsigned long            dev_addr;
 210         unsigned long            load_timeout;
 211         unsigned int             flags;         /* channel flags */
 212
 213         struct s3c24xx_dma_map  *map;           /* channel hw maps */
 214
 215         /* channel's hardware position and configuration */
 216         void __iomem            *regs;          /* channels registers */
 217         void __iomem            *addr_reg;      /* data address register */
 218         unsigned int             irq;           /* channel irq */
 219         unsigned long            dcon;          /* default value of DCON */
 220
 221         /* driver handles */
 222         s3c2410_dma_cbfn_t       callback_fn;   /* buffer done callback */
 223         s3c2410_dma_opfn_t       op_fn;         /* channel op callback */
 224
 225         /* stats gathering */
 226         struct s3c2410_dma_stats *stats;
 227         struct s3c2410_dma_stats  stats_store;
 228
 229         /* buffer list and information */
 230         struct s3c2410_dma_buf  *curr;          /* current dma buffer */
 231         struct s3c2410_dma_buf  *next;          /* next buffer to load */
 232         struct s3c2410_dma_buf  *end;           /* end of queue */
 233
 234         /* system device */
 235         struct sys_device       dev;
 236 };
 237
 238 /* the currently allocated channel information */
 239 extern struct s3c2410_dma_chan s3c2410_chans[];
 240
 241 /* note, we don't really use dma_device_t at the moment */
 242 typedef unsigned long dma_device_t;
 243
 244 /* functions --------------------------------------------------------------- */
 245
 246 /* s3c2410_dma_request
 247  *
 248  * request a dma channel exclusivley
 249 */
 250
 251 extern int s3c2410_dma_request(unsigned int channel,
 252                                struct s3c2410_dma_client *, void *dev);
 253
 254
 255 /* s3c2410_dma_ctrl
 256  *
 257  * change the state of the dma channel
 258 */
 259
 260 extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
 261
 262 /* s3c2410_dma_setflags
 263  *
 264  * set the channel's flags to a given state
 265 */
 266
 267 extern int s3c2410_dma_setflags(unsigned int channel,
 268                                 unsigned int flags);
 269
 270 /* s3c2410_dma_free
 271  *
 272  * free the dma channel (will also abort any outstanding operations)
 273 */
 274
 275 extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
 276
 277 /* s3c2410_dma_enqueue
 278  *
 279  * place the given buffer onto the queue of operations for the channel.
 280  * The buffer must be allocated from dma coherent memory, or the Dcache/WB
 281  * drained before the buffer is given to the DMA system.
 282 */
 283
 284 extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
 285                                dma_addr_t data, int size);
 286
 287 /* s3c2410_dma_config
 288  *
 289  * configure the dma channel
 290 */
 291
 292 extern int s3c2410_dma_config(unsigned int channel, int xferunit);
 293
 294 /* s3c2410_dma_devconfig
 295  *
 296  * configure the device we're talking to
 297 */
 298
 299 extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
 300                                  unsigned long devaddr);
 301
 302 /* s3c2410_dma_getposition
 303  *
 304  * get the position that the dma transfer is currently at
 305 */
 306
 307 extern int s3c2410_dma_getposition(unsigned int channel,
 308                                    dma_addr_t *src, dma_addr_t *dest);
 309
 310 extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
 311 extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
 312
 313 #endif /* __ASM_ARCH_DMA_H */