arch/arm/mach-s3c2410/include/mach/regs-gpio.h

   1 /* arch/arm/mach-s3c2410/include/mach/regs-gpio.h
   2  *
   3  * Copyright (c) 2003-2004 Simtec Electronics <linux@simtec.co.uk>
   4  *      http://www.simtec.co.uk/products/SWLINUX/
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * S3C2410 GPIO register definitions
  11 */
  12
  13
  14 #ifndef __ASM_ARCH_REGS_GPIO_H
  15 #define __ASM_ARCH_REGS_GPIO_H
  16
  17 #include <mach/gpio-nrs.h>
  18
  19 #ifdef CONFIG_CPU_S3C2400
  20 #define S3C24XX_GPIO_BASE(x)  S3C2400_GPIO_BASE(x)
  21 #define S3C24XX_MISCCR        S3C2400_MISCCR
  22 #else
  23 #define S3C24XX_GPIO_BASE(x)  S3C2410_GPIO_BASE(x)
  24 #define S3C24XX_MISCCR        S3C24XX_GPIOREG2(0x80)
  25 #endif /* CONFIG_CPU_S3C2400 */
  26
  27
  28 /* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */
  29
  30 #define S3C2400_BANKNUM(pin)     (((pin) & ~31) / 32)
  31 #define S3C2400_BASEA2B(pin)     ((((pin) & ~31) >> 2))
  32 #define S3C2400_BASEC2H(pin)     ((S3C2400_BANKNUM(pin) * 10) + \
  33                                  (2 * (S3C2400_BANKNUM(pin)-2)))
  34
  35 #define S3C2400_GPIO_BASE(pin)   (pin < S3C2410_GPIO_BANKC ? \
  36                                  S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \
  37                                  S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO)
  38
  39
  40 #define S3C2410_GPIO_BASE(pin)   ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO)
  41 #define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)
  42
  43 /* general configuration options */
  44
  45 #define S3C2410_GPIO_LEAVE   (0xFFFFFFFF)
  46 #define S3C2410_GPIO_INPUT   (0xFFFFFFF0)       /* not available on A */
  47 #define S3C2410_GPIO_OUTPUT  (0xFFFFFFF1)
  48 #define S3C2410_GPIO_IRQ     (0xFFFFFFF2)       /* not available for all */
  49 #define S3C2410_GPIO_SFN2    (0xFFFFFFF2)       /* bank A => addr/cs/nand */
  50 #define S3C2410_GPIO_SFN3    (0xFFFFFFF3)       /* not available on A */
  51
  52 /* register address for the GPIO registers.
  53  * S3C24XX_GPIOREG2 is for the second set of registers in the
  54  * GPIO which move between s3c2410 and s3c2412 type systems */
  55
  56 #define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
  57 #define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
  58
  59
  60 /* configure GPIO ports A..G */
  61
  62 /* port A - S3C2410: 22bits, zero in bit X makes pin X output
  63  *          S3C2400: 18bits, zero in bit X makes pin X output
  64  * 1 makes port special function, this is default
  65 */
  66 #define S3C2410_GPACON     S3C2410_GPIOREG(0x00)
  67 #define S3C2410_GPADAT     S3C2410_GPIOREG(0x04)
  68
  69 #define S3C2400_GPACON     S3C2410_GPIOREG(0x00)
  70 #define S3C2400_GPADAT     S3C2410_GPIOREG(0x04)
  71
  72 #define S3C2410_GPA0_ADDR0   (1<<0)
  73
  74 #define S3C2410_GPA1_ADDR16  (1<<1)
  75
  76 #define S3C2410_GPA2_ADDR17  (1<<2)
  77
  78 #define S3C2410_GPA3_ADDR18  (1<<3)
  79
  80 #define S3C2410_GPA4_ADDR19  (1<<4)
  81
  82 #define S3C2410_GPA5_ADDR20  (1<<5)
  83
  84 #define S3C2410_GPA6_ADDR21  (1<<6)
  85
  86 #define S3C2410_GPA7_ADDR22  (1<<7)
  87
  88 #define S3C2410_GPA8_ADDR23  (1<<8)
  89
  90 #define S3C2410_GPA9_ADDR24  (1<<9)
  91
  92 #define S3C2410_GPA10_ADDR25 (1<<10)
  93 #define S3C2400_GPA10_SCKE   (1<<10)
  94
  95 #define S3C2410_GPA11_ADDR26 (1<<11)
  96 #define S3C2400_GPA11_nCAS0  (1<<11)
  97
  98 #define S3C2410_GPA12_nGCS1  (1<<12)
  99 #define S3C2400_GPA12_nCAS1  (1<<12)
 100
 101 #define S3C2410_GPA13_nGCS2  (1<<13)
 102 #define S3C2400_GPA13_nGCS1  (1<<13)
 103
 104 #define S3C2410_GPA14_nGCS3  (1<<14)
 105 #define S3C2400_GPA14_nGCS2  (1<<14)
 106
 107 #define S3C2410_GPA15_nGCS4  (1<<15)
 108 #define S3C2400_GPA15_nGCS3  (1<<15)
 109
 110 #define S3C2410_GPA16_nGCS5  (1<<16)
 111 #define S3C2400_GPA16_nGCS4  (1<<16)
 112
 113 #define S3C2410_GPA17_CLE    (1<<17)
 114 #define S3C2400_GPA17_nGCS5  (1<<17)
 115
 116 #define S3C2410_GPA18_ALE    (1<<18)
 117
 118 #define S3C2410_GPA19_nFWE   (1<<19)
 119
 120 #define S3C2410_GPA20_nFRE   (1<<20)
 121
 122 #define S3C2410_GPA21_nRSTOUT (1<<21)
 123
 124 #define S3C2410_GPA22_nFCE   (1<<22)
 125
 126 /* 0x08 and 0x0c are reserved on S3C2410 */
 127
 128 /* S3C2410:
 129  * GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
 130  *   00 = input, 01 = output, 10=special function, 11=reserved
 131
 132  * S3C2400:
 133  * GPB is 16 IO pins, each configured by 2 bits each in GPBCON.
 134  *   00 = input, 01 = output, 10=data, 11=special function
 135
 136  * bit 0,1 = pin 0, 2,3= pin 1...
 137  *
 138  * CPBUP = pull up resistor control, 1=disabled, 0=enabled
 139 */
 140
 141 #define S3C2410_GPBCON     S3C2410_GPIOREG(0x10)
 142 #define S3C2410_GPBDAT     S3C2410_GPIOREG(0x14)
 143 #define S3C2410_GPBUP      S3C2410_GPIOREG(0x18)
 144
 145 #define S3C2400_GPBCON     S3C2410_GPIOREG(0x08)
 146 #define S3C2400_GPBDAT     S3C2410_GPIOREG(0x0C)
 147 #define S3C2400_GPBUP      S3C2410_GPIOREG(0x10)
 148
 149 /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
 150
 151 #define S3C2410_GPB0_TOUT0   (0x02 << 0)
 152 #define S3C2400_GPB0_DATA16  (0x02 << 0)
 153
 154 #define S3C2410_GPB1_TOUT1   (0x02 << 2)
 155 #define S3C2400_GPB1_DATA17  (0x02 << 2)
 156
 157 #define S3C2410_GPB2_TOUT2   (0x02 << 4)
 158 #define S3C2400_GPB2_DATA18  (0x02 << 4)
 159 #define S3C2400_GPB2_TCLK1   (0x03 << 4)
 160
 161 #define S3C2410_GPB3_TOUT3   (0x02 << 6)
 162 #define S3C2400_GPB3_DATA19  (0x02 << 6)
 163 #define S3C2400_GPB3_TXD1    (0x03 << 6)
 164
 165 #define S3C2410_GPB4_TCLK0   (0x02 << 8)
 166 #define S3C2400_GPB4_DATA20  (0x02 << 8)
 167 #define S3C2410_GPB4_MASK    (0x03 << 8)
 168 #define S3C2400_GPB4_RXD1    (0x03 << 8)
 169 #define S3C2400_GPB4_MASK    (0x03 << 8)
 170
 171 #define S3C2410_GPB5_nXBACK  (0x02 << 10)
 172 #define S3C2443_GPB5_XBACK   (0x03 << 10)
 173 #define S3C2400_GPB5_DATA21  (0x02 << 10)
 174 #define S3C2400_GPB5_nCTS1   (0x03 << 10)
 175
 176 #define S3C2410_GPB6_nXBREQ  (0x02 << 12)
 177 #define S3C2443_GPB6_XBREQ   (0x03 << 12)
 178 #define S3C2400_GPB6_DATA22  (0x02 << 12)
 179 #define S3C2400_GPB6_nRTS1   (0x03 << 12)
 180
 181 #define S3C2410_GPB7_nXDACK1 (0x02 << 14)
 182 #define S3C2443_GPB7_XDACK1  (0x03 << 14)
 183 #define S3C2400_GPB7_DATA23  (0x02 << 14)
 184
 185 #define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
 186 #define S3C2400_GPB8_DATA24  (0x02 << 16)
 187
 188 #define S3C2410_GPB9_nXDACK0 (0x02 << 18)
 189 #define S3C2443_GPB9_XDACK0  (0x03 << 18)
 190 #define S3C2400_GPB9_DATA25  (0x02 << 18)
 191 #define S3C2400_GPB9_I2SSDI  (0x03 << 18)
 192
 193 #define S3C2410_GPB10_nXDRE0 (0x02 << 20)
 194 #define S3C2443_GPB10_XDREQ0 (0x03 << 20)
 195 #define S3C2400_GPB10_DATA26 (0x02 << 20)
 196 #define S3C2400_GPB10_nSS    (0x03 << 20)
 197
 198 #define S3C2400_GPB11_INP    (0x00 << 22)
 199 #define S3C2400_GPB11_OUTP   (0x01 << 22)
 200 #define S3C2400_GPB11_DATA27 (0x02 << 22)
 201
 202 #define S3C2400_GPB12_INP    (0x00 << 24)
 203 #define S3C2400_GPB12_OUTP   (0x01 << 24)
 204 #define S3C2400_GPB12_DATA28 (0x02 << 24)
 205
 206 #define S3C2400_GPB13_INP    (0x00 << 26)
 207 #define S3C2400_GPB13_OUTP   (0x01 << 26)
 208 #define S3C2400_GPB13_DATA29 (0x02 << 26)
 209
 210 #define S3C2400_GPB14_INP    (0x00 << 28)
 211 #define S3C2400_GPB14_OUTP   (0x01 << 28)
 212 #define S3C2400_GPB14_DATA30 (0x02 << 28)
 213
 214 #define S3C2400_GPB15_INP    (0x00 << 30)
 215 #define S3C2400_GPB15_OUTP   (0x01 << 30)
 216 #define S3C2400_GPB15_DATA31 (0x02 << 30)
 217
 218 #define S3C2410_GPB_PUPDIS(x)  (1<<(x))
 219
 220 /* Port C consits of 16 GPIO/Special function
 221  *
 222  * almost identical setup to port b, but the special functions are mostly
 223  * to do with the video system's sync/etc.
 224 */
 225
 226 #define S3C2410_GPCCON     S3C2410_GPIOREG(0x20)
 227 #define S3C2410_GPCDAT     S3C2410_GPIOREG(0x24)
 228 #define S3C2410_GPCUP      S3C2410_GPIOREG(0x28)
 229
 230 #define S3C2400_GPCCON     S3C2410_GPIOREG(0x14)
 231 #define S3C2400_GPCDAT     S3C2410_GPIOREG(0x18)
 232 #define S3C2400_GPCUP      S3C2410_GPIOREG(0x1C)
 233
 234 #define S3C2410_GPC0_LEND       (0x02 << 0)
 235 #define S3C2400_GPC0_VD0        (0x02 << 0)
 236
 237 #define S3C2410_GPC1_VCLK       (0x02 << 2)
 238 #define S3C2400_GPC1_VD1        (0x02 << 2)
 239
 240 #define S3C2410_GPC2_VLINE      (0x02 << 4)
 241 #define S3C2400_GPC2_VD2        (0x02 << 4)
 242
 243 #define S3C2410_GPC3_VFRAME     (0x02 << 6)
 244 #define S3C2400_GPC3_VD3        (0x02 << 6)
 245
 246 #define S3C2410_GPC4_VM         (0x02 << 8)
 247 #define S3C2400_GPC4_VD4        (0x02 << 8)
 248
 249 #define S3C2410_GPC5_LCDVF0     (0x02 << 10)
 250 #define S3C2400_GPC5_VD5        (0x02 << 10)
 251
 252 #define S3C2410_GPC6_LCDVF1     (0x02 << 12)
 253 #define S3C2400_GPC6_VD6        (0x02 << 12)
 254
 255 #define S3C2410_GPC7_LCDVF2     (0x02 << 14)
 256 #define S3C2400_GPC7_VD7        (0x02 << 14)
 257
 258 #define S3C2410_GPC8_VD0        (0x02 << 16)
 259 #define S3C2400_GPC8_VD8        (0x02 << 16)
 260
 261 #define S3C2410_GPC9_VD1        (0x02 << 18)
 262 #define S3C2400_GPC9_VD9        (0x02 << 18)
 263
 264 #define S3C2410_GPC10_VD2       (0x02 << 20)
 265 #define S3C2400_GPC10_VD10      (0x02 << 20)
 266
 267 #define S3C2410_GPC11_VD3       (0x02 << 22)
 268 #define S3C2400_GPC11_VD11      (0x02 << 22)
 269
 270 #define S3C2410_GPC12_VD4       (0x02 << 24)
 271 #define S3C2400_GPC12_VD12      (0x02 << 24)
 272
 273 #define S3C2410_GPC13_VD5       (0x02 << 26)
 274 #define S3C2400_GPC13_VD13      (0x02 << 26)
 275
 276 #define S3C2410_GPC14_VD6       (0x02 << 28)
 277 #define S3C2400_GPC14_VD14      (0x02 << 28)
 278
 279 #define S3C2410_GPC15_VD7       (0x02 << 30)
 280 #define S3C2400_GPC15_VD15      (0x02 << 30)
 281
 282 #define S3C2410_GPC_PUPDIS(x)  (1<<(x))
 283
 284 /*
 285  * S3C2410: Port D consists of 16 GPIO/Special function
 286  *
 287  * almost identical setup to port b, but the special functions are mostly
 288  * to do with the video system's data.
 289  *
 290  * S3C2400: Port D consists of 11 GPIO/Special function
 291  *
 292  * almost identical setup to port c
 293 */
 294
 295 #define S3C2410_GPDCON     S3C2410_GPIOREG(0x30)
 296 #define S3C2410_GPDDAT     S3C2410_GPIOREG(0x34)
 297 #define S3C2410_GPDUP      S3C2410_GPIOREG(0x38)
 298
 299 #define S3C2400_GPDCON     S3C2410_GPIOREG(0x20)
 300 #define S3C2400_GPDDAT     S3C2410_GPIOREG(0x24)
 301 #define S3C2400_GPDUP      S3C2410_GPIOREG(0x28)
 302
 303 #define S3C2410_GPD0_VD8        (0x02 << 0)
 304 #define S3C2400_GPD0_VFRAME     (0x02 << 0)
 305 #define S3C2442_GPD0_nSPICS1    (0x03 << 0)
 306
 307 #define S3C2410_GPD1_VD9        (0x02 << 2)
 308 #define S3C2400_GPD1_VM         (0x02 << 2)
 309 #define S3C2442_GPD1_SPICLK1    (0x03 << 2)
 310
 311 #define S3C2410_GPD2_VD10       (0x02 << 4)
 312 #define S3C2400_GPD2_VLINE      (0x02 << 4)
 313
 314 #define S3C2410_GPD3_VD11       (0x02 << 6)
 315 #define S3C2400_GPD3_VCLK       (0x02 << 6)
 316
 317 #define S3C2410_GPD4_VD12       (0x02 << 8)
 318 #define S3C2400_GPD4_LEND       (0x02 << 8)
 319
 320 #define S3C2410_GPD5_VD13       (0x02 << 10)
 321 #define S3C2400_GPD5_TOUT0      (0x02 << 10)
 322
 323 #define S3C2410_GPD6_VD14       (0x02 << 12)
 324 #define S3C2400_GPD6_TOUT1      (0x02 << 12)
 325
 326 #define S3C2410_GPD7_VD15       (0x02 << 14)
 327 #define S3C2400_GPD7_TOUT2      (0x02 << 14)
 328
 329 #define S3C2410_GPD8_VD16       (0x02 << 16)
 330 #define S3C2400_GPD8_TOUT3      (0x02 << 16)
 331 #define S3C2440_GPD8_SPIMISO1   (0x03 << 16)
 332
 333 #define S3C2410_GPD9_VD17       (0x02 << 18)
 334 #define S3C2400_GPD9_TCLK0      (0x02 << 18)
 335 #define S3C2440_GPD9_SPIMOSI1   (0x03 << 18)
 336
 337 #define S3C2410_GPD10_VD18      (0x02 << 20)
 338 #define S3C2400_GPD10_nWAIT     (0x02 << 20)
 339 #define S3C2440_GPD10_SPICLK1   (0x03 << 20)
 340
 341 #define S3C2410_GPD11_VD19      (0x02 << 22)
 342
 343 #define S3C2410_GPD12_VD20      (0x02 << 24)
 344
 345 #define S3C2410_GPD13_VD21      (0x02 << 26)
 346
 347 #define S3C2410_GPD14_VD22      (0x02 << 28)
 348 #define S3C2410_GPD14_nSS1      (0x03 << 28)
 349
 350 #define S3C2410_GPD15_VD23      (0x02 << 30)
 351 #define S3C2410_GPD15_nSS0      (0x03 << 30)
 352
 353 #define S3C2410_GPD_PUPDIS(x)  (1<<(x))
 354
 355 /* S3C2410:
 356  * Port E consists of 16 GPIO/Special function
 357  *
 358  * again, the same as port B, but dealing with I2S, SDI, and
 359  * more miscellaneous functions
 360  *
 361  * S3C2400:
 362  * Port E consists of 12 GPIO/Special function
 363  *
 364  * GPIO / interrupt inputs
 365 */
 366
 367 #define S3C2410_GPECON     S3C2410_GPIOREG(0x40)
 368 #define S3C2410_GPEDAT     S3C2410_GPIOREG(0x44)
 369 #define S3C2410_GPEUP      S3C2410_GPIOREG(0x48)
 370
 371 #define S3C2400_GPECON     S3C2410_GPIOREG(0x2C)
 372 #define S3C2400_GPEDAT     S3C2410_GPIOREG(0x30)
 373 #define S3C2400_GPEUP      S3C2410_GPIOREG(0x34)
 374
 375 #define S3C2410_GPE0_I2SLRCK   (0x02 << 0)
 376 #define S3C2443_GPE0_AC_nRESET (0x03 << 0)
 377 #define S3C2400_GPE0_EINT0     (0x02 << 0)
 378 #define S3C2410_GPE0_MASK      (0x03 << 0)
 379
 380 #define S3C2410_GPE1_I2SSCLK   (0x02 << 2)
 381 #define S3C2443_GPE1_AC_SYNC   (0x03 << 2)
 382 #define S3C2400_GPE1_EINT1     (0x02 << 2)
 383 #define S3C2400_GPE1_nSS       (0x03 << 2)
 384 #define S3C2410_GPE1_MASK      (0x03 << 2)
 385
 386 #define S3C2410_GPE2_CDCLK     (0x02 << 4)
 387 #define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
 388 #define S3C2400_GPE2_EINT2     (0x02 << 4)
 389 #define S3C2400_GPE2_I2SSDI    (0x03 << 4)
 390
 391 #define S3C2410_GPE3_I2SSDI    (0x02 << 6)
 392 #define S3C2443_GPE3_AC_SDI    (0x03 << 6)
 393 #define S3C2400_GPE3_EINT3     (0x02 << 6)
 394 #define S3C2400_GPE3_nCTS1     (0x03 << 6)
 395 #define S3C2410_GPE3_nSS0      (0x03 << 6)
 396 #define S3C2410_GPE3_MASK      (0x03 << 6)
 397
 398 #define S3C2410_GPE4_I2SSDO    (0x02 << 8)
 399 #define S3C2443_GPE4_AC_SDO    (0x03 << 8)
 400 #define S3C2400_GPE4_EINT4     (0x02 << 8)
 401 #define S3C2400_GPE4_nRTS1     (0x03 << 8)
 402 #define S3C2410_GPE4_I2SSDI    (0x03 << 8)
 403 #define S3C2410_GPE4_MASK      (0x03 << 8)
 404
 405 #define S3C2410_GPE5_SDCLK     (0x02 << 10)
 406 #define S3C2443_GPE5_SD1_CLK   (0x02 << 10)
 407 #define S3C2400_GPE5_EINT5     (0x02 << 10)
 408 #define S3C2400_GPE5_TCLK1     (0x03 << 10)
 409 #define S3C2443_GPE5_AC_BITCLK (0x03 << 10)
 410
 411 #define S3C2410_GPE6_SDCMD     (0x02 << 12)
 412 #define S3C2443_GPE6_SD1_CMD   (0x02 << 12)
 413 #define S3C2443_GPE6_AC_SDI    (0x03 << 12)
 414 #define S3C2400_GPE6_EINT6     (0x02 << 12)
 415
 416 #define S3C2410_GPE7_SDDAT0    (0x02 << 14)
 417 #define S3C2443_GPE5_SD1_DAT0  (0x02 << 14)
 418 #define S3C2443_GPE7_AC_SDO    (0x03 << 14)
 419 #define S3C2400_GPE7_EINT7     (0x02 << 14)
 420
 421 #define S3C2410_GPE8_SDDAT1    (0x02 << 16)
 422 #define S3C2443_GPE8_SD1_DAT1  (0x02 << 16)
 423 #define S3C2443_GPE8_AC_SYNC   (0x03 << 16)
 424 #define S3C2400_GPE8_nXDACK0   (0x02 << 16)
 425
 426 #define S3C2410_GPE9_SDDAT2    (0x02 << 18)
 427 #define S3C2443_GPE9_SD1_DAT2  (0x02 << 18)
 428 #define S3C2443_GPE9_AC_nRESET (0x03 << 18)
 429 #define S3C2400_GPE9_nXDACK1   (0x02 << 18)
 430 #define S3C2400_GPE9_nXBACK    (0x03 << 18)
 431
 432 #define S3C2410_GPE10_SDDAT3   (0x02 << 20)
 433 #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
 434 #define S3C2400_GPE10_nXDREQ0  (0x02 << 20)
 435
 436 #define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
 437 #define S3C2400_GPE11_nXDREQ1  (0x02 << 22)
 438 #define S3C2400_GPE11_nXBREQ   (0x03 << 22)
 439
 440 #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
 441
 442 #define S3C2410_GPE13_SPICLK0  (0x02 << 26)
 443
 444 #define S3C2410_GPE14_IICSCL   (0x02 << 28)
 445 #define S3C2410_GPE14_MASK     (0x03 << 28)
 446
 447 #define S3C2410_GPE15_IICSDA   (0x02 << 30)
 448 #define S3C2410_GPE15_MASK     (0x03 << 30)
 449
 450 #define S3C2440_GPE0_ACSYNC    (0x03 << 0)
 451 #define S3C2440_GPE1_ACBITCLK  (0x03 << 2)
 452 #define S3C2440_GPE2_ACRESET   (0x03 << 4)
 453 #define S3C2440_GPE3_ACIN      (0x03 << 6)
 454 #define S3C2440_GPE4_ACOUT     (0x03 << 8)
 455
 456 #define S3C2410_GPE_PUPDIS(x)  (1<<(x))
 457
 458 /* S3C2410:
 459  * Port F consists of 8 GPIO/Special function
 460  *
 461  * GPIO / interrupt inputs
 462  *
 463  * GPFCON has 2 bits for each of the input pins on port F
 464  *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
 465  *
 466  * pull up works like all other ports.
 467  *
 468  * S3C2400:
 469  * Port F consists of 7 GPIO/Special function
 470  *
 471  * GPIO/serial/misc pins
 472 */
 473
 474 #define S3C2410_GPFCON     S3C2410_GPIOREG(0x50)
 475 #define S3C2410_GPFDAT     S3C2410_GPIOREG(0x54)
 476 #define S3C2410_GPFUP      S3C2410_GPIOREG(0x58)
 477
 478 #define S3C2400_GPFCON     S3C2410_GPIOREG(0x38)
 479 #define S3C2400_GPFDAT     S3C2410_GPIOREG(0x3C)
 480 #define S3C2400_GPFUP      S3C2410_GPIOREG(0x40)
 481
 482 #define S3C2410_GPF0_EINT0  (0x02 << 0)
 483 #define S3C2400_GPF0_RXD0   (0x02 << 0)
 484
 485 #define S3C2410_GPF1_EINT1  (0x02 << 2)
 486 #define S3C2400_GPF1_RXD1   (0x02 << 2)
 487 #define S3C2400_GPF1_IICSDA (0x03 << 2)
 488
 489 #define S3C2410_GPF2_EINT2  (0x02 << 4)
 490 #define S3C2400_GPF2_TXD0   (0x02 << 4)
 491
 492 #define S3C2410_GPF3_EINT3  (0x02 << 6)
 493 #define S3C2400_GPF3_TXD1   (0x02 << 6)
 494 #define S3C2400_GPF3_IICSCL (0x03 << 6)
 495
 496 #define S3C2410_GPF4_EINT4  (0x02 << 8)
 497 #define S3C2400_GPF4_nRTS0  (0x02 << 8)
 498 #define S3C2400_GPF4_nXBACK (0x03 << 8)
 499
 500 #define S3C2410_GPF5_EINT5  (0x02 << 10)
 501 #define S3C2400_GPF5_nCTS0  (0x02 << 10)
 502 #define S3C2400_GPF5_nXBREQ (0x03 << 10)
 503
 504 #define S3C2410_GPF6_EINT6  (0x02 << 12)
 505 #define S3C2400_GPF6_CLKOUT (0x02 << 12)
 506
 507 #define S3C2410_GPF7_EINT7  (0x02 << 14)
 508
 509 #define S3C2410_GPF_PUPDIS(x)  (1<<(x))
 510
 511 /* S3C2410:
 512  * Port G consists of 8 GPIO/IRQ/Special function
 513  *
 514  * GPGCON has 2 bits for each of the input pins on port F
 515  *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
 516  *
 517  * pull up works like all other ports.
 518  *
 519  * S3C2400:
 520  * Port G consists of 10 GPIO/Special function
 521 */
 522
 523 #define S3C2410_GPGCON     S3C2410_GPIOREG(0x60)
 524 #define S3C2410_GPGDAT     S3C2410_GPIOREG(0x64)
 525 #define S3C2410_GPGUP      S3C2410_GPIOREG(0x68)
 526
 527 #define S3C2400_GPGCON     S3C2410_GPIOREG(0x44)
 528 #define S3C2400_GPGDAT     S3C2410_GPIOREG(0x48)
 529 #define S3C2400_GPGUP      S3C2410_GPIOREG(0x4C)
 530
 531 #define S3C2410_GPG0_EINT8    (0x02 << 0)
 532 #define S3C2400_GPG0_I2SLRCK  (0x02 << 0)
 533
 534 #define S3C2410_GPG1_EINT9    (0x02 << 2)
 535 #define S3C2400_GPG1_I2SSCLK  (0x02 << 2)
 536
 537 #define S3C2410_GPG2_EINT10   (0x02 << 4)
 538 #define S3C2410_GPG2_nSS0     (0x03 << 4)
 539 #define S3C2400_GPG2_CDCLK    (0x02 << 4)
 540
 541 #define S3C2410_GPG3_EINT11   (0x02 << 6)
 542 #define S3C2410_GPG3_nSS1     (0x03 << 6)
 543 #define S3C2400_GPG3_I2SSDO   (0x02 << 6)
 544 #define S3C2400_GPG3_I2SSDI   (0x03 << 6)
 545
 546 #define S3C2410_GPG4_EINT12   (0x02 << 8)
 547 #define S3C2400_GPG4_MMCCLK   (0x02 << 8)
 548 #define S3C2400_GPG4_I2SSDI   (0x03 << 8)
 549 #define S3C2410_GPG4_LCDPWREN (0x03 << 8)
 550 #define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
 551
 552 #define S3C2410_GPG5_EINT13   (0x02 << 10)
 553 #define S3C2400_GPG5_MMCCMD   (0x02 << 10)
 554 #define S3C2400_GPG5_IICSDA   (0x03 << 10)
 555 #define S3C2410_GPG5_SPIMISO1 (0x03 << 10)      /* not s3c2443 */
 556
 557 #define S3C2410_GPG6_EINT14   (0x02 << 12)
 558 #define S3C2400_GPG6_MMCDAT   (0x02 << 12)
 559 #define S3C2400_GPG6_IICSCL   (0x03 << 12)
 560 #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
 561
 562 #define S3C2410_GPG7_EINT15   (0x02 << 14)
 563 #define S3C2410_GPG7_SPICLK1  (0x03 << 14)
 564 #define S3C2400_GPG7_SPIMISO  (0x02 << 14)
 565 #define S3C2400_GPG7_IICSDA   (0x03 << 14)
 566
 567 #define S3C2410_GPG8_EINT16   (0x02 << 16)
 568 #define S3C2400_GPG8_SPIMOSI  (0x02 << 16)
 569 #define S3C2400_GPG8_IICSCL   (0x03 << 16)
 570
 571 #define S3C2410_GPG9_EINT17   (0x02 << 18)
 572 #define S3C2400_GPG9_SPICLK   (0x02 << 18)
 573 #define S3C2400_GPG9_MMCCLK   (0x03 << 18)
 574
 575 #define S3C2410_GPG10_EINT18  (0x02 << 20)
 576
 577 #define S3C2410_GPG11_EINT19  (0x02 << 22)
 578 #define S3C2410_GPG11_TCLK1   (0x03 << 22)
 579 #define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
 580
 581 #define S3C2410_GPG12_EINT20  (0x02 << 24)
 582 #define S3C2410_GPG12_XMON    (0x03 << 24)
 583 #define S3C2442_GPG12_nSPICS0 (0x03 << 24)
 584 #define S3C2443_GPG12_nINPACK (0x03 << 24)
 585
 586 #define S3C2410_GPG13_EINT21  (0x02 << 26)
 587 #define S3C2410_GPG13_nXPON   (0x03 << 26)
 588 #define S3C2443_GPG13_CF_nREG (0x03 << 26)
 589
 590 #define S3C2410_GPG14_EINT22  (0x02 << 28)
 591 #define S3C2410_GPG14_YMON    (0x03 << 28)
 592 #define S3C2443_GPG14_CF_RESET (0x03 << 28)
 593
 594 #define S3C2410_GPG15_EINT23  (0x02 << 30)
 595 #define S3C2410_GPG15_nYPON   (0x03 << 30)
 596 #define S3C2443_GPG15_CF_PWR  (0x03 << 30)
 597
 598 #define S3C2410_GPG_PUPDIS(x)  (1<<(x))
 599
 600 /* Port H consists of11 GPIO/serial/Misc pins
 601  *
 602  * GPGCON has 2 bits for each of the input pins on port F
 603  *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
 604  *
 605  * pull up works like all other ports.
 606 */
 607
 608 #define S3C2410_GPHCON     S3C2410_GPIOREG(0x70)
 609 #define S3C2410_GPHDAT     S3C2410_GPIOREG(0x74)
 610 #define S3C2410_GPHUP      S3C2410_GPIOREG(0x78)
 611
 612 #define S3C2410_GPH0_nCTS0  (0x02 << 0)
 613
 614 #define S3C2410_GPH1_nRTS0  (0x02 << 2)
 615
 616 #define S3C2410_GPH2_TXD0   (0x02 << 4)
 617
 618 #define S3C2410_GPH3_RXD0   (0x02 << 6)
 619
 620 #define S3C2410_GPH4_TXD1   (0x02 << 8)
 621
 622 #define S3C2410_GPH5_RXD1   (0x02 << 10)
 623
 624 #define S3C2410_GPH6_TXD2   (0x02 << 12)
 625 #define S3C2410_GPH6_nRTS1  (0x03 << 12)
 626
 627 #define S3C2410_GPH7_RXD2   (0x02 << 14)
 628 #define S3C2410_GPH7_nCTS1  (0x03 << 14)
 629
 630 #define S3C2410_GPH8_UCLK   (0x02 << 16)
 631
 632 #define S3C2410_GPH9_CLKOUT0  (0x02 << 18)
 633 #define S3C2442_GPH9_nSPICS0  (0x03 << 18)
 634
 635 #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
 636
 637 /* The S3C2412 and S3C2413 move the GPJ register set to after
 638  * GPH, which means all registers after 0x80 are now offset by 0x10
 639  * for the 2412/2413 from the 2410/2440/2442
 640 */
 641
 642 /* S3C2443 and above */
 643 #define S3C2440_GPJCON     S3C2410_GPIOREG(0xD0)
 644 #define S3C2440_GPJDAT     S3C2410_GPIOREG(0xD4)
 645 #define S3C2440_GPJUP      S3C2410_GPIOREG(0xD8)
 646
 647 #define S3C2443_GPKCON     S3C2410_GPIOREG(0xE0)
 648 #define S3C2443_GPKDAT     S3C2410_GPIOREG(0xE4)
 649 #define S3C2443_GPKUP      S3C2410_GPIOREG(0xE8)
 650
 651 #define S3C2443_GPLCON     S3C2410_GPIOREG(0xF0)
 652 #define S3C2443_GPLDAT     S3C2410_GPIOREG(0xF4)
 653 #define S3C2443_GPLUP      S3C2410_GPIOREG(0xF8)
 654
 655 #define S3C2443_GPMCON     S3C2410_GPIOREG(0x100)
 656 #define S3C2443_GPMDAT     S3C2410_GPIOREG(0x104)
 657 #define S3C2443_GPMUP      S3C2410_GPIOREG(0x108)
 658
 659 /* miscellaneous control */
 660 #define S3C2400_MISCCR     S3C2410_GPIOREG(0x54)
 661 #define S3C2410_MISCCR     S3C2410_GPIOREG(0x80)
 662 #define S3C2410_DCLKCON    S3C2410_GPIOREG(0x84)
 663
 664 #define S3C24XX_DCLKCON    S3C24XX_GPIOREG2(0x84)
 665
 666 /* see clock.h for dclk definitions */
 667
 668 /* pullup control on databus */
 669 #define S3C2410_MISCCR_SPUCR_HEN    (0<<0)
 670 #define S3C2410_MISCCR_SPUCR_HDIS   (1<<0)
 671 #define S3C2410_MISCCR_SPUCR_LEN    (0<<1)
 672 #define S3C2410_MISCCR_SPUCR_LDIS   (1<<1)
 673
 674 #define S3C2400_MISCCR_SPUCR_LEN    (0<<0)
 675 #define S3C2400_MISCCR_SPUCR_LDIS   (1<<0)
 676 #define S3C2400_MISCCR_SPUCR_HEN    (0<<1)
 677 #define S3C2400_MISCCR_SPUCR_HDIS   (1<<1)
 678
 679 #define S3C2400_MISCCR_HZ_STOPEN    (0<<2)
 680 #define S3C2400_MISCCR_HZ_STOPPREV  (1<<2)
 681
 682 #define S3C2410_MISCCR_USBDEV       (0<<3)
 683 #define S3C2410_MISCCR_USBHOST      (1<<3)
 684
 685 #define S3C2410_MISCCR_CLK0_MPLL    (0<<4)
 686 #define S3C2410_MISCCR_CLK0_UPLL    (1<<4)
 687 #define S3C2410_MISCCR_CLK0_FCLK    (2<<4)
 688 #define S3C2410_MISCCR_CLK0_HCLK    (3<<4)
 689 #define S3C2410_MISCCR_CLK0_PCLK    (4<<4)
 690 #define S3C2410_MISCCR_CLK0_DCLK0   (5<<4)
 691 #define S3C2410_MISCCR_CLK0_MASK    (7<<4)
 692
 693 #define S3C2412_MISCCR_CLK0_RTC     (2<<4)
 694
 695 #define S3C2410_MISCCR_CLK1_MPLL    (0<<8)
 696 #define S3C2410_MISCCR_CLK1_UPLL    (1<<8)
 697 #define S3C2410_MISCCR_CLK1_FCLK    (2<<8)
 698 #define S3C2410_MISCCR_CLK1_HCLK    (3<<8)
 699 #define S3C2410_MISCCR_CLK1_PCLK    (4<<8)
 700 #define S3C2410_MISCCR_CLK1_DCLK1   (5<<8)
 701 #define S3C2410_MISCCR_CLK1_MASK    (7<<8)
 702
 703 #define S3C2412_MISCCR_CLK1_CLKsrc  (0<<8)
 704
 705 #define S3C2410_MISCCR_USBSUSPND0   (1<<12)
 706 #define S3C2410_MISCCR_USBSUSPND1   (1<<13)
 707
 708 #define S3C2410_MISCCR_nRSTCON      (1<<16)
 709
 710 #define S3C2410_MISCCR_nEN_SCLK0    (1<<17)
 711 #define S3C2410_MISCCR_nEN_SCLK1    (1<<18)
 712 #define S3C2410_MISCCR_nEN_SCLKE    (1<<19)     /* not 2412 */
 713 #define S3C2410_MISCCR_SDSLEEP      (7<<17)
 714
 715 /* external interrupt control... */
 716 /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
 717  * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
 718  * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
 719  *
 720  * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
 721  *
 722  * Samsung datasheet p9-25
 723 */
 724 #define S3C2400_EXTINT0    S3C2410_GPIOREG(0x58)
 725 #define S3C2410_EXTINT0    S3C2410_GPIOREG(0x88)
 726 #define S3C2410_EXTINT1    S3C2410_GPIOREG(0x8C)
 727 #define S3C2410_EXTINT2    S3C2410_GPIOREG(0x90)
 728
 729 #define S3C24XX_EXTINT0    S3C24XX_GPIOREG2(0x88)
 730 #define S3C24XX_EXTINT1    S3C24XX_GPIOREG2(0x8C)
 731 #define S3C24XX_EXTINT2    S3C24XX_GPIOREG2(0x90)
 732
 733 /* interrupt filtering conrrol for EINT16..EINT23 */
 734 #define S3C2410_EINFLT0    S3C2410_GPIOREG(0x94)
 735 #define S3C2410_EINFLT1    S3C2410_GPIOREG(0x98)
 736 #define S3C2410_EINFLT2    S3C2410_GPIOREG(0x9C)
 737 #define S3C2410_EINFLT3    S3C2410_GPIOREG(0xA0)
 738
 739 #define S3C24XX_EINFLT0    S3C24XX_GPIOREG2(0x94)
 740 #define S3C24XX_EINFLT1    S3C24XX_GPIOREG2(0x98)
 741 #define S3C24XX_EINFLT2    S3C24XX_GPIOREG2(0x9C)
 742 #define S3C24XX_EINFLT3    S3C24XX_GPIOREG2(0xA0)
 743
 744 /* values for interrupt filtering */
 745 #define S3C2410_EINTFLT_PCLK            (0x00)
 746 #define S3C2410_EINTFLT_EXTCLK          (1<<7)
 747 #define S3C2410_EINTFLT_WIDTHMSK(x)     ((x) & 0x3f)
 748
 749 /* removed EINTxxxx defs from here, not meant for this */
 750
 751 /* GSTATUS have miscellaneous information in them
 752  *
 753  * These move between s3c2410 and s3c2412 style systems.
 754  */
 755
 756 #define S3C2410_GSTATUS0   S3C2410_GPIOREG(0x0AC)
 757 #define S3C2410_GSTATUS1   S3C2410_GPIOREG(0x0B0)
 758 #define S3C2410_GSTATUS2   S3C2410_GPIOREG(0x0B4)
 759 #define S3C2410_GSTATUS3   S3C2410_GPIOREG(0x0B8)
 760 #define S3C2410_GSTATUS4   S3C2410_GPIOREG(0x0BC)
 761
 762 #define S3C2412_GSTATUS0   S3C2410_GPIOREG(0x0BC)
 763 #define S3C2412_GSTATUS1   S3C2410_GPIOREG(0x0C0)
 764 #define S3C2412_GSTATUS2   S3C2410_GPIOREG(0x0C4)
 765 #define S3C2412_GSTATUS3   S3C2410_GPIOREG(0x0C8)
 766 #define S3C2412_GSTATUS4   S3C2410_GPIOREG(0x0CC)
 767
 768 #define S3C24XX_GSTATUS0   S3C24XX_GPIOREG2(0x0AC)
 769 #define S3C24XX_GSTATUS1   S3C24XX_GPIOREG2(0x0B0)
 770 #define S3C24XX_GSTATUS2   S3C24XX_GPIOREG2(0x0B4)
 771 #define S3C24XX_GSTATUS3   S3C24XX_GPIOREG2(0x0B8)
 772 #define S3C24XX_GSTATUS4   S3C24XX_GPIOREG2(0x0BC)
 773
 774 #define S3C2410_GSTATUS0_nWAIT     (1<<3)
 775 #define S3C2410_GSTATUS0_NCON      (1<<2)
 776 #define S3C2410_GSTATUS0_RnB       (1<<1)
 777 #define S3C2410_GSTATUS0_nBATTFLT  (1<<0)
 778
 779 #define S3C2410_GSTATUS1_IDMASK    (0xffff0000)
 780 #define S3C2410_GSTATUS1_2410      (0x32410000)
 781 #define S3C2410_GSTATUS1_2412      (0x32412001)
 782 #define S3C2410_GSTATUS1_2440      (0x32440000)
 783 #define S3C2410_GSTATUS1_2442      (0x32440aaa)
 784
 785 #define S3C2410_GSTATUS2_WTRESET   (1<<2)
 786 #define S3C2410_GSTATUS2_OFFRESET  (1<<1)
 787 #define S3C2410_GSTATUS2_PONRESET  (1<<0)
 788
 789 /* open drain control register */
 790 #define S3C2400_OPENCR     S3C2410_GPIOREG(0x50)
 791
 792 #define S3C2400_OPENCR_OPC_RXD1DIS  (0<<0)
 793 #define S3C2400_OPENCR_OPC_RXD1EN   (1<<0)
 794 #define S3C2400_OPENCR_OPC_TXD1DIS  (0<<1)
 795 #define S3C2400_OPENCR_OPC_TXD1EN   (1<<1)
 796 #define S3C2400_OPENCR_OPC_CMDDIS   (0<<2)
 797 #define S3C2400_OPENCR_OPC_CMDEN    (1<<2)
 798 #define S3C2400_OPENCR_OPC_DATDIS   (0<<3)
 799 #define S3C2400_OPENCR_OPC_DATEN    (1<<3)
 800 #define S3C2400_OPENCR_OPC_MISODIS  (0<<4)
 801 #define S3C2400_OPENCR_OPC_MISOEN   (1<<4)
 802 #define S3C2400_OPENCR_OPC_MOSIDIS  (0<<5)
 803 #define S3C2400_OPENCR_OPC_MOSIEN   (1<<5)
 804
 805 /* 2412/2413 sleep configuration registers */
 806
 807 #define S3C2412_GPBSLPCON       S3C2410_GPIOREG(0x1C)
 808 #define S3C2412_GPCSLPCON       S3C2410_GPIOREG(0x2C)
 809 #define S3C2412_GPDSLPCON       S3C2410_GPIOREG(0x3C)
 810 #define S3C2412_GPFSLPCON       S3C2410_GPIOREG(0x5C)
 811 #define S3C2412_GPGSLPCON       S3C2410_GPIOREG(0x6C)
 812 #define S3C2412_GPHSLPCON       S3C2410_GPIOREG(0x7C)
 813
 814 /* definitions for each pin bit */
 815 #define S3C2412_GPIO_SLPCON_LOW  ( 0x00 )
 816 #define S3C2412_GPIO_SLPCON_HIGH ( 0x01 )
 817 #define S3C2412_GPIO_SLPCON_IN   ( 0x02 )
 818 #define S3C2412_GPIO_SLPCON_PULL ( 0x03 )
 819
 820 #define S3C2412_SLPCON_LOW(x)   ( 0x00 << ((x) * 2))
 821 #define S3C2412_SLPCON_HIGH(x)  ( 0x01 << ((x) * 2))
 822 #define S3C2412_SLPCON_IN(x)    ( 0x02 << ((x) * 2))
 823 #define S3C2412_SLPCON_PULL(x)  ( 0x03 << ((x) * 2))
 824 #define S3C2412_SLPCON_EINT(x)  ( 0x02 << ((x) * 2))  /* only IRQ pins */
 825 #define S3C2412_SLPCON_MASK(x)  ( 0x03 << ((x) * 2))
 826
 827 #define S3C2412_SLPCON_ALL_LOW  (0x0)
 828 #define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444)
 829 #define S3C2412_SLPCON_ALL_IN   (0x22222222 | 0x88888888)
 830 #define S3C2412_SLPCON_ALL_PULL (0x33333333)
 831
 832 #endif  /* __ASM_ARCH_REGS_GPIO_H */
 833