arch/arm/mach-s3c2410/include/mach/regs-gpio.h

   1 /* arch/arm/mach-s3c2410/include/mach/regs-gpio.h
   2  *
   3  * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
   4  *                         http://www.simtec.co.uk/products/SWLINUX/
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * S3C2410 GPIO register definitions
  11 */
  12
  13
  14 #ifndef __ASM_ARCH_REGS_GPIO_H
  15 #define __ASM_ARCH_REGS_GPIO_H
  16
  17 #include <mach/gpio-nrs.h>
  18
  19 #ifdef CONFIG_CPU_S3C2400
  20 #define S3C24XX_GPIO_BASE(x)  S3C2400_GPIO_BASE(x)
  21 #define S3C24XX_MISCCR        S3C2400_MISCCR
  22 #else
  23 #define S3C24XX_GPIO_BASE(x)  S3C2410_GPIO_BASE(x)
  24 #define S3C24XX_MISCCR        S3C24XX_GPIOREG2(0x80)
  25 #endif /* CONFIG_CPU_S3C2400 */
  26
  27
  28 /* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */
  29
  30 #define S3C2400_BANKNUM(pin)     (((pin) & ~31) / 32)
  31 #define S3C2400_BASEA2B(pin)     ((((pin) & ~31) >> 2))
  32 #define S3C2400_BASEC2H(pin)     ((S3C2400_BANKNUM(pin) * 10) + \
  33                                  (2 * (S3C2400_BANKNUM(pin)-2)))
  34
  35 #define S3C2400_GPIO_BASE(pin)   (pin < S3C2410_GPIO_BANKC ? \
  36                                  S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \
  37                                  S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO)
  38
  39
  40 #define S3C2410_GPIO_BASE(pin)   ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO)
  41 #define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)
  42
  43 /* general configuration options */
  44
  45 #define S3C2410_GPIO_LEAVE   (0xFFFFFFFF)
  46 #define S3C2410_GPIO_INPUT   (0xFFFFFFF0)       /* not available on A */
  47 #define S3C2410_GPIO_OUTPUT  (0xFFFFFFF1)
  48 #define S3C2410_GPIO_IRQ     (0xFFFFFFF2)       /* not available for all */
  49 #define S3C2410_GPIO_SFN2    (0xFFFFFFF2)       /* bank A => addr/cs/nand */
  50 #define S3C2410_GPIO_SFN3    (0xFFFFFFF3)       /* not available on A */
  51
  52 /* register address for the GPIO registers.
  53  * S3C24XX_GPIOREG2 is for the second set of registers in the
  54  * GPIO which move between s3c2410 and s3c2412 type systems */
  55
  56 #define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
  57 #define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
  58
  59
  60 /* configure GPIO ports A..G */
  61
  62 /* port A - S3C2410: 22bits, zero in bit X makes pin X output
  63  *          S3C2400: 18bits, zero in bit X makes pin X output
  64  * 1 makes port special function, this is default
  65 */
  66 #define S3C2410_GPACON     S3C2410_GPIOREG(0x00)
  67 #define S3C2410_GPADAT     S3C2410_GPIOREG(0x04)
  68
  69 #define S3C2400_GPACON     S3C2410_GPIOREG(0x00)
  70 #define S3C2400_GPADAT     S3C2410_GPIOREG(0x04)
  71
  72 #define S3C2410_GPA0         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
  73 #define S3C2410_GPA0_ADDR0   (1<<0)
  74
  75 #define S3C2410_GPA1         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1)
  76 #define S3C2410_GPA1_ADDR16  (1<<1)
  77
  78 #define S3C2410_GPA2         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2)
  79 #define S3C2410_GPA2_ADDR17  (1<<2)
  80
  81 #define S3C2410_GPA3         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3)
  82 #define S3C2410_GPA3_ADDR18  (1<<3)
  83
  84 #define S3C2410_GPA4         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4)
  85 #define S3C2410_GPA4_ADDR19  (1<<4)
  86
  87 #define S3C2410_GPA5         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5)
  88 #define S3C2410_GPA5_ADDR20  (1<<5)
  89
  90 #define S3C2410_GPA6         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6)
  91 #define S3C2410_GPA6_ADDR21  (1<<6)
  92
  93 #define S3C2410_GPA7         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7)
  94 #define S3C2410_GPA7_ADDR22  (1<<7)
  95
  96 #define S3C2410_GPA8         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8)
  97 #define S3C2410_GPA8_ADDR23  (1<<8)
  98
  99 #define S3C2410_GPA9         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9)
 100 #define S3C2410_GPA9_ADDR24  (1<<9)
 101
 102 #define S3C2410_GPA10        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
 103 #define S3C2410_GPA10_ADDR25 (1<<10)
 104 #define S3C2400_GPA10_SCKE   (1<<10)
 105
 106 #define S3C2410_GPA11        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
 107 #define S3C2410_GPA11_ADDR26 (1<<11)
 108 #define S3C2400_GPA11_nCAS0  (1<<11)
 109
 110 #define S3C2410_GPA12        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
 111 #define S3C2410_GPA12_nGCS1  (1<<12)
 112 #define S3C2400_GPA12_nCAS1  (1<<12)
 113
 114 #define S3C2410_GPA13        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
 115 #define S3C2410_GPA13_nGCS2  (1<<13)
 116 #define S3C2400_GPA13_nGCS1  (1<<13)
 117
 118 #define S3C2410_GPA14        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
 119 #define S3C2410_GPA14_nGCS3  (1<<14)
 120 #define S3C2400_GPA14_nGCS2  (1<<14)
 121
 122 #define S3C2410_GPA15        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
 123 #define S3C2410_GPA15_nGCS4  (1<<15)
 124 #define S3C2400_GPA15_nGCS3  (1<<15)
 125
 126 #define S3C2410_GPA16        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
 127 #define S3C2410_GPA16_nGCS5  (1<<16)
 128 #define S3C2400_GPA16_nGCS4  (1<<16)
 129
 130 #define S3C2410_GPA17        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
 131 #define S3C2410_GPA17_CLE    (1<<17)
 132 #define S3C2400_GPA17_nGCS5  (1<<17)
 133
 134 #define S3C2410_GPA18        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
 135 #define S3C2410_GPA18_ALE    (1<<18)
 136
 137 #define S3C2410_GPA19        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19)
 138 #define S3C2410_GPA19_nFWE   (1<<19)
 139
 140 #define S3C2410_GPA20        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20)
 141 #define S3C2410_GPA20_nFRE   (1<<20)
 142
 143 #define S3C2410_GPA21        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21)
 144 #define S3C2410_GPA21_nRSTOUT (1<<21)
 145
 146 #define S3C2410_GPA22        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22)
 147 #define S3C2410_GPA22_nFCE   (1<<22)
 148
 149 /* 0x08 and 0x0c are reserved on S3C2410 */
 150
 151 /* S3C2410:
 152  * GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
 153  *   00 = input, 01 = output, 10=special function, 11=reserved
 154
 155  * S3C2400:
 156  * GPB is 16 IO pins, each configured by 2 bits each in GPBCON.
 157  *   00 = input, 01 = output, 10=data, 11=special function
 158
 159  * bit 0,1 = pin 0, 2,3= pin 1...
 160  *
 161  * CPBUP = pull up resistor control, 1=disabled, 0=enabled
 162 */
 163
 164 #define S3C2410_GPBCON     S3C2410_GPIOREG(0x10)
 165 #define S3C2410_GPBDAT     S3C2410_GPIOREG(0x14)
 166 #define S3C2410_GPBUP      S3C2410_GPIOREG(0x18)
 167
 168 #define S3C2400_GPBCON     S3C2410_GPIOREG(0x08)
 169 #define S3C2400_GPBDAT     S3C2410_GPIOREG(0x0C)
 170 #define S3C2400_GPBUP      S3C2410_GPIOREG(0x10)
 171
 172 /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
 173
 174 #define S3C2410_GPB0         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
 175 #define S3C2410_GPB0_TOUT0   (0x02 << 0)
 176 #define S3C2400_GPB0_DATA16  (0x02 << 0)
 177
 178 #define S3C2410_GPB1         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
 179 #define S3C2410_GPB1_TOUT1   (0x02 << 2)
 180 #define S3C2400_GPB1_DATA17  (0x02 << 2)
 181
 182 #define S3C2410_GPB2         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
 183 #define S3C2410_GPB2_TOUT2   (0x02 << 4)
 184 #define S3C2400_GPB2_DATA18  (0x02 << 4)
 185 #define S3C2400_GPB2_TCLK1   (0x03 << 4)
 186
 187 #define S3C2410_GPB3         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
 188 #define S3C2410_GPB3_TOUT3   (0x02 << 6)
 189 #define S3C2400_GPB3_DATA19  (0x02 << 6)
 190 #define S3C2400_GPB3_TXD1    (0x03 << 6)
 191
 192 #define S3C2410_GPB4         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
 193 #define S3C2410_GPB4_TCLK0   (0x02 << 8)
 194 #define S3C2400_GPB4_DATA20  (0x02 << 8)
 195 #define S3C2410_GPB4_MASK    (0x03 << 8)
 196 #define S3C2400_GPB4_RXD1    (0x03 << 8)
 197 #define S3C2400_GPB4_MASK    (0x03 << 8)
 198
 199 #define S3C2410_GPB5         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
 200 #define S3C2410_GPB5_nXBACK  (0x02 << 10)
 201 #define S3C2443_GPB5_XBACK   (0x03 << 10)
 202 #define S3C2400_GPB5_DATA21  (0x02 << 10)
 203 #define S3C2400_GPB5_nCTS1   (0x03 << 10)
 204
 205 #define S3C2410_GPB6         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
 206 #define S3C2410_GPB6_nXBREQ  (0x02 << 12)
 207 #define S3C2443_GPB6_XBREQ   (0x03 << 12)
 208 #define S3C2400_GPB6_DATA22  (0x02 << 12)
 209 #define S3C2400_GPB6_nRTS1   (0x03 << 12)
 210
 211 #define S3C2410_GPB7         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
 212 #define S3C2410_GPB7_nXDACK1 (0x02 << 14)
 213 #define S3C2443_GPB7_XDACK1  (0x03 << 14)
 214 #define S3C2400_GPB7_DATA23  (0x02 << 14)
 215
 216 #define S3C2410_GPB8         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
 217 #define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
 218 #define S3C2400_GPB8_DATA24  (0x02 << 16)
 219
 220 #define S3C2410_GPB9         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
 221 #define S3C2410_GPB9_nXDACK0 (0x02 << 18)
 222 #define S3C2443_GPB9_XDACK0  (0x03 << 18)
 223 #define S3C2400_GPB9_DATA25  (0x02 << 18)
 224 #define S3C2400_GPB9_I2SSDI  (0x03 << 18)
 225
 226 #define S3C2410_GPB10        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
 227 #define S3C2410_GPB10_nXDRE0 (0x02 << 20)
 228 #define S3C2443_GPB10_XDREQ0 (0x03 << 20)
 229 #define S3C2400_GPB10_DATA26 (0x02 << 20)
 230 #define S3C2400_GPB10_nSS    (0x03 << 20)
 231
 232 #define S3C2400_GPB11        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11)
 233 #define S3C2400_GPB11_INP    (0x00 << 22)
 234 #define S3C2400_GPB11_OUTP   (0x01 << 22)
 235 #define S3C2400_GPB11_DATA27 (0x02 << 22)
 236
 237 #define S3C2400_GPB12        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12)
 238 #define S3C2400_GPB12_INP    (0x00 << 24)
 239 #define S3C2400_GPB12_OUTP   (0x01 << 24)
 240 #define S3C2400_GPB12_DATA28 (0x02 << 24)
 241
 242 #define S3C2400_GPB13        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13)
 243 #define S3C2400_GPB13_INP    (0x00 << 26)
 244 #define S3C2400_GPB13_OUTP   (0x01 << 26)
 245 #define S3C2400_GPB13_DATA29 (0x02 << 26)
 246
 247 #define S3C2400_GPB14        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14)
 248 #define S3C2400_GPB14_INP    (0x00 << 28)
 249 #define S3C2400_GPB14_OUTP   (0x01 << 28)
 250 #define S3C2400_GPB14_DATA30 (0x02 << 28)
 251
 252 #define S3C2400_GPB15        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15)
 253 #define S3C2400_GPB15_INP    (0x00 << 30)
 254 #define S3C2400_GPB15_OUTP   (0x01 << 30)
 255 #define S3C2400_GPB15_DATA31 (0x02 << 30)
 256
 257 #define S3C2410_GPB_PUPDIS(x)  (1<<(x))
 258
 259 /* Port C consits of 16 GPIO/Special function
 260  *
 261  * almost identical setup to port b, but the special functions are mostly
 262  * to do with the video system's sync/etc.
 263 */
 264
 265 #define S3C2410_GPCCON     S3C2410_GPIOREG(0x20)
 266 #define S3C2410_GPCDAT     S3C2410_GPIOREG(0x24)
 267 #define S3C2410_GPCUP      S3C2410_GPIOREG(0x28)
 268
 269 #define S3C2400_GPCCON     S3C2410_GPIOREG(0x14)
 270 #define S3C2400_GPCDAT     S3C2410_GPIOREG(0x18)
 271 #define S3C2400_GPCUP      S3C2410_GPIOREG(0x1C)
 272
 273 #define S3C2410_GPC0            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
 274 #define S3C2410_GPC0_LEND       (0x02 << 0)
 275 #define S3C2400_GPC0_VD0        (0x02 << 0)
 276
 277 #define S3C2410_GPC1            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
 278 #define S3C2410_GPC1_VCLK       (0x02 << 2)
 279 #define S3C2400_GPC1_VD1        (0x02 << 2)
 280
 281 #define S3C2410_GPC2            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
 282 #define S3C2410_GPC2_VLINE      (0x02 << 4)
 283 #define S3C2400_GPC2_VD2        (0x02 << 4)
 284
 285 #define S3C2410_GPC3            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
 286 #define S3C2410_GPC3_VFRAME     (0x02 << 6)
 287 #define S3C2400_GPC3_VD3        (0x02 << 6)
 288
 289 #define S3C2410_GPC4            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
 290 #define S3C2410_GPC4_VM         (0x02 << 8)
 291 #define S3C2400_GPC4_VD4        (0x02 << 8)
 292
 293 #define S3C2410_GPC5            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
 294 #define S3C2410_GPC5_LCDVF0     (0x02 << 10)
 295 #define S3C2400_GPC5_VD5        (0x02 << 10)
 296
 297 #define S3C2410_GPC6            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
 298 #define S3C2410_GPC6_LCDVF1     (0x02 << 12)
 299 #define S3C2400_GPC6_VD6        (0x02 << 12)
 300
 301 #define S3C2410_GPC7            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
 302 #define S3C2410_GPC7_LCDVF2     (0x02 << 14)
 303 #define S3C2400_GPC7_VD7        (0x02 << 14)
 304
 305 #define S3C2410_GPC8            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
 306 #define S3C2410_GPC8_VD0        (0x02 << 16)
 307 #define S3C2400_GPC8_VD8        (0x02 << 16)
 308
 309 #define S3C2410_GPC9            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
 310 #define S3C2410_GPC9_VD1        (0x02 << 18)
 311 #define S3C2400_GPC9_VD9        (0x02 << 18)
 312
 313 #define S3C2410_GPC10           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
 314 #define S3C2410_GPC10_VD2       (0x02 << 20)
 315 #define S3C2400_GPC10_VD10      (0x02 << 20)
 316
 317 #define S3C2410_GPC11           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
 318 #define S3C2410_GPC11_VD3       (0x02 << 22)
 319 #define S3C2400_GPC11_VD11      (0x02 << 22)
 320
 321 #define S3C2410_GPC12           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
 322 #define S3C2410_GPC12_VD4       (0x02 << 24)
 323 #define S3C2400_GPC12_VD12      (0x02 << 24)
 324
 325 #define S3C2410_GPC13           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
 326 #define S3C2410_GPC13_VD5       (0x02 << 26)
 327 #define S3C2400_GPC13_VD13      (0x02 << 26)
 328
 329 #define S3C2410_GPC14           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
 330 #define S3C2410_GPC14_VD6       (0x02 << 28)
 331 #define S3C2400_GPC14_VD14      (0x02 << 28)
 332
 333 #define S3C2410_GPC15           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
 334 #define S3C2410_GPC15_VD7       (0x02 << 30)
 335 #define S3C2400_GPC15_VD15      (0x02 << 30)
 336
 337 #define S3C2410_GPC_PUPDIS(x)  (1<<(x))
 338
 339 /*
 340  * S3C2410: Port D consists of 16 GPIO/Special function
 341  *
 342  * almost identical setup to port b, but the special functions are mostly
 343  * to do with the video system's data.
 344  *
 345  * S3C2400: Port D consists of 11 GPIO/Special function
 346  *
 347  * almost identical setup to port c
 348 */
 349
 350 #define S3C2410_GPDCON     S3C2410_GPIOREG(0x30)
 351 #define S3C2410_GPDDAT     S3C2410_GPIOREG(0x34)
 352 #define S3C2410_GPDUP      S3C2410_GPIOREG(0x38)
 353
 354 #define S3C2400_GPDCON     S3C2410_GPIOREG(0x20)
 355 #define S3C2400_GPDDAT     S3C2410_GPIOREG(0x24)
 356 #define S3C2400_GPDUP      S3C2410_GPIOREG(0x28)
 357
 358 #define S3C2410_GPD0            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
 359 #define S3C2410_GPD0_VD8        (0x02 << 0)
 360 #define S3C2400_GPD0_VFRAME     (0x02 << 0)
 361 #define S3C2442_GPD0_nSPICS1    (0x03 << 0)
 362
 363 #define S3C2410_GPD1            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
 364 #define S3C2410_GPD1_VD9        (0x02 << 2)
 365 #define S3C2400_GPD1_VM         (0x02 << 2)
 366 #define S3C2442_GPD1_SPICLK1    (0x03 << 2)
 367
 368 #define S3C2410_GPD2            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
 369 #define S3C2410_GPD2_VD10       (0x02 << 4)
 370 #define S3C2400_GPD2_VLINE      (0x02 << 4)
 371
 372 #define S3C2410_GPD3            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
 373 #define S3C2410_GPD3_VD11       (0x02 << 6)
 374 #define S3C2400_GPD3_VCLK       (0x02 << 6)
 375
 376 #define S3C2410_GPD4            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
 377 #define S3C2410_GPD4_VD12       (0x02 << 8)
 378 #define S3C2400_GPD4_LEND       (0x02 << 8)
 379
 380 #define S3C2410_GPD5            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
 381 #define S3C2410_GPD5_VD13       (0x02 << 10)
 382 #define S3C2400_GPD5_TOUT0      (0x02 << 10)
 383
 384 #define S3C2410_GPD6            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
 385 #define S3C2410_GPD6_VD14       (0x02 << 12)
 386 #define S3C2400_GPD6_TOUT1      (0x02 << 12)
 387
 388 #define S3C2410_GPD7            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
 389 #define S3C2410_GPD7_VD15       (0x02 << 14)
 390 #define S3C2400_GPD7_TOUT2      (0x02 << 14)
 391
 392 #define S3C2410_GPD8            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
 393 #define S3C2410_GPD8_VD16       (0x02 << 16)
 394 #define S3C2400_GPD8_TOUT3      (0x02 << 16)
 395
 396 #define S3C2410_GPD9            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
 397 #define S3C2410_GPD9_VD17       (0x02 << 18)
 398 #define S3C2400_GPD9_TCLK0      (0x02 << 18)
 399 #define S3C2410_GPD9_MASK       (0x03 << 18)
 400
 401 #define S3C2410_GPD10           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
 402 #define S3C2410_GPD10_VD18      (0x02 << 20)
 403 #define S3C2400_GPD10_nWAIT     (0x02 << 20)
 404
 405 #define S3C2410_GPD11           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
 406 #define S3C2410_GPD11_VD19      (0x02 << 22)
 407
 408 #define S3C2410_GPD12           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12)
 409 #define S3C2410_GPD12_VD20      (0x02 << 24)
 410
 411 #define S3C2410_GPD13           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13)
 412 #define S3C2410_GPD13_VD21      (0x02 << 26)
 413
 414 #define S3C2410_GPD14           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14)
 415 #define S3C2410_GPD14_VD22      (0x02 << 28)
 416 #define S3C2410_GPD14_nSS1      (0x03 << 28)
 417
 418 #define S3C2410_GPD15           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
 419 #define S3C2410_GPD15_VD23      (0x02 << 30)
 420 #define S3C2410_GPD15_nSS0      (0x03 << 30)
 421
 422 #define S3C2410_GPD_PUPDIS(x)  (1<<(x))
 423
 424 /* S3C2410:
 425  * Port E consists of 16 GPIO/Special function
 426  *
 427  * again, the same as port B, but dealing with I2S, SDI, and
 428  * more miscellaneous functions
 429  *
 430  * S3C2400:
 431  * Port E consists of 12 GPIO/Special function
 432  *
 433  * GPIO / interrupt inputs
 434 */
 435
 436 #define S3C2410_GPECON     S3C2410_GPIOREG(0x40)
 437 #define S3C2410_GPEDAT     S3C2410_GPIOREG(0x44)
 438 #define S3C2410_GPEUP      S3C2410_GPIOREG(0x48)
 439
 440 #define S3C2400_GPECON     S3C2410_GPIOREG(0x2C)
 441 #define S3C2400_GPEDAT     S3C2410_GPIOREG(0x30)
 442 #define S3C2400_GPEUP      S3C2410_GPIOREG(0x34)
 443
 444 #define S3C2410_GPE0           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
 445 #define S3C2410_GPE0_I2SLRCK   (0x02 << 0)
 446 #define S3C2443_GPE0_AC_nRESET (0x03 << 0)
 447 #define S3C2400_GPE0_EINT0     (0x02 << 0)
 448 #define S3C2410_GPE0_MASK      (0x03 << 0)
 449
 450 #define S3C2410_GPE1           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
 451 #define S3C2410_GPE1_I2SSCLK   (0x02 << 2)
 452 #define S3C2443_GPE1_AC_SYNC   (0x03 << 2)
 453 #define S3C2400_GPE1_EINT1     (0x02 << 2)
 454 #define S3C2400_GPE1_nSS       (0x03 << 2)
 455 #define S3C2410_GPE1_MASK      (0x03 << 2)
 456
 457 #define S3C2410_GPE2           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
 458 #define S3C2410_GPE2_CDCLK     (0x02 << 4)
 459 #define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
 460 #define S3C2400_GPE2_EINT2     (0x02 << 4)
 461 #define S3C2400_GPE2_I2SSDI    (0x03 << 4)
 462
 463 #define S3C2410_GPE3           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
 464 #define S3C2410_GPE3_I2SSDI    (0x02 << 6)
 465 #define S3C2443_GPE3_AC_SDI    (0x03 << 6)
 466 #define S3C2400_GPE3_EINT3     (0x02 << 6)
 467 #define S3C2400_GPE3_nCTS1     (0x03 << 6)
 468 #define S3C2410_GPE3_nSS0      (0x03 << 6)
 469 #define S3C2410_GPE3_MASK      (0x03 << 6)
 470
 471 #define S3C2410_GPE4           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
 472 #define S3C2410_GPE4_I2SSDO    (0x02 << 8)
 473 #define S3C2443_GPE4_AC_SDO    (0x03 << 8)
 474 #define S3C2400_GPE4_EINT4     (0x02 << 8)
 475 #define S3C2400_GPE4_nRTS1     (0x03 << 8)
 476 #define S3C2410_GPE4_I2SSDI    (0x03 << 8)
 477 #define S3C2410_GPE4_MASK      (0x03 << 8)
 478
 479 #define S3C2410_GPE5           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
 480 #define S3C2410_GPE5_SDCLK     (0x02 << 10)
 481 #define S3C2443_GPE5_SD1_CLK   (0x02 << 10)
 482 #define S3C2400_GPE5_EINT5     (0x02 << 10)
 483 #define S3C2400_GPE5_TCLK1     (0x03 << 10)
 484
 485 #define S3C2410_GPE6           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
 486 #define S3C2410_GPE6_SDCMD     (0x02 << 12)
 487 #define S3C2443_GPE6_SD1_CMD   (0x02 << 12)
 488 #define S3C2443_GPE6_AC_BITCLK (0x03 << 12)
 489 #define S3C2400_GPE6_EINT6     (0x02 << 12)
 490
 491 #define S3C2410_GPE7           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
 492 #define S3C2410_GPE7_SDDAT0    (0x02 << 14)
 493 #define S3C2443_GPE5_SD1_DAT0  (0x02 << 14)
 494 #define S3C2443_GPE7_AC_SDI    (0x03 << 14)
 495 #define S3C2400_GPE7_EINT7     (0x02 << 14)
 496
 497 #define S3C2410_GPE8           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
 498 #define S3C2410_GPE8_SDDAT1    (0x02 << 16)
 499 #define S3C2443_GPE8_SD1_DAT1  (0x02 << 16)
 500 #define S3C2443_GPE8_AC_SDO    (0x03 << 16)
 501 #define S3C2400_GPE8_nXDACK0   (0x02 << 16)
 502
 503 #define S3C2410_GPE9           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
 504 #define S3C2410_GPE9_SDDAT2    (0x02 << 18)
 505 #define S3C2443_GPE9_SD1_DAT2  (0x02 << 18)
 506 #define S3C2443_GPE9_AC_SYNC   (0x03 << 18)
 507 #define S3C2400_GPE9_nXDACK1   (0x02 << 18)
 508 #define S3C2400_GPE9_nXBACK    (0x03 << 18)
 509
 510 #define S3C2410_GPE10          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
 511 #define S3C2410_GPE10_SDDAT3   (0x02 << 20)
 512 #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
 513 #define S3C2443_GPE10_AC_nRESET (0x03 << 20)
 514 #define S3C2400_GPE10_nXDREQ0  (0x02 << 20)
 515
 516 #define S3C2410_GPE11          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
 517 #define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
 518 #define S3C2400_GPE11_nXDREQ1  (0x02 << 22)
 519 #define S3C2400_GPE11_nXBREQ   (0x03 << 22)
 520
 521 #define S3C2410_GPE12          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
 522 #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
 523
 524 #define S3C2410_GPE13          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13)
 525 #define S3C2410_GPE13_SPICLK0  (0x02 << 26)
 526
 527 #define S3C2410_GPE14          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14)
 528 #define S3C2410_GPE14_IICSCL   (0x02 << 28)
 529 #define S3C2410_GPE14_MASK     (0x03 << 28)
 530
 531 #define S3C2410_GPE15          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15)
 532 #define S3C2410_GPE15_IICSDA   (0x02 << 30)
 533 #define S3C2410_GPE15_MASK     (0x03 << 30)
 534
 535 #define S3C2440_GPE0_ACSYNC    (0x03 << 0)
 536 #define S3C2440_GPE1_ACBITCLK  (0x03 << 2)
 537 #define S3C2440_GPE2_ACRESET   (0x03 << 4)
 538 #define S3C2440_GPE3_ACIN      (0x03 << 6)
 539 #define S3C2440_GPE4_ACOUT     (0x03 << 8)
 540
 541 #define S3C2410_GPE_PUPDIS(x)  (1<<(x))
 542
 543 /* S3C2410:
 544  * Port F consists of 8 GPIO/Special function
 545  *
 546  * GPIO / interrupt inputs
 547  *
 548  * GPFCON has 2 bits for each of the input pins on port F
 549  *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
 550  *
 551  * pull up works like all other ports.
 552  *
 553  * S3C2400:
 554  * Port F consists of 7 GPIO/Special function
 555  *
 556  * GPIO/serial/misc pins
 557 */
 558
 559 #define S3C2410_GPFCON     S3C2410_GPIOREG(0x50)
 560 #define S3C2410_GPFDAT     S3C2410_GPIOREG(0x54)
 561 #define S3C2410_GPFUP      S3C2410_GPIOREG(0x58)
 562
 563 #define S3C2400_GPFCON     S3C2410_GPIOREG(0x38)
 564 #define S3C2400_GPFDAT     S3C2410_GPIOREG(0x3C)
 565 #define S3C2400_GPFUP      S3C2410_GPIOREG(0x40)
 566
 567 #define S3C2410_GPF0        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
 568 #define S3C2410_GPF0_EINT0  (0x02 << 0)
 569 #define S3C2400_GPF0_RXD0   (0x02 << 0)
 570
 571 #define S3C2410_GPF1        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
 572 #define S3C2410_GPF1_EINT1  (0x02 << 2)
 573 #define S3C2400_GPF1_RXD1   (0x02 << 2)
 574 #define S3C2400_GPF1_IICSDA (0x03 << 2)
 575
 576 #define S3C2410_GPF2        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
 577 #define S3C2410_GPF2_EINT2  (0x02 << 4)
 578 #define S3C2400_GPF2_TXD0   (0x02 << 4)
 579
 580 #define S3C2410_GPF3        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
 581 #define S3C2410_GPF3_EINT3  (0x02 << 6)
 582 #define S3C2400_GPF3_TXD1   (0x02 << 6)
 583 #define S3C2400_GPF3_IICSCL (0x03 << 6)
 584
 585 #define S3C2410_GPF4        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
 586 #define S3C2410_GPF4_EINT4  (0x02 << 8)
 587 #define S3C2400_GPF4_nRTS0  (0x02 << 8)
 588 #define S3C2400_GPF4_nXBACK (0x03 << 8)
 589
 590 #define S3C2410_GPF5        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
 591 #define S3C2410_GPF5_EINT5  (0x02 << 10)
 592 #define S3C2400_GPF5_nCTS0  (0x02 << 10)
 593 #define S3C2400_GPF5_nXBREQ (0x03 << 10)
 594
 595 #define S3C2410_GPF6        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
 596 #define S3C2410_GPF6_EINT6  (0x02 << 12)
 597 #define S3C2400_GPF6_CLKOUT (0x02 << 12)
 598
 599 #define S3C2410_GPF7        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
 600 #define S3C2410_GPF7_EINT7  (0x02 << 14)
 601
 602 #define S3C2410_GPF_PUPDIS(x)  (1<<(x))
 603
 604 /* S3C2410:
 605  * Port G consists of 8 GPIO/IRQ/Special function
 606  *
 607  * GPGCON has 2 bits for each of the input pins on port F
 608  *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
 609  *
 610  * pull up works like all other ports.
 611  *
 612  * S3C2400:
 613  * Port G consists of 10 GPIO/Special function
 614 */
 615
 616 #define S3C2410_GPGCON     S3C2410_GPIOREG(0x60)
 617 #define S3C2410_GPGDAT     S3C2410_GPIOREG(0x64)
 618 #define S3C2410_GPGUP      S3C2410_GPIOREG(0x68)
 619
 620 #define S3C2400_GPGCON     S3C2410_GPIOREG(0x44)
 621 #define S3C2400_GPGDAT     S3C2410_GPIOREG(0x48)
 622 #define S3C2400_GPGUP      S3C2410_GPIOREG(0x4C)
 623
 624 #define S3C2410_GPG0          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
 625 #define S3C2410_GPG0_EINT8    (0x02 << 0)
 626 #define S3C2400_GPG0_I2SLRCK  (0x02 << 0)
 627
 628 #define S3C2410_GPG1          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
 629 #define S3C2410_GPG1_EINT9    (0x02 << 2)
 630 #define S3C2400_GPG1_I2SSCLK  (0x02 << 2)
 631
 632 #define S3C2410_GPG2          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
 633 #define S3C2410_GPG2_EINT10   (0x02 << 4)
 634 #define S3C2410_GPG2_nSS0     (0x03 << 4)
 635 #define S3C2400_GPG2_CDCLK    (0x02 << 4)
 636
 637 #define S3C2410_GPG3          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
 638 #define S3C2410_GPG3_EINT11   (0x02 << 6)
 639 #define S3C2410_GPG3_nSS1     (0x03 << 6)
 640 #define S3C2400_GPG3_I2SSDO   (0x02 << 6)
 641 #define S3C2400_GPG3_I2SSDI   (0x03 << 6)
 642
 643 #define S3C2410_GPG4          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
 644 #define S3C2410_GPG4_EINT12   (0x02 << 8)
 645 #define S3C2400_GPG4_MMCCLK   (0x02 << 8)
 646 #define S3C2400_GPG4_I2SSDI   (0x03 << 8)
 647 #define S3C2410_GPG4_LCDPWREN (0x03 << 8)
 648 #define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
 649
 650 #define S3C2410_GPG5          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
 651 #define S3C2410_GPG5_EINT13   (0x02 << 10)
 652 #define S3C2400_GPG5_MMCCMD   (0x02 << 10)
 653 #define S3C2400_GPG5_IICSDA   (0x03 << 10)
 654 #define S3C2410_GPG5_SPIMISO1 (0x03 << 10)      /* not s3c2443 */
 655
 656 #define S3C2410_GPG6          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
 657 #define S3C2410_GPG6_EINT14   (0x02 << 12)
 658 #define S3C2400_GPG6_MMCDAT   (0x02 << 12)
 659 #define S3C2400_GPG6_IICSCL   (0x03 << 12)
 660 #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
 661
 662 #define S3C2410_GPG7          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
 663 #define S3C2410_GPG7_EINT15   (0x02 << 14)
 664 #define S3C2410_GPG7_SPICLK1  (0x03 << 14)
 665 #define S3C2400_GPG7_SPIMISO  (0x02 << 14)
 666 #define S3C2400_GPG7_IICSDA   (0x03 << 14)
 667
 668 #define S3C2410_GPG8          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
 669 #define S3C2410_GPG8_EINT16   (0x02 << 16)
 670 #define S3C2400_GPG8_SPIMOSI  (0x02 << 16)
 671 #define S3C2400_GPG8_IICSCL   (0x03 << 16)
 672
 673 #define S3C2410_GPG9          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
 674 #define S3C2410_GPG9_EINT17   (0x02 << 18)
 675 #define S3C2400_GPG9_SPICLK   (0x02 << 18)
 676 #define S3C2400_GPG9_MMCCLK   (0x03 << 18)
 677
 678 #define S3C2410_GPG10         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
 679 #define S3C2410_GPG10_EINT18  (0x02 << 20)
 680
 681 #define S3C2410_GPG11         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11)
 682 #define S3C2410_GPG11_EINT19  (0x02 << 22)
 683 #define S3C2410_GPG11_TCLK1   (0x03 << 22)
 684 #define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
 685
 686 #define S3C2410_GPG12         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)
 687 #define S3C2410_GPG12_EINT20  (0x02 << 24)
 688 #define S3C2410_GPG12_XMON    (0x03 << 24)
 689 #define S3C2442_GPG12_nSPICS0 (0x03 << 24)
 690 #define S3C2443_GPG12_nINPACK (0x03 << 24)
 691
 692 #define S3C2410_GPG13         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
 693 #define S3C2410_GPG13_EINT21  (0x02 << 26)
 694 #define S3C2410_GPG13_nXPON   (0x03 << 26)
 695 #define S3C2443_GPG13_CF_nREG (0x03 << 26)
 696
 697 #define S3C2410_GPG14         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)
 698 #define S3C2410_GPG14_EINT22  (0x02 << 28)
 699 #define S3C2410_GPG14_YMON    (0x03 << 28)
 700 #define S3C2443_GPG14_CF_RESET (0x03 << 28)
 701
 702 #define S3C2410_GPG15         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)
 703 #define S3C2410_GPG15_EINT23  (0x02 << 30)
 704 #define S3C2410_GPG15_nYPON   (0x03 << 30)
 705 #define S3C2443_GPG15_CF_PWR  (0x03 << 30)
 706
 707 #define S3C2410_GPG_PUPDIS(x)  (1<<(x))
 708
 709 /* Port H consists of11 GPIO/serial/Misc pins
 710  *
 711  * GPGCON has 2 bits for each of the input pins on port F
 712  *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
 713  *
 714  * pull up works like all other ports.
 715 */
 716
 717 #define S3C2410_GPHCON     S3C2410_GPIOREG(0x70)
 718 #define S3C2410_GPHDAT     S3C2410_GPIOREG(0x74)
 719 #define S3C2410_GPHUP      S3C2410_GPIOREG(0x78)
 720
 721 #define S3C2410_GPH0        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0)
 722 #define S3C2410_GPH0_nCTS0  (0x02 << 0)
 723
 724 #define S3C2410_GPH1        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1)
 725 #define S3C2410_GPH1_nRTS0  (0x02 << 2)
 726
 727 #define S3C2410_GPH2        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2)
 728 #define S3C2410_GPH2_TXD0   (0x02 << 4)
 729
 730 #define S3C2410_GPH3        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3)
 731 #define S3C2410_GPH3_RXD0   (0x02 << 6)
 732
 733 #define S3C2410_GPH4        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4)
 734 #define S3C2410_GPH4_TXD1   (0x02 << 8)
 735
 736 #define S3C2410_GPH5        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5)
 737 #define S3C2410_GPH5_RXD1   (0x02 << 10)
 738
 739 #define S3C2410_GPH6        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6)
 740 #define S3C2410_GPH6_TXD2   (0x02 << 12)
 741 #define S3C2410_GPH6_nRTS1  (0x03 << 12)
 742
 743 #define S3C2410_GPH7        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7)
 744 #define S3C2410_GPH7_RXD2   (0x02 << 14)
 745 #define S3C2410_GPH7_nCTS1  (0x03 << 14)
 746
 747 #define S3C2410_GPH8        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8)
 748 #define S3C2410_GPH8_UCLK   (0x02 << 16)
 749
 750 #define S3C2410_GPH9          S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9)
 751 #define S3C2410_GPH9_CLKOUT0  (0x02 << 18)
 752 #define S3C2442_GPH9_nSPICS0  (0x03 << 18)
 753
 754 #define S3C2410_GPH10         S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
 755 #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
 756
 757 /* The S3C2412 and S3C2413 move the GPJ register set to after
 758  * GPH, which means all registers after 0x80 are now offset by 0x10
 759  * for the 2412/2413 from the 2410/2440/2442
 760 */
 761
 762 /* miscellaneous control */
 763 #define S3C2400_MISCCR     S3C2410_GPIOREG(0x54)
 764 #define S3C2410_MISCCR     S3C2410_GPIOREG(0x80)
 765 #define S3C2410_DCLKCON    S3C2410_GPIOREG(0x84)
 766
 767 #define S3C24XX_DCLKCON    S3C24XX_GPIOREG2(0x84)
 768
 769 /* see clock.h for dclk definitions */
 770
 771 /* pullup control on databus */
 772 #define S3C2410_MISCCR_SPUCR_HEN    (0<<0)
 773 #define S3C2410_MISCCR_SPUCR_HDIS   (1<<0)
 774 #define S3C2410_MISCCR_SPUCR_LEN    (0<<1)
 775 #define S3C2410_MISCCR_SPUCR_LDIS   (1<<1)
 776
 777 #define S3C2400_MISCCR_SPUCR_LEN    (0<<0)
 778 #define S3C2400_MISCCR_SPUCR_LDIS   (1<<0)
 779 #define S3C2400_MISCCR_SPUCR_HEN    (0<<1)
 780 #define S3C2400_MISCCR_SPUCR_HDIS   (1<<1)
 781
 782 #define S3C2400_MISCCR_HZ_STOPEN    (0<<2)
 783 #define S3C2400_MISCCR_HZ_STOPPREV  (1<<2)
 784
 785 #define S3C2410_MISCCR_USBDEV       (0<<3)
 786 #define S3C2410_MISCCR_USBHOST      (1<<3)
 787
 788 #define S3C2410_MISCCR_CLK0_MPLL    (0<<4)
 789 #define S3C2410_MISCCR_CLK0_UPLL    (1<<4)
 790 #define S3C2410_MISCCR_CLK0_FCLK    (2<<4)
 791 #define S3C2410_MISCCR_CLK0_HCLK    (3<<4)
 792 #define S3C2410_MISCCR_CLK0_PCLK    (4<<4)
 793 #define S3C2410_MISCCR_CLK0_DCLK0   (5<<4)
 794 #define S3C2410_MISCCR_CLK0_MASK    (7<<4)
 795
 796 #define S3C2412_MISCCR_CLK0_RTC     (2<<4)
 797
 798 #define S3C2410_MISCCR_CLK1_MPLL    (0<<8)
 799 #define S3C2410_MISCCR_CLK1_UPLL    (1<<8)
 800 #define S3C2410_MISCCR_CLK1_FCLK    (2<<8)
 801 #define S3C2410_MISCCR_CLK1_HCLK    (3<<8)
 802 #define S3C2410_MISCCR_CLK1_PCLK    (4<<8)
 803 #define S3C2410_MISCCR_CLK1_DCLK1   (5<<8)
 804 #define S3C2410_MISCCR_CLK1_MASK    (7<<8)
 805
 806 #define S3C2412_MISCCR_CLK1_CLKsrc  (0<<8)
 807
 808 #define S3C2410_MISCCR_USBSUSPND0   (1<<12)
 809 #define S3C2410_MISCCR_USBSUSPND1   (1<<13)
 810
 811 #define S3C2410_MISCCR_nRSTCON      (1<<16)
 812
 813 #define S3C2410_MISCCR_nEN_SCLK0    (1<<17)
 814 #define S3C2410_MISCCR_nEN_SCLK1    (1<<18)
 815 #define S3C2410_MISCCR_nEN_SCLKE    (1<<19)     /* not 2412 */
 816 #define S3C2410_MISCCR_SDSLEEP      (7<<17)
 817
 818 /* external interrupt control... */
 819 /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
 820  * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
 821  * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
 822  *
 823  * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
 824  *
 825  * Samsung datasheet p9-25
 826 */
 827 #define S3C2400_EXTINT0    S3C2410_GPIOREG(0x58)
 828 #define S3C2410_EXTINT0    S3C2410_GPIOREG(0x88)
 829 #define S3C2410_EXTINT1    S3C2410_GPIOREG(0x8C)
 830 #define S3C2410_EXTINT2    S3C2410_GPIOREG(0x90)
 831
 832 #define S3C24XX_EXTINT0    S3C24XX_GPIOREG2(0x88)
 833 #define S3C24XX_EXTINT1    S3C24XX_GPIOREG2(0x8C)
 834 #define S3C24XX_EXTINT2    S3C24XX_GPIOREG2(0x90)
 835
 836 /* interrupt filtering conrrol for EINT16..EINT23 */
 837 #define S3C2410_EINFLT0    S3C2410_GPIOREG(0x94)
 838 #define S3C2410_EINFLT1    S3C2410_GPIOREG(0x98)
 839 #define S3C2410_EINFLT2    S3C2410_GPIOREG(0x9C)
 840 #define S3C2410_EINFLT3    S3C2410_GPIOREG(0xA0)
 841
 842 #define S3C24XX_EINFLT0    S3C24XX_GPIOREG2(0x94)
 843 #define S3C24XX_EINFLT1    S3C24XX_GPIOREG2(0x98)
 844 #define S3C24XX_EINFLT2    S3C24XX_GPIOREG2(0x9C)
 845 #define S3C24XX_EINFLT3    S3C24XX_GPIOREG2(0xA0)
 846
 847 /* values for interrupt filtering */
 848 #define S3C2410_EINTFLT_PCLK            (0x00)
 849 #define S3C2410_EINTFLT_EXTCLK          (1<<7)
 850 #define S3C2410_EINTFLT_WIDTHMSK(x)     ((x) & 0x3f)
 851
 852 /* removed EINTxxxx defs from here, not meant for this */
 853
 854 /* GSTATUS have miscellaneous information in them
 855  *
 856  * These move between s3c2410 and s3c2412 style systems.
 857  */
 858
 859 #define S3C2410_GSTATUS0   S3C2410_GPIOREG(0x0AC)
 860 #define S3C2410_GSTATUS1   S3C2410_GPIOREG(0x0B0)
 861 #define S3C2410_GSTATUS2   S3C2410_GPIOREG(0x0B4)
 862 #define S3C2410_GSTATUS3   S3C2410_GPIOREG(0x0B8)
 863 #define S3C2410_GSTATUS4   S3C2410_GPIOREG(0x0BC)
 864
 865 #define S3C2412_GSTATUS0   S3C2410_GPIOREG(0x0BC)
 866 #define S3C2412_GSTATUS1   S3C2410_GPIOREG(0x0C0)
 867 #define S3C2412_GSTATUS2   S3C2410_GPIOREG(0x0C4)
 868 #define S3C2412_GSTATUS3   S3C2410_GPIOREG(0x0C8)
 869 #define S3C2412_GSTATUS4   S3C2410_GPIOREG(0x0CC)
 870
 871 #define S3C24XX_GSTATUS0   S3C24XX_GPIOREG2(0x0AC)
 872 #define S3C24XX_GSTATUS1   S3C24XX_GPIOREG2(0x0B0)
 873 #define S3C24XX_GSTATUS2   S3C24XX_GPIOREG2(0x0B4)
 874 #define S3C24XX_GSTATUS3   S3C24XX_GPIOREG2(0x0B8)
 875 #define S3C24XX_GSTATUS4   S3C24XX_GPIOREG2(0x0BC)
 876
 877 #define S3C2410_GSTATUS0_nWAIT     (1<<3)
 878 #define S3C2410_GSTATUS0_NCON      (1<<2)
 879 #define S3C2410_GSTATUS0_RnB       (1<<1)
 880 #define S3C2410_GSTATUS0_nBATTFLT  (1<<0)
 881
 882 #define S3C2410_GSTATUS1_IDMASK    (0xffff0000)
 883 #define S3C2410_GSTATUS1_2410      (0x32410000)
 884 #define S3C2410_GSTATUS1_2412      (0x32412001)
 885 #define S3C2410_GSTATUS1_2440      (0x32440000)
 886 #define S3C2410_GSTATUS1_2442      (0x32440aaa)
 887
 888 #define S3C2410_GSTATUS2_WTRESET   (1<<2)
 889 #define S3C2410_GSTATUS2_OFFRESET  (1<<1)
 890 #define S3C2410_GSTATUS2_PONRESET  (1<<0)
 891
 892 /* open drain control register */
 893 #define S3C2400_OPENCR     S3C2410_GPIOREG(0x50)
 894
 895 #define S3C2400_OPENCR_OPC_RXD1DIS  (0<<0)
 896 #define S3C2400_OPENCR_OPC_RXD1EN   (1<<0)
 897 #define S3C2400_OPENCR_OPC_TXD1DIS  (0<<1)
 898 #define S3C2400_OPENCR_OPC_TXD1EN   (1<<1)
 899 #define S3C2400_OPENCR_OPC_CMDDIS   (0<<2)
 900 #define S3C2400_OPENCR_OPC_CMDEN    (1<<2)
 901 #define S3C2400_OPENCR_OPC_DATDIS   (0<<3)
 902 #define S3C2400_OPENCR_OPC_DATEN    (1<<3)
 903 #define S3C2400_OPENCR_OPC_MISODIS  (0<<4)
 904 #define S3C2400_OPENCR_OPC_MISOEN   (1<<4)
 905 #define S3C2400_OPENCR_OPC_MOSIDIS  (0<<5)
 906 #define S3C2400_OPENCR_OPC_MOSIEN   (1<<5)
 907
 908 /* 2412/2413 sleep configuration registers */
 909
 910 #define S3C2412_GPBSLPCON       S3C2410_GPIOREG(0x1C)
 911 #define S3C2412_GPCSLPCON       S3C2410_GPIOREG(0x2C)
 912 #define S3C2412_GPDSLPCON       S3C2410_GPIOREG(0x3C)
 913 #define S3C2412_GPFSLPCON       S3C2410_GPIOREG(0x5C)
 914 #define S3C2412_GPGSLPCON       S3C2410_GPIOREG(0x6C)
 915 #define S3C2412_GPHSLPCON       S3C2410_GPIOREG(0x7C)
 916
 917 /* definitions for each pin bit */
 918 #define S3C2412_GPIO_SLPCON_LOW  ( 0x00 )
 919 #define S3C2412_GPIO_SLPCON_HIGH ( 0x01 )
 920 #define S3C2412_GPIO_SLPCON_IN   ( 0x02 )
 921 #define S3C2412_GPIO_SLPCON_PULL ( 0x03 )
 922
 923 #define S3C2412_SLPCON_LOW(x)   ( 0x00 << ((x) * 2))
 924 #define S3C2412_SLPCON_HIGH(x)  ( 0x01 << ((x) * 2))
 925 #define S3C2412_SLPCON_IN(x)    ( 0x02 << ((x) * 2))
 926 #define S3C2412_SLPCON_PULL(x)  ( 0x03 << ((x) * 2))
 927 #define S3C2412_SLPCON_EINT(x)  ( 0x02 << ((x) * 2))  /* only IRQ pins */
 928 #define S3C2412_SLPCON_MASK(x)  ( 0x03 << ((x) * 2))
 929
 930 #define S3C2412_SLPCON_ALL_LOW  (0x0)
 931 #define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444)
 932 #define S3C2412_SLPCON_ALL_IN   (0x22222222 | 0x88888888)
 933 #define S3C2412_SLPCON_ALL_PULL (0x33333333)
 934
 935 #endif  /* __ASM_ARCH_REGS_GPIO_H */
 936