arch/arm/mach-s3c2410/include/mach/regs-gpio.h

   1 /* arch/arm/mach-s3c2410/include/mach/regs-gpio.h
   2  *
   3  * Copyright (c) 2003-2004 Simtec Electronics <linux@simtec.co.uk>
   4  *      http://www.simtec.co.uk/products/SWLINUX/
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * S3C2410 GPIO register definitions
  11 */
  12
  13
  14 #ifndef __ASM_ARCH_REGS_GPIO_H
  15 #define __ASM_ARCH_REGS_GPIO_H
  16
  17 #include <mach/gpio-nrs.h>
  18
  19 #define S3C24XX_MISCCR          S3C24XX_GPIOREG2(0x80)
  20
  21 /* general configuration options */
  22
  23 #define S3C2410_GPIO_LEAVE   (0xFFFFFFFF)
  24 #define S3C2410_GPIO_INPUT   (0xFFFFFFF0)       /* not available on A */
  25 #define S3C2410_GPIO_OUTPUT  (0xFFFFFFF1)
  26 #define S3C2410_GPIO_IRQ     (0xFFFFFFF2)       /* not available for all */
  27 #define S3C2410_GPIO_SFN2    (0xFFFFFFF2)       /* bank A => addr/cs/nand */
  28 #define S3C2410_GPIO_SFN3    (0xFFFFFFF3)       /* not available on A */
  29
  30 /* register address for the GPIO registers.
  31  * S3C24XX_GPIOREG2 is for the second set of registers in the
  32  * GPIO which move between s3c2410 and s3c2412 type systems */
  33
  34 #define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
  35 #define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
  36
  37
  38 /* configure GPIO ports A..G */
  39
  40 /* port A - S3C2410: 22bits, zero in bit X makes pin X output
  41  * 1 makes port special function, this is default
  42 */
  43 #define S3C2410_GPACON     S3C2410_GPIOREG(0x00)
  44 #define S3C2410_GPADAT     S3C2410_GPIOREG(0x04)
  45
  46 #define S3C2410_GPA0_ADDR0   (1<<0)
  47 #define S3C2410_GPA1_ADDR16  (1<<1)
  48 #define S3C2410_GPA2_ADDR17  (1<<2)
  49 #define S3C2410_GPA3_ADDR18  (1<<3)
  50 #define S3C2410_GPA4_ADDR19  (1<<4)
  51 #define S3C2410_GPA5_ADDR20  (1<<5)
  52 #define S3C2410_GPA6_ADDR21  (1<<6)
  53 #define S3C2410_GPA7_ADDR22  (1<<7)
  54 #define S3C2410_GPA8_ADDR23  (1<<8)
  55 #define S3C2410_GPA9_ADDR24  (1<<9)
  56 #define S3C2410_GPA10_ADDR25 (1<<10)
  57 #define S3C2410_GPA11_ADDR26 (1<<11)
  58 #define S3C2410_GPA12_nGCS1  (1<<12)
  59 #define S3C2410_GPA13_nGCS2  (1<<13)
  60 #define S3C2410_GPA14_nGCS3  (1<<14)
  61 #define S3C2410_GPA15_nGCS4  (1<<15)
  62 #define S3C2410_GPA16_nGCS5  (1<<16)
  63 #define S3C2410_GPA17_CLE    (1<<17)
  64 #define S3C2410_GPA18_ALE    (1<<18)
  65 #define S3C2410_GPA19_nFWE   (1<<19)
  66 #define S3C2410_GPA20_nFRE   (1<<20)
  67 #define S3C2410_GPA21_nRSTOUT (1<<21)
  68 #define S3C2410_GPA22_nFCE   (1<<22)
  69
  70 /* 0x08 and 0x0c are reserved on S3C2410 */
  71
  72 /* S3C2410:
  73  * GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
  74  *   00 = input, 01 = output, 10=special function, 11=reserved
  75
  76  * bit 0,1 = pin 0, 2,3= pin 1...
  77  *
  78  * CPBUP = pull up resistor control, 1=disabled, 0=enabled
  79 */
  80
  81 #define S3C2410_GPBCON     S3C2410_GPIOREG(0x10)
  82 #define S3C2410_GPBDAT     S3C2410_GPIOREG(0x14)
  83 #define S3C2410_GPBUP      S3C2410_GPIOREG(0x18)
  84
  85 /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
  86
  87 #define S3C2410_GPB0_TOUT0   (0x02 << 0)
  88
  89 #define S3C2410_GPB1_TOUT1   (0x02 << 2)
  90
  91 #define S3C2410_GPB2_TOUT2   (0x02 << 4)
  92
  93 #define S3C2410_GPB3_TOUT3   (0x02 << 6)
  94
  95 #define S3C2410_GPB4_TCLK0   (0x02 << 8)
  96 #define S3C2410_GPB4_MASK    (0x03 << 8)
  97
  98 #define S3C2410_GPB5_nXBACK  (0x02 << 10)
  99 #define S3C2443_GPB5_XBACK   (0x03 << 10)
 100
 101 #define S3C2410_GPB6_nXBREQ  (0x02 << 12)
 102 #define S3C2443_GPB6_XBREQ   (0x03 << 12)
 103
 104 #define S3C2410_GPB7_nXDACK1 (0x02 << 14)
 105 #define S3C2443_GPB7_XDACK1  (0x03 << 14)
 106
 107 #define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
 108
 109 #define S3C2410_GPB9_nXDACK0 (0x02 << 18)
 110 #define S3C2443_GPB9_XDACK0  (0x03 << 18)
 111
 112 #define S3C2410_GPB10_nXDRE0 (0x02 << 20)
 113 #define S3C2443_GPB10_XDREQ0 (0x03 << 20)
 114
 115 #define S3C2410_GPB_PUPDIS(x)  (1<<(x))
 116
 117 /* Port C consits of 16 GPIO/Special function
 118  *
 119  * almost identical setup to port b, but the special functions are mostly
 120  * to do with the video system's sync/etc.
 121 */
 122
 123 #define S3C2410_GPCCON     S3C2410_GPIOREG(0x20)
 124 #define S3C2410_GPCDAT     S3C2410_GPIOREG(0x24)
 125 #define S3C2410_GPCUP      S3C2410_GPIOREG(0x28)
 126 #define S3C2410_GPC0_LEND       (0x02 << 0)
 127 #define S3C2410_GPC1_VCLK       (0x02 << 2)
 128 #define S3C2410_GPC2_VLINE      (0x02 << 4)
 129 #define S3C2410_GPC3_VFRAME     (0x02 << 6)
 130 #define S3C2410_GPC4_VM         (0x02 << 8)
 131 #define S3C2410_GPC5_LCDVF0     (0x02 << 10)
 132 #define S3C2410_GPC6_LCDVF1     (0x02 << 12)
 133 #define S3C2410_GPC7_LCDVF2     (0x02 << 14)
 134 #define S3C2410_GPC8_VD0        (0x02 << 16)
 135 #define S3C2410_GPC9_VD1        (0x02 << 18)
 136 #define S3C2410_GPC10_VD2       (0x02 << 20)
 137 #define S3C2410_GPC11_VD3       (0x02 << 22)
 138 #define S3C2410_GPC12_VD4       (0x02 << 24)
 139 #define S3C2410_GPC13_VD5       (0x02 << 26)
 140 #define S3C2410_GPC14_VD6       (0x02 << 28)
 141 #define S3C2410_GPC15_VD7       (0x02 << 30)
 142 #define S3C2410_GPC_PUPDIS(x)  (1<<(x))
 143
 144 /*
 145  * S3C2410: Port D consists of 16 GPIO/Special function
 146  *
 147  * almost identical setup to port b, but the special functions are mostly
 148  * to do with the video system's data.
 149  *
 150  * almost identical setup to port c
 151 */
 152
 153 #define S3C2410_GPDCON     S3C2410_GPIOREG(0x30)
 154 #define S3C2410_GPDDAT     S3C2410_GPIOREG(0x34)
 155 #define S3C2410_GPDUP      S3C2410_GPIOREG(0x38)
 156
 157 #define S3C2410_GPD0_VD8        (0x02 << 0)
 158 #define S3C2442_GPD0_nSPICS1    (0x03 << 0)
 159
 160 #define S3C2410_GPD1_VD9        (0x02 << 2)
 161 #define S3C2442_GPD1_SPICLK1    (0x03 << 2)
 162
 163 #define S3C2410_GPD2_VD10       (0x02 << 4)
 164
 165 #define S3C2410_GPD3_VD11       (0x02 << 6)
 166
 167 #define S3C2410_GPD4_VD12       (0x02 << 8)
 168
 169 #define S3C2410_GPD5_VD13       (0x02 << 10)
 170
 171 #define S3C2410_GPD6_VD14       (0x02 << 12)
 172
 173 #define S3C2410_GPD7_VD15       (0x02 << 14)
 174
 175 #define S3C2410_GPD8_VD16       (0x02 << 16)
 176 #define S3C2440_GPD8_SPIMISO1   (0x03 << 16)
 177
 178 #define S3C2410_GPD9_VD17       (0x02 << 18)
 179 #define S3C2440_GPD9_SPIMOSI1   (0x03 << 18)
 180
 181 #define S3C2410_GPD10_VD18      (0x02 << 20)
 182 #define S3C2440_GPD10_SPICLK1   (0x03 << 20)
 183
 184 #define S3C2410_GPD11_VD19      (0x02 << 22)
 185
 186 #define S3C2410_GPD12_VD20      (0x02 << 24)
 187
 188 #define S3C2410_GPD13_VD21      (0x02 << 26)
 189
 190 #define S3C2410_GPD14_VD22      (0x02 << 28)
 191 #define S3C2410_GPD14_nSS1      (0x03 << 28)
 192
 193 #define S3C2410_GPD15_VD23      (0x02 << 30)
 194 #define S3C2410_GPD15_nSS0      (0x03 << 30)
 195
 196 #define S3C2410_GPD_PUPDIS(x)  (1<<(x))
 197
 198 /* S3C2410:
 199  * Port E consists of 16 GPIO/Special function
 200  *
 201  * again, the same as port B, but dealing with I2S, SDI, and
 202  * more miscellaneous functions
 203  *
 204  * GPIO / interrupt inputs
 205 */
 206
 207 #define S3C2410_GPECON     S3C2410_GPIOREG(0x40)
 208 #define S3C2410_GPEDAT     S3C2410_GPIOREG(0x44)
 209 #define S3C2410_GPEUP      S3C2410_GPIOREG(0x48)
 210
 211 #define S3C2410_GPE0_I2SLRCK   (0x02 << 0)
 212 #define S3C2443_GPE0_AC_nRESET (0x03 << 0)
 213 #define S3C2410_GPE0_MASK      (0x03 << 0)
 214
 215 #define S3C2410_GPE1_I2SSCLK   (0x02 << 2)
 216 #define S3C2443_GPE1_AC_SYNC   (0x03 << 2)
 217 #define S3C2410_GPE1_MASK      (0x03 << 2)
 218
 219 #define S3C2410_GPE2_CDCLK     (0x02 << 4)
 220 #define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
 221
 222 #define S3C2410_GPE3_I2SSDI    (0x02 << 6)
 223 #define S3C2443_GPE3_AC_SDI    (0x03 << 6)
 224 #define S3C2410_GPE3_nSS0      (0x03 << 6)
 225 #define S3C2410_GPE3_MASK      (0x03 << 6)
 226
 227 #define S3C2410_GPE4_I2SSDO    (0x02 << 8)
 228 #define S3C2443_GPE4_AC_SDO    (0x03 << 8)
 229 #define S3C2410_GPE4_I2SSDI    (0x03 << 8)
 230 #define S3C2410_GPE4_MASK      (0x03 << 8)
 231
 232 #define S3C2410_GPE5_SDCLK     (0x02 << 10)
 233 #define S3C2443_GPE5_SD1_CLK   (0x02 << 10)
 234 #define S3C2443_GPE5_AC_BITCLK (0x03 << 10)
 235
 236 #define S3C2410_GPE6_SDCMD     (0x02 << 12)
 237 #define S3C2443_GPE6_SD1_CMD   (0x02 << 12)
 238 #define S3C2443_GPE6_AC_SDI    (0x03 << 12)
 239
 240 #define S3C2410_GPE7_SDDAT0    (0x02 << 14)
 241 #define S3C2443_GPE5_SD1_DAT0  (0x02 << 14)
 242 #define S3C2443_GPE7_AC_SDO    (0x03 << 14)
 243
 244 #define S3C2410_GPE8_SDDAT1    (0x02 << 16)
 245 #define S3C2443_GPE8_SD1_DAT1  (0x02 << 16)
 246 #define S3C2443_GPE8_AC_SYNC   (0x03 << 16)
 247
 248 #define S3C2410_GPE9_SDDAT2    (0x02 << 18)
 249 #define S3C2443_GPE9_SD1_DAT2  (0x02 << 18)
 250 #define S3C2443_GPE9_AC_nRESET (0x03 << 18)
 251
 252 #define S3C2410_GPE10_SDDAT3   (0x02 << 20)
 253 #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
 254
 255 #define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
 256
 257 #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
 258
 259 #define S3C2410_GPE13_SPICLK0  (0x02 << 26)
 260
 261 #define S3C2410_GPE14_IICSCL   (0x02 << 28)
 262 #define S3C2410_GPE14_MASK     (0x03 << 28)
 263
 264 #define S3C2410_GPE15_IICSDA   (0x02 << 30)
 265 #define S3C2410_GPE15_MASK     (0x03 << 30)
 266
 267 #define S3C2440_GPE0_ACSYNC    (0x03 << 0)
 268 #define S3C2440_GPE1_ACBITCLK  (0x03 << 2)
 269 #define S3C2440_GPE2_ACRESET   (0x03 << 4)
 270 #define S3C2440_GPE3_ACIN      (0x03 << 6)
 271 #define S3C2440_GPE4_ACOUT     (0x03 << 8)
 272
 273 #define S3C2410_GPE_PUPDIS(x)  (1<<(x))
 274
 275 /* S3C2410:
 276  * Port F consists of 8 GPIO/Special function
 277  *
 278  * GPIO / interrupt inputs
 279  *
 280  * GPFCON has 2 bits for each of the input pins on port F
 281  *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
 282  *
 283  * pull up works like all other ports.
 284  *
 285  * GPIO/serial/misc pins
 286 */
 287
 288 #define S3C2410_GPFCON     S3C2410_GPIOREG(0x50)
 289 #define S3C2410_GPFDAT     S3C2410_GPIOREG(0x54)
 290 #define S3C2410_GPFUP      S3C2410_GPIOREG(0x58)
 291
 292 #define S3C2410_GPF0_EINT0  (0x02 << 0)
 293 #define S3C2410_GPF1_EINT1  (0x02 << 2)
 294 #define S3C2410_GPF2_EINT2  (0x02 << 4)
 295 #define S3C2410_GPF3_EINT3  (0x02 << 6)
 296 #define S3C2410_GPF4_EINT4  (0x02 << 8)
 297 #define S3C2410_GPF5_EINT5  (0x02 << 10)
 298 #define S3C2410_GPF6_EINT6  (0x02 << 12)
 299 #define S3C2410_GPF7_EINT7  (0x02 << 14)
 300 #define S3C2410_GPF_PUPDIS(x)  (1<<(x))
 301
 302 /* S3C2410:
 303  * Port G consists of 8 GPIO/IRQ/Special function
 304  *
 305  * GPGCON has 2 bits for each of the input pins on port F
 306  *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
 307  *
 308  * pull up works like all other ports.
 309 */
 310
 311 #define S3C2410_GPGCON     S3C2410_GPIOREG(0x60)
 312 #define S3C2410_GPGDAT     S3C2410_GPIOREG(0x64)
 313 #define S3C2410_GPGUP      S3C2410_GPIOREG(0x68)
 314
 315 #define S3C2410_GPG0_EINT8    (0x02 << 0)
 316
 317 #define S3C2410_GPG1_EINT9    (0x02 << 2)
 318
 319 #define S3C2410_GPG2_EINT10   (0x02 << 4)
 320 #define S3C2410_GPG2_nSS0     (0x03 << 4)
 321
 322 #define S3C2410_GPG3_EINT11   (0x02 << 6)
 323 #define S3C2410_GPG3_nSS1     (0x03 << 6)
 324
 325 #define S3C2410_GPG4_EINT12   (0x02 << 8)
 326 #define S3C2410_GPG4_LCDPWREN (0x03 << 8)
 327 #define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
 328
 329 #define S3C2410_GPG5_EINT13   (0x02 << 10)
 330 #define S3C2410_GPG5_SPIMISO1 (0x03 << 10)      /* not s3c2443 */
 331
 332 #define S3C2410_GPG6_EINT14   (0x02 << 12)
 333 #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
 334
 335 #define S3C2410_GPG7_EINT15   (0x02 << 14)
 336 #define S3C2410_GPG7_SPICLK1  (0x03 << 14)
 337
 338 #define S3C2410_GPG8_EINT16   (0x02 << 16)
 339
 340 #define S3C2410_GPG9_EINT17   (0x02 << 18)
 341
 342 #define S3C2410_GPG10_EINT18  (0x02 << 20)
 343
 344 #define S3C2410_GPG11_EINT19  (0x02 << 22)
 345 #define S3C2410_GPG11_TCLK1   (0x03 << 22)
 346 #define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
 347
 348 #define S3C2410_GPG12_EINT20  (0x02 << 24)
 349 #define S3C2410_GPG12_XMON    (0x03 << 24)
 350 #define S3C2442_GPG12_nSPICS0 (0x03 << 24)
 351 #define S3C2443_GPG12_nINPACK (0x03 << 24)
 352
 353 #define S3C2410_GPG13_EINT21  (0x02 << 26)
 354 #define S3C2410_GPG13_nXPON   (0x03 << 26)
 355 #define S3C2443_GPG13_CF_nREG (0x03 << 26)
 356
 357 #define S3C2410_GPG14_EINT22  (0x02 << 28)
 358 #define S3C2410_GPG14_YMON    (0x03 << 28)
 359 #define S3C2443_GPG14_CF_RESET (0x03 << 28)
 360
 361 #define S3C2410_GPG15_EINT23  (0x02 << 30)
 362 #define S3C2410_GPG15_nYPON   (0x03 << 30)
 363 #define S3C2443_GPG15_CF_PWR  (0x03 << 30)
 364
 365 #define S3C2410_GPG_PUPDIS(x)  (1<<(x))
 366
 367 /* Port H consists of11 GPIO/serial/Misc pins
 368  *
 369  * GPGCON has 2 bits for each of the input pins on port F
 370  *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
 371  *
 372  * pull up works like all other ports.
 373 */
 374
 375 #define S3C2410_GPHCON     S3C2410_GPIOREG(0x70)
 376 #define S3C2410_GPHDAT     S3C2410_GPIOREG(0x74)
 377 #define S3C2410_GPHUP      S3C2410_GPIOREG(0x78)
 378
 379 #define S3C2410_GPH0_nCTS0  (0x02 << 0)
 380 #define S3C2416_GPH0_TXD0  (0x02 << 0)
 381
 382 #define S3C2410_GPH1_nRTS0  (0x02 << 2)
 383 #define S3C2416_GPH1_RXD0  (0x02 << 2)
 384
 385 #define S3C2410_GPH2_TXD0   (0x02 << 4)
 386 #define S3C2416_GPH2_TXD1   (0x02 << 4)
 387
 388 #define S3C2410_GPH3_RXD0   (0x02 << 6)
 389 #define S3C2416_GPH3_RXD1   (0x02 << 6)
 390
 391 #define S3C2410_GPH4_TXD1   (0x02 << 8)
 392 #define S3C2416_GPH4_TXD2   (0x02 << 8)
 393
 394 #define S3C2410_GPH5_RXD1   (0x02 << 10)
 395 #define S3C2416_GPH5_RXD2   (0x02 << 10)
 396
 397 #define S3C2410_GPH6_TXD2   (0x02 << 12)
 398 #define S3C2416_GPH6_TXD3   (0x02 << 12)
 399 #define S3C2410_GPH6_nRTS1  (0x03 << 12)
 400 #define S3C2416_GPH6_nRTS2  (0x03 << 12)
 401
 402 #define S3C2410_GPH7_RXD2   (0x02 << 14)
 403 #define S3C2416_GPH7_RXD3   (0x02 << 14)
 404 #define S3C2410_GPH7_nCTS1  (0x03 << 14)
 405 #define S3C2416_GPH7_nCTS2  (0x03 << 14)
 406
 407 #define S3C2410_GPH8_UCLK   (0x02 << 16)
 408 #define S3C2416_GPH8_nCTS0  (0x02 << 16)
 409
 410 #define S3C2410_GPH9_CLKOUT0  (0x02 << 18)
 411 #define S3C2442_GPH9_nSPICS0  (0x03 << 18)
 412 #define S3C2416_GPH9_nRTS0    (0x02 << 18)
 413
 414 #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
 415 #define S3C2416_GPH10_nCTS1   (0x02 << 20)
 416
 417 #define S3C2416_GPH11_nRTS1   (0x02 << 22)
 418
 419 #define S3C2416_GPH12_EXTUARTCLK (0x02 << 24)
 420
 421 #define S3C2416_GPH13_CLKOUT0 (0x02 << 26)
 422
 423 #define S3C2416_GPH14_CLKOUT1 (0x02 << 28)
 424
 425 /* The S3C2412 and S3C2413 move the GPJ register set to after
 426  * GPH, which means all registers after 0x80 are now offset by 0x10
 427  * for the 2412/2413 from the 2410/2440/2442
 428 */
 429
 430 /* S3C2443 and above */
 431 #define S3C2440_GPJCON     S3C2410_GPIOREG(0xD0)
 432 #define S3C2440_GPJDAT     S3C2410_GPIOREG(0xD4)
 433 #define S3C2440_GPJUP      S3C2410_GPIOREG(0xD8)
 434
 435 #define S3C2443_GPKCON     S3C2410_GPIOREG(0xE0)
 436 #define S3C2443_GPKDAT     S3C2410_GPIOREG(0xE4)
 437 #define S3C2443_GPKUP      S3C2410_GPIOREG(0xE8)
 438
 439 #define S3C2443_GPLCON     S3C2410_GPIOREG(0xF0)
 440 #define S3C2443_GPLDAT     S3C2410_GPIOREG(0xF4)
 441 #define S3C2443_GPLUP      S3C2410_GPIOREG(0xF8)
 442
 443 #define S3C2443_GPMCON     S3C2410_GPIOREG(0x100)
 444 #define S3C2443_GPMDAT     S3C2410_GPIOREG(0x104)
 445 #define S3C2443_GPMUP      S3C2410_GPIOREG(0x108)
 446
 447 /* miscellaneous control */
 448 #define S3C2410_MISCCR     S3C2410_GPIOREG(0x80)
 449 #define S3C2410_DCLKCON    S3C2410_GPIOREG(0x84)
 450
 451 #define S3C24XX_DCLKCON    S3C24XX_GPIOREG2(0x84)
 452
 453 /* see clock.h for dclk definitions */
 454
 455 /* pullup control on databus */
 456 #define S3C2410_MISCCR_SPUCR_HEN    (0<<0)
 457 #define S3C2410_MISCCR_SPUCR_HDIS   (1<<0)
 458 #define S3C2410_MISCCR_SPUCR_LEN    (0<<1)
 459 #define S3C2410_MISCCR_SPUCR_LDIS   (1<<1)
 460
 461 #define S3C2410_MISCCR_USBDEV       (0<<3)
 462 #define S3C2410_MISCCR_USBHOST      (1<<3)
 463
 464 #define S3C2410_MISCCR_CLK0_MPLL    (0<<4)
 465 #define S3C2410_MISCCR_CLK0_UPLL    (1<<4)
 466 #define S3C2410_MISCCR_CLK0_FCLK    (2<<4)
 467 #define S3C2410_MISCCR_CLK0_HCLK    (3<<4)
 468 #define S3C2410_MISCCR_CLK0_PCLK    (4<<4)
 469 #define S3C2410_MISCCR_CLK0_DCLK0   (5<<4)
 470 #define S3C2410_MISCCR_CLK0_MASK    (7<<4)
 471
 472 #define S3C2412_MISCCR_CLK0_RTC     (2<<4)
 473
 474 #define S3C2410_MISCCR_CLK1_MPLL    (0<<8)
 475 #define S3C2410_MISCCR_CLK1_UPLL    (1<<8)
 476 #define S3C2410_MISCCR_CLK1_FCLK    (2<<8)
 477 #define S3C2410_MISCCR_CLK1_HCLK    (3<<8)
 478 #define S3C2410_MISCCR_CLK1_PCLK    (4<<8)
 479 #define S3C2410_MISCCR_CLK1_DCLK1   (5<<8)
 480 #define S3C2410_MISCCR_CLK1_MASK    (7<<8)
 481
 482 #define S3C2412_MISCCR_CLK1_CLKsrc  (0<<8)
 483
 484 #define S3C2410_MISCCR_USBSUSPND0   (1<<12)
 485 #define S3C2416_MISCCR_SEL_SUSPND   (1<<12)
 486 #define S3C2410_MISCCR_USBSUSPND1   (1<<13)
 487
 488 #define S3C2410_MISCCR_nRSTCON      (1<<16)
 489
 490 #define S3C2410_MISCCR_nEN_SCLK0    (1<<17)
 491 #define S3C2410_MISCCR_nEN_SCLK1    (1<<18)
 492 #define S3C2410_MISCCR_nEN_SCLKE    (1<<19)     /* not 2412 */
 493 #define S3C2410_MISCCR_SDSLEEP      (7<<17)
 494
 495 #define S3C2416_MISCCR_FLT_I2C      (1<<24)
 496 #define S3C2416_MISCCR_HSSPI_EN2    (1<<31)
 497
 498 /* external interrupt control... */
 499 /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
 500  * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
 501  * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
 502  *
 503  * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
 504  *
 505  * Samsung datasheet p9-25
 506 */
 507 #define S3C2410_EXTINT0    S3C2410_GPIOREG(0x88)
 508 #define S3C2410_EXTINT1    S3C2410_GPIOREG(0x8C)
 509 #define S3C2410_EXTINT2    S3C2410_GPIOREG(0x90)
 510
 511 #define S3C24XX_EXTINT0    S3C24XX_GPIOREG2(0x88)
 512 #define S3C24XX_EXTINT1    S3C24XX_GPIOREG2(0x8C)
 513 #define S3C24XX_EXTINT2    S3C24XX_GPIOREG2(0x90)
 514
 515 /* interrupt filtering conrrol for EINT16..EINT23 */
 516 #define S3C2410_EINFLT0    S3C2410_GPIOREG(0x94)
 517 #define S3C2410_EINFLT1    S3C2410_GPIOREG(0x98)
 518 #define S3C2410_EINFLT2    S3C2410_GPIOREG(0x9C)
 519 #define S3C2410_EINFLT3    S3C2410_GPIOREG(0xA0)
 520
 521 #define S3C24XX_EINFLT0    S3C24XX_GPIOREG2(0x94)
 522 #define S3C24XX_EINFLT1    S3C24XX_GPIOREG2(0x98)
 523 #define S3C24XX_EINFLT2    S3C24XX_GPIOREG2(0x9C)
 524 #define S3C24XX_EINFLT3    S3C24XX_GPIOREG2(0xA0)
 525
 526 /* values for interrupt filtering */
 527 #define S3C2410_EINTFLT_PCLK            (0x00)
 528 #define S3C2410_EINTFLT_EXTCLK          (1<<7)
 529 #define S3C2410_EINTFLT_WIDTHMSK(x)     ((x) & 0x3f)
 530
 531 /* removed EINTxxxx defs from here, not meant for this */
 532
 533 /* GSTATUS have miscellaneous information in them
 534  *
 535  * These move between s3c2410 and s3c2412 style systems.
 536  */
 537
 538 #define S3C2410_GSTATUS0   S3C2410_GPIOREG(0x0AC)
 539 #define S3C2410_GSTATUS1   S3C2410_GPIOREG(0x0B0)
 540 #define S3C2410_GSTATUS2   S3C2410_GPIOREG(0x0B4)
 541 #define S3C2410_GSTATUS3   S3C2410_GPIOREG(0x0B8)
 542 #define S3C2410_GSTATUS4   S3C2410_GPIOREG(0x0BC)
 543
 544 #define S3C2412_GSTATUS0   S3C2410_GPIOREG(0x0BC)
 545 #define S3C2412_GSTATUS1   S3C2410_GPIOREG(0x0C0)
 546 #define S3C2412_GSTATUS2   S3C2410_GPIOREG(0x0C4)
 547 #define S3C2412_GSTATUS3   S3C2410_GPIOREG(0x0C8)
 548 #define S3C2412_GSTATUS4   S3C2410_GPIOREG(0x0CC)
 549
 550 #define S3C24XX_GSTATUS0   S3C24XX_GPIOREG2(0x0AC)
 551 #define S3C24XX_GSTATUS1   S3C24XX_GPIOREG2(0x0B0)
 552 #define S3C24XX_GSTATUS2   S3C24XX_GPIOREG2(0x0B4)
 553 #define S3C24XX_GSTATUS3   S3C24XX_GPIOREG2(0x0B8)
 554 #define S3C24XX_GSTATUS4   S3C24XX_GPIOREG2(0x0BC)
 555
 556 #define S3C2410_GSTATUS0_nWAIT     (1<<3)
 557 #define S3C2410_GSTATUS0_NCON      (1<<2)
 558 #define S3C2410_GSTATUS0_RnB       (1<<1)
 559 #define S3C2410_GSTATUS0_nBATTFLT  (1<<0)
 560
 561 #define S3C2410_GSTATUS1_IDMASK    (0xffff0000)
 562 #define S3C2410_GSTATUS1_2410      (0x32410000)
 563 #define S3C2410_GSTATUS1_2412      (0x32412001)
 564 #define S3C2410_GSTATUS1_2416      (0x32416003)
 565 #define S3C2410_GSTATUS1_2440      (0x32440000)
 566 #define S3C2410_GSTATUS1_2442      (0x32440aaa)
 567 /* some 2416 CPUs report this value also */
 568 #define S3C2410_GSTATUS1_2450      (0x32450003)
 569
 570 #define S3C2410_GSTATUS2_WTRESET   (1<<2)
 571 #define S3C2410_GSTATUS2_OFFRESET  (1<<1)
 572 #define S3C2410_GSTATUS2_PONRESET  (1<<0)
 573
 574 /* 2412/2413 sleep configuration registers */
 575
 576 #define S3C2412_GPBSLPCON       S3C2410_GPIOREG(0x1C)
 577 #define S3C2412_GPCSLPCON       S3C2410_GPIOREG(0x2C)
 578 #define S3C2412_GPDSLPCON       S3C2410_GPIOREG(0x3C)
 579 #define S3C2412_GPFSLPCON       S3C2410_GPIOREG(0x5C)
 580 #define S3C2412_GPGSLPCON       S3C2410_GPIOREG(0x6C)
 581 #define S3C2412_GPHSLPCON       S3C2410_GPIOREG(0x7C)
 582
 583 /* definitions for each pin bit */
 584 #define S3C2412_GPIO_SLPCON_LOW  ( 0x00 )
 585 #define S3C2412_GPIO_SLPCON_HIGH ( 0x01 )
 586 #define S3C2412_GPIO_SLPCON_IN   ( 0x02 )
 587 #define S3C2412_GPIO_SLPCON_PULL ( 0x03 )
 588
 589 #define S3C2412_SLPCON_LOW(x)   ( 0x00 << ((x) * 2))
 590 #define S3C2412_SLPCON_HIGH(x)  ( 0x01 << ((x) * 2))
 591 #define S3C2412_SLPCON_IN(x)    ( 0x02 << ((x) * 2))
 592 #define S3C2412_SLPCON_PULL(x)  ( 0x03 << ((x) * 2))
 593 #define S3C2412_SLPCON_EINT(x)  ( 0x02 << ((x) * 2))  /* only IRQ pins */
 594 #define S3C2412_SLPCON_MASK(x)  ( 0x03 << ((x) * 2))
 595
 596 #define S3C2412_SLPCON_ALL_LOW  (0x0)
 597 #define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444)
 598 #define S3C2412_SLPCON_ALL_IN   (0x22222222 | 0x88888888)
 599 #define S3C2412_SLPCON_ALL_PULL (0x33333333)
 600
 601 #endif  /* __ASM_ARCH_REGS_GPIO_H */
 602