projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ARM: BAST: Update mach-bast to use gpiolib API
[deliverable/linux.git] / arch / arm / mach-s3c2410 / mach-bast.c
1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
2 *
3 * Copyright 2003-2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.simtec.co.uk/products/EB2410ITX/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/gpio.h>
20 #include <linux/sysdev.h>
21 #include <linux/serial_core.h>
22 #include <linux/platform_device.h>
23 #include <linux/dm9000.h>
24 #include <linux/ata_platform.h>
25 #include <linux/i2c.h>
26 #include <linux/io.h>
27
28 #include <net/ax88796.h>
29
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32 #include <asm/mach/irq.h>
33
34 #include <mach/bast-map.h>
35 #include <mach/bast-irq.h>
36 #include <mach/bast-cpld.h>
37
38 #include <mach/hardware.h>
39 #include <asm/irq.h>
40 #include <asm/mach-types.h>
41
42 //#include <asm/debug-ll.h>
43 #include <plat/regs-serial.h>
44 #include <mach/regs-gpio.h>
45 #include <mach/regs-mem.h>
46 #include <mach/regs-lcd.h>
47
48 #include <plat/hwmon.h>
49 #include <plat/nand.h>
50 #include <plat/iic.h>
51 #include <mach/fb.h>
52
53 #include <linux/mtd/mtd.h>
54 #include <linux/mtd/nand.h>
55 #include <linux/mtd/nand_ecc.h>
56 #include <linux/mtd/partitions.h>
57
58 #include <linux/serial_8250.h>
59
60 #include <plat/clock.h>
61 #include <plat/devs.h>
62 #include <plat/cpu.h>
63 #include <plat/cpu-freq.h>
64 #include <plat/audio-simtec.h>
65
66 #include "usb-simtec.h"
67 #include "nor-simtec.h"
68
69 #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
70
71 /* macros for virtual address mods for the io space entries */
72 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
73 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
74 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
75 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
76
77 /* macros to modify the physical addresses for io space */
78
79 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
80 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
81 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
82 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
83
84 static struct map_desc bast_iodesc[] __initdata = {
85 /* ISA IO areas */
86 {
87 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
88 .pfn = PA_CS2(BAST_PA_ISAIO),
89 .length = SZ_16M,
90 .type = MT_DEVICE,
91 }, {
92 .virtual = (u32)S3C24XX_VA_ISA_WORD,
93 .pfn = PA_CS3(BAST_PA_ISAIO),
94 .length = SZ_16M,
95 .type = MT_DEVICE,
96 },
97 /* bast CPLD control registers, and external interrupt controls */
98 {
99 .virtual = (u32)BAST_VA_CTRL1,
100 .pfn = __phys_to_pfn(BAST_PA_CTRL1),
101 .length = SZ_1M,
102 .type = MT_DEVICE,
103 }, {
104 .virtual = (u32)BAST_VA_CTRL2,
105 .pfn = __phys_to_pfn(BAST_PA_CTRL2),
106 .length = SZ_1M,
107 .type = MT_DEVICE,
108 }, {
109 .virtual = (u32)BAST_VA_CTRL3,
110 .pfn = __phys_to_pfn(BAST_PA_CTRL3),
111 .length = SZ_1M,
112 .type = MT_DEVICE,
113 }, {
114 .virtual = (u32)BAST_VA_CTRL4,
115 .pfn = __phys_to_pfn(BAST_PA_CTRL4),
116 .length = SZ_1M,
117 .type = MT_DEVICE,
118 },
119 /* PC104 IRQ mux */
120 {
121 .virtual = (u32)BAST_VA_PC104_IRQREQ,
122 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
123 .length = SZ_1M,
124 .type = MT_DEVICE,
125 }, {
126 .virtual = (u32)BAST_VA_PC104_IRQRAW,
127 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
128 .length = SZ_1M,
129 .type = MT_DEVICE,
130 }, {
131 .virtual = (u32)BAST_VA_PC104_IRQMASK,
132 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
133 .length = SZ_1M,
134 .type = MT_DEVICE,
135 },
136
137 /* peripheral space... one for each of fast/slow/byte/16bit */
138 /* note, ide is only decoded in word space, even though some registers
139 * are only 8bit */
140
141 /* slow, byte */
142 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
143 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
144 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
145
146 /* slow, word */
147 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
148 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
149 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
150
151 /* fast, byte */
152 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
153 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
154 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
155
156 /* fast, word */
157 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
158 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
159 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
160 };
161
162 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
163 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
164 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
165
166 static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
167 [0] = {
168 .name = "uclk",
169 .divisor = 1,
170 .min_baud = 0,
171 .max_baud = 0,
172 },
173 [1] = {
174 .name = "pclk",
175 .divisor = 1,
176 .min_baud = 0,
177 .max_baud = 0,
178 }
179 };
180
181
182 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
183 [0] = {
184 .hwport = 0,
185 .flags = 0,
186 .ucon = UCON,
187 .ulcon = ULCON,
188 .ufcon = UFCON,
189 .clocks = bast_serial_clocks,
190 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
191 },
192 [1] = {
193 .hwport = 1,
194 .flags = 0,
195 .ucon = UCON,
196 .ulcon = ULCON,
197 .ufcon = UFCON,
198 .clocks = bast_serial_clocks,
199 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
200 },
201 /* port 2 is not actually used */
202 [2] = {
203 .hwport = 2,
204 .flags = 0,
205 .ucon = UCON,
206 .ulcon = ULCON,
207 .ufcon = UFCON,
208 .clocks = bast_serial_clocks,
209 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
210 }
211 };
212
213 /* NAND Flash on BAST board */
214
215 #ifdef CONFIG_PM
216 static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
217 {
218 /* ensure that an nRESET is not generated on resume. */
219 gpio_direction_output(S3C2410_GPA(21), 1);
220 return 0;
221 }
222
223 static int bast_pm_resume(struct sys_device *sd)
224 {
225 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
226 return 0;
227 }
228
229 #else
230 #define bast_pm_suspend NULL
231 #define bast_pm_resume NULL
232 #endif
233
234 static struct sysdev_class bast_pm_sysclass = {
235 .name = "mach-bast",
236 .suspend = bast_pm_suspend,
237 .resume = bast_pm_resume,
238 };
239
240 static struct sys_device bast_pm_sysdev = {
241 .cls = &bast_pm_sysclass,
242 };
243
244 static int smartmedia_map[] = { 0 };
245 static int chip0_map[] = { 1 };
246 static int chip1_map[] = { 2 };
247 static int chip2_map[] = { 3 };
248
249 static struct mtd_partition __initdata bast_default_nand_part[] = {
250 [0] = {
251 .name = "Boot Agent",
252 .size = SZ_16K,
253 .offset = 0,
254 },
255 [1] = {
256 .name = "/boot",
257 .size = SZ_4M - SZ_16K,
258 .offset = SZ_16K,
259 },
260 [2] = {
261 .name = "user",
262 .offset = SZ_4M,
263 .size = MTDPART_SIZ_FULL,
264 }
265 };
266
267 /* the bast has 4 selectable slots for nand-flash, the three
268 * on-board chip areas, as well as the external SmartMedia
269 * slot.
270 *
271 * Note, there is no current hot-plug support for the SmartMedia
272 * socket.
273 */
274
275 static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
276 [0] = {
277 .name = "SmartMedia",
278 .nr_chips = 1,
279 .nr_map = smartmedia_map,
280 .options = NAND_SCAN_SILENT_NODEV,
281 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
282 .partitions = bast_default_nand_part,
283 },
284 [1] = {
285 .name = "chip0",
286 .nr_chips = 1,
287 .nr_map = chip0_map,
288 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
289 .partitions = bast_default_nand_part,
290 },
291 [2] = {
292 .name = "chip1",
293 .nr_chips = 1,
294 .nr_map = chip1_map,
295 .options = NAND_SCAN_SILENT_NODEV,
296 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
297 .partitions = bast_default_nand_part,
298 },
299 [3] = {
300 .name = "chip2",
301 .nr_chips = 1,
302 .nr_map = chip2_map,
303 .options = NAND_SCAN_SILENT_NODEV,
304 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
305 .partitions = bast_default_nand_part,
306 }
307 };
308
309 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
310 {
311 unsigned int tmp;
312
313 slot = set->nr_map[slot] & 3;
314
315 pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
316 slot, set, set->nr_map);
317
318 tmp = __raw_readb(BAST_VA_CTRL2);
319 tmp &= BAST_CPLD_CTLR2_IDERST;
320 tmp |= slot;
321 tmp |= BAST_CPLD_CTRL2_WNAND;
322
323 pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
324
325 __raw_writeb(tmp, BAST_VA_CTRL2);
326 }
327
328 static struct s3c2410_platform_nand __initdata bast_nand_info = {
329 .tacls = 30,
330 .twrph0 = 60,
331 .twrph1 = 60,
332 .nr_sets = ARRAY_SIZE(bast_nand_sets),
333 .sets = bast_nand_sets,
334 .select_chip = bast_nand_select,
335 };
336
337 /* DM9000 */
338
339 static struct resource bast_dm9k_resource[] = {
340 [0] = {
341 .start = S3C2410_CS5 + BAST_PA_DM9000,
342 .end = S3C2410_CS5 + BAST_PA_DM9000 + 3,
343 .flags = IORESOURCE_MEM,
344 },
345 [1] = {
346 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
347 .end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
348 .flags = IORESOURCE_MEM,
349 },
350 [2] = {
351 .start = IRQ_DM9000,
352 .end = IRQ_DM9000,
353 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
354 }
355
356 };
357
358 /* for the moment we limit ourselves to 16bit IO until some
359 * better IO routines can be written and tested
360 */
361
362 static struct dm9000_plat_data bast_dm9k_platdata = {
363 .flags = DM9000_PLATF_16BITONLY,
364 };
365
366 static struct platform_device bast_device_dm9k = {
367 .name = "dm9000",
368 .id = 0,
369 .num_resources = ARRAY_SIZE(bast_dm9k_resource),
370 .resource = bast_dm9k_resource,
371 .dev = {
372 .platform_data = &bast_dm9k_platdata,
373 }
374 };
375
376 /* serial devices */
377
378 #define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
379 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
380 #define SERIAL_CLK (1843200)
381
382 static struct plat_serial8250_port bast_sio_data[] = {
383 [0] = {
384 .mapbase = SERIAL_BASE + 0x2f8,
385 .irq = IRQ_PCSERIAL1,
386 .flags = SERIAL_FLAGS,
387 .iotype = UPIO_MEM,
388 .regshift = 0,
389 .uartclk = SERIAL_CLK,
390 },
391 [1] = {
392 .mapbase = SERIAL_BASE + 0x3f8,
393 .irq = IRQ_PCSERIAL2,
394 .flags = SERIAL_FLAGS,
395 .iotype = UPIO_MEM,
396 .regshift = 0,
397 .uartclk = SERIAL_CLK,
398 },
399 { }
400 };
401
402 static struct platform_device bast_sio = {
403 .name = "serial8250",
404 .id = PLAT8250_DEV_PLATFORM,
405 .dev = {
406 .platform_data = &bast_sio_data,
407 },
408 };
409
410 /* we have devices on the bus which cannot work much over the
411 * standard 100KHz i2c bus frequency
412 */
413
414 static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
415 .flags = 0,
416 .slave_addr = 0x10,
417 .frequency = 100*1000,
418 };
419
420 /* Asix AX88796 10/100 ethernet controller */
421
422 static struct ax_plat_data bast_asix_platdata = {
423 .flags = AXFLG_MAC_FROMDEV,
424 .wordlength = 2,
425 .dcr_val = 0x48,
426 .rcr_val = 0x40,
427 };
428
429 static struct resource bast_asix_resource[] = {
430 [0] = {
431 .start = S3C2410_CS5 + BAST_PA_ASIXNET,
432 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
433 .flags = IORESOURCE_MEM,
434 },
435 [1] = {
436 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
437 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
438 .flags = IORESOURCE_MEM,
439 },
440 [2] = {
441 .start = IRQ_ASIX,
442 .end = IRQ_ASIX,
443 .flags = IORESOURCE_IRQ
444 }
445 };
446
447 static struct platform_device bast_device_asix = {
448 .name = "ax88796",
449 .id = 0,
450 .num_resources = ARRAY_SIZE(bast_asix_resource),
451 .resource = bast_asix_resource,
452 .dev = {
453 .platform_data = &bast_asix_platdata
454 }
455 };
456
457 /* Asix AX88796 10/100 ethernet controller parallel port */
458
459 static struct resource bast_asixpp_resource[] = {
460 [0] = {
461 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
462 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
463 .flags = IORESOURCE_MEM,
464 }
465 };
466
467 static struct platform_device bast_device_axpp = {
468 .name = "ax88796-pp",
469 .id = 0,
470 .num_resources = ARRAY_SIZE(bast_asixpp_resource),
471 .resource = bast_asixpp_resource,
472 };
473
474 /* LCD/VGA controller */
475
476 static struct s3c2410fb_display __initdata bast_lcd_info[] = {
477 {
478 .type = S3C2410_LCDCON1_TFT,
479 .width = 640,
480 .height = 480,
481
482 .pixclock = 33333,
483 .xres = 640,
484 .yres = 480,
485 .bpp = 4,
486 .left_margin = 40,
487 .right_margin = 20,
488 .hsync_len = 88,
489 .upper_margin = 30,
490 .lower_margin = 32,
491 .vsync_len = 3,
492
493 .lcdcon5 = 0x00014b02,
494 },
495 {
496 .type = S3C2410_LCDCON1_TFT,
497 .width = 640,
498 .height = 480,
499
500 .pixclock = 33333,
501 .xres = 640,
502 .yres = 480,
503 .bpp = 8,
504 .left_margin = 40,
505 .right_margin = 20,
506 .hsync_len = 88,
507 .upper_margin = 30,
508 .lower_margin = 32,
509 .vsync_len = 3,
510
511 .lcdcon5 = 0x00014b02,
512 },
513 {
514 .type = S3C2410_LCDCON1_TFT,
515 .width = 640,
516 .height = 480,
517
518 .pixclock = 33333,
519 .xres = 640,
520 .yres = 480,
521 .bpp = 16,
522 .left_margin = 40,
523 .right_margin = 20,
524 .hsync_len = 88,
525 .upper_margin = 30,
526 .lower_margin = 32,
527 .vsync_len = 3,
528
529 .lcdcon5 = 0x00014b02,
530 },
531 };
532
533 /* LCD/VGA controller */
534
535 static struct s3c2410fb_mach_info __initdata bast_fb_info = {
536
537 .displays = bast_lcd_info,
538 .num_displays = ARRAY_SIZE(bast_lcd_info),
539 .default_display = 1,
540 };
541
542 /* I2C devices fitted. */
543
544 static struct i2c_board_info bast_i2c_devs[] __initdata = {
545 {
546 I2C_BOARD_INFO("tlv320aic23", 0x1a),
547 }, {
548 I2C_BOARD_INFO("simtec-pmu", 0x6b),
549 }, {
550 I2C_BOARD_INFO("ch7013", 0x75),
551 },
552 };
553
554 static struct s3c_hwmon_pdata bast_hwmon_info = {
555 /* LCD contrast (0-6.6V) */
556 .in[0] = &(struct s3c_hwmon_chcfg) {
557 .name = "lcd-contrast",
558 .mult = 3300,
559 .div = 512,
560 },
561 /* LED current feedback */
562 .in[1] = &(struct s3c_hwmon_chcfg) {
563 .name = "led-feedback",
564 .mult = 3300,
565 .div = 1024,
566 },
567 /* LCD feedback (0-6.6V) */
568 .in[2] = &(struct s3c_hwmon_chcfg) {
569 .name = "lcd-feedback",
570 .mult = 3300,
571 .div = 512,
572 },
573 /* Vcore (1.8-2.0V), Vref 3.3V */
574 .in[3] = &(struct s3c_hwmon_chcfg) {
575 .name = "vcore",
576 .mult = 3300,
577 .div = 1024,
578 },
579 };
580
581 /* Standard BAST devices */
582 // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
583
584 static struct platform_device *bast_devices[] __initdata = {
585 &s3c_device_ohci,
586 &s3c_device_lcd,
587 &s3c_device_wdt,
588 &s3c_device_i2c0,
589 &s3c_device_rtc,
590 &s3c_device_nand,
591 &s3c_device_adc,
592 &s3c_device_hwmon,
593 &bast_device_dm9k,
594 &bast_device_asix,
595 &bast_device_axpp,
596 &bast_sio,
597 };
598
599 static struct clk *bast_clocks[] __initdata = {
600 &s3c24xx_dclk0,
601 &s3c24xx_dclk1,
602 &s3c24xx_clkout0,
603 &s3c24xx_clkout1,
604 &s3c24xx_uclk,
605 };
606
607 static struct s3c_cpufreq_board __initdata bast_cpufreq = {
608 .refresh = 7800, /* 7.8usec */
609 .auto_io = 1,
610 .need_io = 1,
611 };
612
613 static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
614 .have_mic = 1,
615 .have_lout = 1,
616 };
617
618 static void __init bast_map_io(void)
619 {
620 /* initialise the clocks */
621
622 s3c24xx_dclk0.parent = &clk_upll;
623 s3c24xx_dclk0.rate = 12*1000*1000;
624
625 s3c24xx_dclk1.parent = &clk_upll;
626 s3c24xx_dclk1.rate = 24*1000*1000;
627
628 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
629 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
630
631 s3c24xx_uclk.parent = &s3c24xx_clkout1;
632
633 s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
634
635 s3c_device_hwmon.dev.platform_data = &bast_hwmon_info;
636
637 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
638 s3c24xx_init_clocks(0);
639 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
640 }
641
642 static void __init bast_init(void)
643 {
644 sysdev_class_register(&bast_pm_sysclass);
645 sysdev_register(&bast_pm_sysdev);
646
647 s3c_i2c0_set_platdata(&bast_i2c_info);
648 s3c_nand_set_platdata(&bast_nand_info);
649 s3c24xx_fb_set_platdata(&bast_fb_info);
650 platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
651
652 i2c_register_board_info(0, bast_i2c_devs,
653 ARRAY_SIZE(bast_i2c_devs));
654
655 usb_simtec_init();
656 nor_simtec_init();
657 simtec_audio_add(NULL, true, &bast_audio);
658
659 WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
660
661 s3c_cpufreq_setboard(&bast_cpufreq);
662 }
663
664 MACHINE_START(BAST, "Simtec-BAST")
665 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
666 .phys_io = S3C2410_PA_UART,
667 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
668 .boot_params = S3C2410_SDRAM_PA + 0x100,
669 .map_io = bast_map_io,
670 .init_irq = s3c24xx_init_irq,
671 .init_machine = bast_init,
672 .timer = &s3c24xx_timer,
673 MACHINE_END
Linux kernel - Deliverables
This page took 0.094178 seconds and 5 git commands to generate.