1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * http://www.simtec.co.uk/products/EB2410ITX/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * 14-Sep-2004 BJD USB power control
14 * 20-Aug-2004 BJD Added s3c2410_board struct
15 * 18-Aug-2004 BJD Added platform devices from default set
16 * 16-May-2003 BJD Created initial version
17 * 16-Aug-2003 BJD Fixed header files and copyright, added URL
18 * 05-Sep-2003 BJD Moved to v2.6 kernel
19 * 06-Jan-2003 BJD Updates for <arch/map.h>
20 * 18-Jan-2003 BJD Added serial port configuration
21 * 05-Oct-2004 BJD Power management code
22 * 04-Nov-2004 BJD Updated serial port clocks
23 * 04-Jan-2005 BJD New uart init call
24 * 10-Jan-2005 BJD Removed include of s3c2410.h
25 * 14-Jan-2005 BJD Add support for muitlple NAND devices
26 * 03-Mar-2005 BJD Ensured that bast-cpld.h is included
27 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
28 * 14-Mar-2005 BJD Updated for __iomem changes
29 * 22-Jun-2005 BJD Added DM9000 platform information
30 * 28-Jun-2005 BJD Moved pm functionality out to common code
31 * 17-Jul-2005 BJD Changed to platform device for SuperIO 16550s
32 * 25-Jul-2005 BJD Removed ASIX static mappings
33 * 27-Jul-2005 BJD Ensure maximum frequency of i2c bus
36 #include <linux/kernel.h>
37 #include <linux/types.h>
38 #include <linux/interrupt.h>
39 #include <linux/list.h>
40 #include <linux/timer.h>
41 #include <linux/init.h>
42 #include <linux/device.h>
43 #include <linux/dm9000.h>
45 #include <asm/mach/arch.h>
46 #include <asm/mach/map.h>
47 #include <asm/mach/irq.h>
49 #include <asm/arch/bast-map.h>
50 #include <asm/arch/bast-irq.h>
51 #include <asm/arch/bast-cpld.h>
53 #include <asm/hardware.h>
56 #include <asm/mach-types.h>
58 //#include <asm/debug-ll.h>
59 #include <asm/arch/regs-serial.h>
60 #include <asm/arch/regs-gpio.h>
61 #include <asm/arch/regs-mem.h>
62 #include <asm/arch/regs-lcd.h>
63 #include <asm/arch/nand.h>
64 #include <asm/arch/iic.h>
66 #include <linux/mtd/mtd.h>
67 #include <linux/mtd/nand.h>
68 #include <linux/mtd/nand_ecc.h>
69 #include <linux/mtd/partitions.h>
71 #include <linux/serial_8250.h>
76 #include "usb-simtec.h"
78 #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
80 /* macros for virtual address mods for the io space entries */
81 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
82 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
83 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
84 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
86 /* macros to modify the physical addresses for io space */
88 #define PA_CS2(item) ((item) + S3C2410_CS2)
89 #define PA_CS3(item) ((item) + S3C2410_CS3)
90 #define PA_CS4(item) ((item) + S3C2410_CS4)
91 #define PA_CS5(item) ((item) + S3C2410_CS5)
93 static struct map_desc bast_iodesc
[] __initdata
= {
96 { (u32
)S3C24XX_VA_ISA_BYTE
, PA_CS2(BAST_PA_ISAIO
), SZ_16M
, MT_DEVICE
},
97 { (u32
)S3C24XX_VA_ISA_WORD
, PA_CS3(BAST_PA_ISAIO
), SZ_16M
, MT_DEVICE
},
99 /* we could possibly compress the next set down into a set of smaller tables
100 * pagetables, but that would mean using an L2 section, and it still means
101 * we cannot actually feed the same register to an LDR due to 16K spacing
104 /* bast CPLD control registers, and external interrupt controls */
105 { (u32
)BAST_VA_CTRL1
, BAST_PA_CTRL1
, SZ_1M
, MT_DEVICE
},
106 { (u32
)BAST_VA_CTRL2
, BAST_PA_CTRL2
, SZ_1M
, MT_DEVICE
},
107 { (u32
)BAST_VA_CTRL3
, BAST_PA_CTRL3
, SZ_1M
, MT_DEVICE
},
108 { (u32
)BAST_VA_CTRL4
, BAST_PA_CTRL4
, SZ_1M
, MT_DEVICE
},
111 { (u32
)BAST_VA_PC104_IRQREQ
, BAST_PA_PC104_IRQREQ
, SZ_1M
, MT_DEVICE
},
112 { (u32
)BAST_VA_PC104_IRQRAW
, BAST_PA_PC104_IRQRAW
, SZ_1M
, MT_DEVICE
},
113 { (u32
)BAST_VA_PC104_IRQMASK
, BAST_PA_PC104_IRQMASK
, SZ_1M
, MT_DEVICE
},
115 /* peripheral space... one for each of fast/slow/byte/16bit */
116 /* note, ide is only decoded in word space, even though some registers
120 { VA_C2(BAST_VA_ISAIO
), PA_CS2(BAST_PA_ISAIO
), SZ_16M
, MT_DEVICE
},
121 { VA_C2(BAST_VA_ISAMEM
), PA_CS2(BAST_PA_ISAMEM
), SZ_16M
, MT_DEVICE
},
122 { VA_C2(BAST_VA_SUPERIO
), PA_CS2(BAST_PA_SUPERIO
), SZ_1M
, MT_DEVICE
},
123 { VA_C2(BAST_VA_IDEPRI
), PA_CS3(BAST_PA_IDEPRI
), SZ_1M
, MT_DEVICE
},
124 { VA_C2(BAST_VA_IDESEC
), PA_CS3(BAST_PA_IDESEC
), SZ_1M
, MT_DEVICE
},
125 { VA_C2(BAST_VA_IDEPRIAUX
), PA_CS3(BAST_PA_IDEPRIAUX
), SZ_1M
, MT_DEVICE
},
126 { VA_C2(BAST_VA_IDESECAUX
), PA_CS3(BAST_PA_IDESECAUX
), SZ_1M
, MT_DEVICE
},
129 { VA_C3(BAST_VA_ISAIO
), PA_CS3(BAST_PA_ISAIO
), SZ_16M
, MT_DEVICE
},
130 { VA_C3(BAST_VA_ISAMEM
), PA_CS3(BAST_PA_ISAMEM
), SZ_16M
, MT_DEVICE
},
131 { VA_C3(BAST_VA_SUPERIO
), PA_CS3(BAST_PA_SUPERIO
), SZ_1M
, MT_DEVICE
},
132 { VA_C3(BAST_VA_IDEPRI
), PA_CS3(BAST_PA_IDEPRI
), SZ_1M
, MT_DEVICE
},
133 { VA_C3(BAST_VA_IDESEC
), PA_CS3(BAST_PA_IDESEC
), SZ_1M
, MT_DEVICE
},
134 { VA_C3(BAST_VA_IDEPRIAUX
), PA_CS3(BAST_PA_IDEPRIAUX
), SZ_1M
, MT_DEVICE
},
135 { VA_C3(BAST_VA_IDESECAUX
), PA_CS3(BAST_PA_IDESECAUX
), SZ_1M
, MT_DEVICE
},
138 { VA_C4(BAST_VA_ISAIO
), PA_CS4(BAST_PA_ISAIO
), SZ_16M
, MT_DEVICE
},
139 { VA_C4(BAST_VA_ISAMEM
), PA_CS4(BAST_PA_ISAMEM
), SZ_16M
, MT_DEVICE
},
140 { VA_C4(BAST_VA_SUPERIO
), PA_CS4(BAST_PA_SUPERIO
), SZ_1M
, MT_DEVICE
},
141 { VA_C4(BAST_VA_IDEPRI
), PA_CS5(BAST_PA_IDEPRI
), SZ_1M
, MT_DEVICE
},
142 { VA_C4(BAST_VA_IDESEC
), PA_CS5(BAST_PA_IDESEC
), SZ_1M
, MT_DEVICE
},
143 { VA_C4(BAST_VA_IDEPRIAUX
), PA_CS5(BAST_PA_IDEPRIAUX
), SZ_1M
, MT_DEVICE
},
144 { VA_C4(BAST_VA_IDESECAUX
), PA_CS5(BAST_PA_IDESECAUX
), SZ_1M
, MT_DEVICE
},
147 { VA_C5(BAST_VA_ISAIO
), PA_CS5(BAST_PA_ISAIO
), SZ_16M
, MT_DEVICE
},
148 { VA_C5(BAST_VA_ISAMEM
), PA_CS5(BAST_PA_ISAMEM
), SZ_16M
, MT_DEVICE
},
149 { VA_C5(BAST_VA_SUPERIO
), PA_CS5(BAST_PA_SUPERIO
), SZ_1M
, MT_DEVICE
},
150 { VA_C5(BAST_VA_IDEPRI
), PA_CS5(BAST_PA_IDEPRI
), SZ_1M
, MT_DEVICE
},
151 { VA_C5(BAST_VA_IDESEC
), PA_CS5(BAST_PA_IDESEC
), SZ_1M
, MT_DEVICE
},
152 { VA_C5(BAST_VA_IDEPRIAUX
), PA_CS5(BAST_PA_IDEPRIAUX
), SZ_1M
, MT_DEVICE
},
153 { VA_C5(BAST_VA_IDESECAUX
), PA_CS5(BAST_PA_IDESECAUX
), SZ_1M
, MT_DEVICE
},
156 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
157 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
158 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
160 static struct s3c24xx_uart_clksrc bast_serial_clocks
[] = {
176 static struct s3c2410_uartcfg bast_uartcfgs
[] = {
183 .clocks
= bast_serial_clocks
,
184 .clocks_size
= ARRAY_SIZE(bast_serial_clocks
)
192 .clocks
= bast_serial_clocks
,
193 .clocks_size
= ARRAY_SIZE(bast_serial_clocks
)
195 /* port 2 is not actually used */
202 .clocks
= bast_serial_clocks
,
203 .clocks_size
= ARRAY_SIZE(bast_serial_clocks
)
207 /* NOR Flash on BAST board */
209 static struct resource bast_nor_resource
[] = {
211 .start
= S3C2410_CS1
+ 0x4000000,
212 .end
= S3C2410_CS1
+ 0x4000000 + (32*1024*1024) - 1,
213 .flags
= IORESOURCE_MEM
,
217 static struct platform_device bast_device_nor
= {
220 .num_resources
= ARRAY_SIZE(bast_nor_resource
),
221 .resource
= bast_nor_resource
,
224 /* NAND Flash on BAST board */
227 static int smartmedia_map
[] = { 0 };
228 static int chip0_map
[] = { 1 };
229 static int chip1_map
[] = { 2 };
230 static int chip2_map
[] = { 3 };
232 struct mtd_partition bast_default_nand_part
[] = {
234 .name
= "Boot Agent",
240 .size
= SZ_4M
- SZ_16K
,
246 .size
= MTDPART_SIZ_FULL
,
250 /* the bast has 4 selectable slots for nand-flash, the three
251 * on-board chip areas, as well as the external SmartMedia
254 * Note, there is no current hot-plug support for the SmartMedia
258 static struct s3c2410_nand_set bast_nand_sets
[] = {
260 .name
= "SmartMedia",
262 .nr_map
= smartmedia_map
,
263 .nr_partitions
= ARRAY_SIZE(bast_default_nand_part
),
264 .partitions
= bast_default_nand_part
270 .nr_partitions
= ARRAY_SIZE(bast_default_nand_part
),
271 .partitions
= bast_default_nand_part
277 .nr_partitions
= ARRAY_SIZE(bast_default_nand_part
),
278 .partitions
= bast_default_nand_part
284 .nr_partitions
= ARRAY_SIZE(bast_default_nand_part
),
285 .partitions
= bast_default_nand_part
289 static void bast_nand_select(struct s3c2410_nand_set
*set
, int slot
)
293 slot
= set
->nr_map
[slot
] & 3;
295 pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
296 slot
, set
, set
->nr_map
);
298 tmp
= __raw_readb(BAST_VA_CTRL2
);
299 tmp
&= BAST_CPLD_CTLR2_IDERST
;
301 tmp
|= BAST_CPLD_CTRL2_WNAND
;
303 pr_debug("bast_nand: ctrl2 now %02x\n", tmp
);
305 __raw_writeb(tmp
, BAST_VA_CTRL2
);
308 static struct s3c2410_platform_nand bast_nand_info
= {
312 .nr_sets
= ARRAY_SIZE(bast_nand_sets
),
313 .sets
= bast_nand_sets
,
314 .select_chip
= bast_nand_select
,
319 static struct resource bast_dm9k_resource
[] = {
321 .start
= S3C2410_CS5
+ BAST_PA_DM9000
,
322 .end
= S3C2410_CS5
+ BAST_PA_DM9000
+ 3,
323 .flags
= IORESOURCE_MEM
326 .start
= S3C2410_CS5
+ BAST_PA_DM9000
+ 0x40,
327 .end
= S3C2410_CS5
+ BAST_PA_DM9000
+ 0x40 + 0x3f,
328 .flags
= IORESOURCE_MEM
333 .flags
= IORESOURCE_IRQ
338 /* for the moment we limit ourselves to 16bit IO until some
339 * better IO routines can be written and tested
342 struct dm9000_plat_data bast_dm9k_platdata
= {
343 .flags
= DM9000_PLATF_16BITONLY
346 static struct platform_device bast_device_dm9k
= {
349 .num_resources
= ARRAY_SIZE(bast_dm9k_resource
),
350 .resource
= bast_dm9k_resource
,
352 .platform_data
= &bast_dm9k_platdata
,
358 #define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
359 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
360 #define SERIAL_CLK (1843200)
362 static struct plat_serial8250_port bast_sio_data
[] = {
364 .mapbase
= SERIAL_BASE
+ 0x2f8,
365 .irq
= IRQ_PCSERIAL1
,
366 .flags
= SERIAL_FLAGS
,
369 .uartclk
= SERIAL_CLK
,
372 .mapbase
= SERIAL_BASE
+ 0x3f8,
373 .irq
= IRQ_PCSERIAL2
,
374 .flags
= SERIAL_FLAGS
,
377 .uartclk
= SERIAL_CLK
,
382 static struct platform_device bast_sio
= {
383 .name
= "serial8250",
386 .platform_data
= &bast_sio_data
,
390 /* we have devices on the bus which cannot work much over the
391 * standard 100KHz i2c bus frequency
394 static struct s3c2410_platform_i2c bast_i2c_info
= {
397 .bus_freq
= 100*1000,
398 .max_freq
= 130*1000,
401 /* Standard BAST devices */
403 static struct platform_device
*bast_devices
[] __initdata
= {
416 static struct clk
*bast_clocks
[] = {
424 static struct s3c24xx_board bast_board __initdata
= {
425 .devices
= bast_devices
,
426 .devices_count
= ARRAY_SIZE(bast_devices
),
427 .clocks
= bast_clocks
,
428 .clocks_count
= ARRAY_SIZE(bast_clocks
)
431 void __init
bast_map_io(void)
433 /* initialise the clocks */
435 s3c24xx_dclk0
.parent
= NULL
;
436 s3c24xx_dclk0
.rate
= 12*1000*1000;
438 s3c24xx_dclk1
.parent
= NULL
;
439 s3c24xx_dclk1
.rate
= 24*1000*1000;
441 s3c24xx_clkout0
.parent
= &s3c24xx_dclk0
;
442 s3c24xx_clkout1
.parent
= &s3c24xx_dclk1
;
444 s3c24xx_uclk
.parent
= &s3c24xx_clkout1
;
446 s3c_device_nand
.dev
.platform_data
= &bast_nand_info
;
447 s3c_device_i2c
.dev
.platform_data
= &bast_i2c_info
;
449 s3c24xx_init_io(bast_iodesc
, ARRAY_SIZE(bast_iodesc
));
450 s3c24xx_init_clocks(0);
451 s3c24xx_init_uarts(bast_uartcfgs
, ARRAY_SIZE(bast_uartcfgs
));
452 s3c24xx_set_board(&bast_board
);
457 MACHINE_START(BAST
, "Simtec-BAST")
458 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
459 .phys_ram
= S3C2410_SDRAM_PA
,
460 .phys_io
= S3C2410_PA_UART
,
461 .io_pg_offst
= (((u32
)S3C24XX_VA_UART
) >> 18) & 0xfffc,
462 .boot_params
= S3C2410_SDRAM_PA
+ 0x100,
463 .map_io
= bast_map_io
,
464 .init_irq
= s3c24xx_init_irq
,
465 .timer
= &s3c24xx_timer
,