1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * http://www.simtec.co.uk/products/EB2410ITX/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * 14-Sep-2004 BJD USB power control
14 * 20-Aug-2004 BJD Added s3c2410_board struct
15 * 18-Aug-2004 BJD Added platform devices from default set
16 * 16-May-2003 BJD Created initial version
17 * 16-Aug-2003 BJD Fixed header files and copyright, added URL
18 * 05-Sep-2003 BJD Moved to v2.6 kernel
19 * 06-Jan-2003 BJD Updates for <arch/map.h>
20 * 18-Jan-2003 BJD Added serial port configuration
21 * 05-Oct-2004 BJD Power management code
22 * 04-Nov-2004 BJD Updated serial port clocks
23 * 04-Jan-2005 BJD New uart init call
24 * 10-Jan-2005 BJD Removed include of s3c2410.h
25 * 14-Jan-2005 BJD Add support for muitlple NAND devices
26 * 03-Mar-2005 BJD Ensured that bast-cpld.h is included
27 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
28 * 14-Mar-2006 BJD Updated for __iomem changes
29 * 22-Jun-2006 BJD Added DM9000 platform information
32 #include <linux/kernel.h>
33 #include <linux/types.h>
34 #include <linux/interrupt.h>
35 #include <linux/list.h>
36 #include <linux/timer.h>
37 #include <linux/init.h>
38 #include <linux/device.h>
39 #include <linux/dm9000.h>
41 #include <asm/mach/arch.h>
42 #include <asm/mach/map.h>
43 #include <asm/mach/irq.h>
45 #include <asm/arch/bast-map.h>
46 #include <asm/arch/bast-irq.h>
47 #include <asm/arch/bast-cpld.h>
49 #include <asm/hardware.h>
52 #include <asm/mach-types.h>
54 //#include <asm/debug-ll.h>
55 #include <asm/arch/regs-serial.h>
56 #include <asm/arch/regs-gpio.h>
57 #include <asm/arch/regs-mem.h>
58 #include <asm/arch/regs-lcd.h>
59 #include <asm/arch/nand.h>
61 #include <linux/mtd/mtd.h>
62 #include <linux/mtd/nand.h>
63 #include <linux/mtd/nand_ecc.h>
64 #include <linux/mtd/partitions.h>
69 #include "usb-simtec.h"
72 #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
74 /* macros for virtual address mods for the io space entries */
75 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
76 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
77 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
78 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
80 /* macros to modify the physical addresses for io space */
82 #define PA_CS2(item) ((item) + S3C2410_CS2)
83 #define PA_CS3(item) ((item) + S3C2410_CS3)
84 #define PA_CS4(item) ((item) + S3C2410_CS4)
85 #define PA_CS5(item) ((item) + S3C2410_CS5)
87 static struct map_desc bast_iodesc
[] __initdata
= {
90 { (u32
)S3C24XX_VA_ISA_BYTE
, PA_CS2(BAST_PA_ISAIO
), SZ_16M
, MT_DEVICE
},
91 { (u32
)S3C24XX_VA_ISA_WORD
, PA_CS3(BAST_PA_ISAIO
), SZ_16M
, MT_DEVICE
},
93 /* we could possibly compress the next set down into a set of smaller tables
94 * pagetables, but that would mean using an L2 section, and it still means
95 * we cannot actually feed the same register to an LDR due to 16K spacing
98 /* bast CPLD control registers, and external interrupt controls */
99 { (u32
)BAST_VA_CTRL1
, BAST_PA_CTRL1
, SZ_1M
, MT_DEVICE
},
100 { (u32
)BAST_VA_CTRL2
, BAST_PA_CTRL2
, SZ_1M
, MT_DEVICE
},
101 { (u32
)BAST_VA_CTRL3
, BAST_PA_CTRL3
, SZ_1M
, MT_DEVICE
},
102 { (u32
)BAST_VA_CTRL4
, BAST_PA_CTRL4
, SZ_1M
, MT_DEVICE
},
105 { (u32
)BAST_VA_PC104_IRQREQ
, BAST_PA_PC104_IRQREQ
, SZ_1M
, MT_DEVICE
},
106 { (u32
)BAST_VA_PC104_IRQRAW
, BAST_PA_PC104_IRQRAW
, SZ_1M
, MT_DEVICE
},
107 { (u32
)BAST_VA_PC104_IRQMASK
, BAST_PA_PC104_IRQMASK
, SZ_1M
, MT_DEVICE
},
109 /* peripheral space... one for each of fast/slow/byte/16bit */
110 /* note, ide is only decoded in word space, even though some registers
114 { VA_C2(BAST_VA_ISAIO
), PA_CS2(BAST_PA_ISAIO
), SZ_16M
, MT_DEVICE
},
115 { VA_C2(BAST_VA_ISAMEM
), PA_CS2(BAST_PA_ISAMEM
), SZ_16M
, MT_DEVICE
},
116 { VA_C2(BAST_VA_ASIXNET
), PA_CS3(BAST_PA_ASIXNET
), SZ_1M
, MT_DEVICE
},
117 { VA_C2(BAST_VA_SUPERIO
), PA_CS2(BAST_PA_SUPERIO
), SZ_1M
, MT_DEVICE
},
118 { VA_C2(BAST_VA_IDEPRI
), PA_CS3(BAST_PA_IDEPRI
), SZ_1M
, MT_DEVICE
},
119 { VA_C2(BAST_VA_IDESEC
), PA_CS3(BAST_PA_IDESEC
), SZ_1M
, MT_DEVICE
},
120 { VA_C2(BAST_VA_IDEPRIAUX
), PA_CS3(BAST_PA_IDEPRIAUX
), SZ_1M
, MT_DEVICE
},
121 { VA_C2(BAST_VA_IDESECAUX
), PA_CS3(BAST_PA_IDESECAUX
), SZ_1M
, MT_DEVICE
},
124 { VA_C3(BAST_VA_ISAIO
), PA_CS3(BAST_PA_ISAIO
), SZ_16M
, MT_DEVICE
},
125 { VA_C3(BAST_VA_ISAMEM
), PA_CS3(BAST_PA_ISAMEM
), SZ_16M
, MT_DEVICE
},
126 { VA_C3(BAST_VA_ASIXNET
), PA_CS3(BAST_PA_ASIXNET
), SZ_1M
, MT_DEVICE
},
127 { VA_C3(BAST_VA_SUPERIO
), PA_CS3(BAST_PA_SUPERIO
), SZ_1M
, MT_DEVICE
},
128 { VA_C3(BAST_VA_IDEPRI
), PA_CS3(BAST_PA_IDEPRI
), SZ_1M
, MT_DEVICE
},
129 { VA_C3(BAST_VA_IDESEC
), PA_CS3(BAST_PA_IDESEC
), SZ_1M
, MT_DEVICE
},
130 { VA_C3(BAST_VA_IDEPRIAUX
), PA_CS3(BAST_PA_IDEPRIAUX
), SZ_1M
, MT_DEVICE
},
131 { VA_C3(BAST_VA_IDESECAUX
), PA_CS3(BAST_PA_IDESECAUX
), SZ_1M
, MT_DEVICE
},
134 { VA_C4(BAST_VA_ISAIO
), PA_CS4(BAST_PA_ISAIO
), SZ_16M
, MT_DEVICE
},
135 { VA_C4(BAST_VA_ISAMEM
), PA_CS4(BAST_PA_ISAMEM
), SZ_16M
, MT_DEVICE
},
136 { VA_C4(BAST_VA_ASIXNET
), PA_CS5(BAST_PA_ASIXNET
), SZ_1M
, MT_DEVICE
},
137 { VA_C4(BAST_VA_SUPERIO
), PA_CS4(BAST_PA_SUPERIO
), SZ_1M
, MT_DEVICE
},
138 { VA_C4(BAST_VA_IDEPRI
), PA_CS5(BAST_PA_IDEPRI
), SZ_1M
, MT_DEVICE
},
139 { VA_C4(BAST_VA_IDESEC
), PA_CS5(BAST_PA_IDESEC
), SZ_1M
, MT_DEVICE
},
140 { VA_C4(BAST_VA_IDEPRIAUX
), PA_CS5(BAST_PA_IDEPRIAUX
), SZ_1M
, MT_DEVICE
},
141 { VA_C4(BAST_VA_IDESECAUX
), PA_CS5(BAST_PA_IDESECAUX
), SZ_1M
, MT_DEVICE
},
144 { VA_C5(BAST_VA_ISAIO
), PA_CS5(BAST_PA_ISAIO
), SZ_16M
, MT_DEVICE
},
145 { VA_C5(BAST_VA_ISAMEM
), PA_CS5(BAST_PA_ISAMEM
), SZ_16M
, MT_DEVICE
},
146 { VA_C5(BAST_VA_ASIXNET
), PA_CS5(BAST_PA_ASIXNET
), SZ_1M
, MT_DEVICE
},
147 { VA_C5(BAST_VA_SUPERIO
), PA_CS5(BAST_PA_SUPERIO
), SZ_1M
, MT_DEVICE
},
148 { VA_C5(BAST_VA_IDEPRI
), PA_CS5(BAST_PA_IDEPRI
), SZ_1M
, MT_DEVICE
},
149 { VA_C5(BAST_VA_IDESEC
), PA_CS5(BAST_PA_IDESEC
), SZ_1M
, MT_DEVICE
},
150 { VA_C5(BAST_VA_IDEPRIAUX
), PA_CS5(BAST_PA_IDEPRIAUX
), SZ_1M
, MT_DEVICE
},
151 { VA_C5(BAST_VA_IDESECAUX
), PA_CS5(BAST_PA_IDESECAUX
), SZ_1M
, MT_DEVICE
},
154 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
155 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
156 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
158 static struct s3c24xx_uart_clksrc bast_serial_clocks
[] = {
174 static struct s3c2410_uartcfg bast_uartcfgs
[] = {
181 .clocks
= bast_serial_clocks
,
182 .clocks_size
= ARRAY_SIZE(bast_serial_clocks
)
190 .clocks
= bast_serial_clocks
,
191 .clocks_size
= ARRAY_SIZE(bast_serial_clocks
)
193 /* port 2 is not actually used */
200 .clocks
= bast_serial_clocks
,
201 .clocks_size
= ARRAY_SIZE(bast_serial_clocks
)
205 /* NOR Flash on BAST board */
207 static struct resource bast_nor_resource
[] = {
209 .start
= S3C2410_CS1
+ 0x4000000,
210 .end
= S3C2410_CS1
+ 0x4000000 + (32*1024*1024) - 1,
211 .flags
= IORESOURCE_MEM
,
215 static struct platform_device bast_device_nor
= {
218 .num_resources
= ARRAY_SIZE(bast_nor_resource
),
219 .resource
= bast_nor_resource
,
222 /* NAND Flash on BAST board */
225 static int smartmedia_map
[] = { 0 };
226 static int chip0_map
[] = { 1 };
227 static int chip1_map
[] = { 2 };
228 static int chip2_map
[] = { 3 };
230 struct mtd_partition bast_default_nand_part
[] = {
232 .name
= "Boot Agent",
238 .size
= SZ_4M
- SZ_16K
,
244 .size
= MTDPART_SIZ_FULL
,
248 /* the bast has 4 selectable slots for nand-flash, the three
249 * on-board chip areas, as well as the external SmartMedia
252 * Note, there is no current hot-plug support for the SmartMedia
256 static struct s3c2410_nand_set bast_nand_sets
[] = {
258 .name
= "SmartMedia",
260 .nr_map
= smartmedia_map
,
261 .nr_partitions
= ARRAY_SIZE(bast_default_nand_part
),
262 .partitions
= bast_default_nand_part
268 .nr_partitions
= ARRAY_SIZE(bast_default_nand_part
),
269 .partitions
= bast_default_nand_part
275 .nr_partitions
= ARRAY_SIZE(bast_default_nand_part
),
276 .partitions
= bast_default_nand_part
282 .nr_partitions
= ARRAY_SIZE(bast_default_nand_part
),
283 .partitions
= bast_default_nand_part
287 static void bast_nand_select(struct s3c2410_nand_set
*set
, int slot
)
291 slot
= set
->nr_map
[slot
] & 3;
293 pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
294 slot
, set
, set
->nr_map
);
296 tmp
= __raw_readb(BAST_VA_CTRL2
);
297 tmp
&= BAST_CPLD_CTLR2_IDERST
;
299 tmp
|= BAST_CPLD_CTRL2_WNAND
;
301 pr_debug("bast_nand: ctrl2 now %02x\n", tmp
);
303 __raw_writeb(tmp
, BAST_VA_CTRL2
);
306 static struct s3c2410_platform_nand bast_nand_info
= {
310 .nr_sets
= ARRAY_SIZE(bast_nand_sets
),
311 .sets
= bast_nand_sets
,
312 .select_chip
= bast_nand_select
,
317 static struct resource bast_dm9k_resource
[] = {
319 .start
= S3C2410_CS5
+ BAST_PA_DM9000
,
320 .end
= S3C2410_CS5
+ BAST_PA_DM9000
+ 3,
321 .flags
= IORESOURCE_MEM
324 .start
= S3C2410_CS5
+ BAST_PA_DM9000
+ 0x40,
325 .end
= S3C2410_CS5
+ BAST_PA_DM9000
+ 0x40 + 0x3f,
326 .flags
= IORESOURCE_MEM
331 .flags
= IORESOURCE_IRQ
336 /* for the moment we limit ourselves to 16bit IO until some
337 * better IO routines can be written and tested
340 struct dm9000_plat_data bast_dm9k_platdata
= {
341 .flags
= DM9000_PLATF_16BITONLY
344 static struct platform_device bast_device_dm9k
= {
347 .num_resources
= ARRAY_SIZE(bast_dm9k_resource
),
348 .resource
= bast_dm9k_resource
,
350 .platform_data
= &bast_dm9k_platdata
,
355 /* Standard BAST devices */
357 static struct platform_device
*bast_devices
[] __initdata
= {
369 static struct clk
*bast_clocks
[] = {
377 static struct s3c24xx_board bast_board __initdata
= {
378 .devices
= bast_devices
,
379 .devices_count
= ARRAY_SIZE(bast_devices
),
380 .clocks
= bast_clocks
,
381 .clocks_count
= ARRAY_SIZE(bast_clocks
)
384 void __init
bast_map_io(void)
386 /* initialise the clocks */
388 s3c24xx_dclk0
.parent
= NULL
;
389 s3c24xx_dclk0
.rate
= 12*1000*1000;
391 s3c24xx_dclk1
.parent
= NULL
;
392 s3c24xx_dclk1
.rate
= 24*1000*1000;
394 s3c24xx_clkout0
.parent
= &s3c24xx_dclk0
;
395 s3c24xx_clkout1
.parent
= &s3c24xx_dclk1
;
397 s3c24xx_uclk
.parent
= &s3c24xx_clkout1
;
399 s3c_device_nand
.dev
.platform_data
= &bast_nand_info
;
401 s3c24xx_init_io(bast_iodesc
, ARRAY_SIZE(bast_iodesc
));
402 s3c24xx_init_clocks(0);
403 s3c24xx_init_uarts(bast_uartcfgs
, ARRAY_SIZE(bast_uartcfgs
));
404 s3c24xx_set_board(&bast_board
);
408 void __init
bast_init_irq(void)
417 * enable the power management functions for the EB2410ITX
420 static __init
void bast_init_machine(void)
422 unsigned long gstatus4
;
424 printk(KERN_INFO
"BAST Power Manangement" COPYRIGHT
"\n");
426 gstatus4
= (__raw_readl(S3C2410_BANKCON7
) & 0x3) << 30;
427 gstatus4
|= (__raw_readl(S3C2410_BANKCON6
) & 0x3) << 28;
428 gstatus4
|= (__raw_readl(S3C2410_BANKSIZE
) & S3C2410_BANKSIZE_MASK
);
430 __raw_writel(gstatus4
, S3C2410_GSTATUS4
);
436 #define bast_init_machine NULL
440 MACHINE_START(BAST
, "Simtec-BAST")
441 MAINTAINER("Ben Dooks <ben@simtec.co.uk>")
442 BOOT_MEM(S3C2410_SDRAM_PA
, S3C2410_PA_UART
, (u32
)S3C24XX_VA_UART
)
443 BOOT_PARAMS(S3C2410_SDRAM_PA
+ 0x100)
445 INITIRQ(bast_init_irq
)
446 .init_machine
= bast_init_machine
,
447 .timer
= &s3c24xx_timer
,