arch/arm/mach-s3c2410/mach-qt2410.c

   1 /* linux/arch/arm/mach-s3c2410/mach-qt2410.c
   2  *
   3  * Copyright (C) 2006 by OpenMoko, Inc.
   4  * Author: Harald Welte <laforge@openmoko.org>
   5  * All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/types.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/list.h>
  28 #include <linux/timer.h>
  29 #include <linux/init.h>
  30 #include <linux/sysdev.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/serial_core.h>
  33 #include <linux/spi/spi.h>
  34 #include <linux/spi/spi_bitbang.h>
  35
  36 #include <linux/mtd/mtd.h>
  37 #include <linux/mtd/nand.h>
  38 #include <linux/mtd/nand_ecc.h>
  39 #include <linux/mtd/partitions.h>
  40
  41 #include <asm/mach/arch.h>
  42 #include <asm/mach/map.h>
  43 #include <asm/mach/irq.h>
  44
  45 #include <asm/hardware.h>
  46 #include <asm/io.h>
  47 #include <asm/irq.h>
  48 #include <asm/mach-types.h>
  49
  50 #include <asm/arch/regs-gpio.h>
  51 #include <asm/arch/leds-gpio.h>
  52 #include <asm/plat-s3c/regs-serial.h>
  53 #include <asm/arch/fb.h>
  54 #include <asm/plat-s3c/nand.h>
  55 #include <asm/plat-s3c24xx/udc.h>
  56 #include <asm/arch/spi.h>
  57 #include <asm/arch/spi-gpio.h>
  58
  59 #include <asm/plat-s3c24xx/common-smdk.h>
  60 #include <asm/plat-s3c24xx/devs.h>
  61 #include <asm/plat-s3c24xx/cpu.h>
  62 #include <asm/plat-s3c24xx/pm.h>
  63
  64 static struct map_desc qt2410_iodesc[] __initdata = {
  65         { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
  66 };
  67
  68 #define UCON S3C2410_UCON_DEFAULT
  69 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  70 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  71
  72 static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
  73         [0] = {
  74                 .hwport      = 0,
  75                 .flags       = 0,
  76                 .ucon        = UCON,
  77                 .ulcon       = ULCON,
  78                 .ufcon       = UFCON,
  79         },
  80         [1] = {
  81                 .hwport      = 1,
  82                 .flags       = 0,
  83                 .ucon        = UCON,
  84                 .ulcon       = ULCON,
  85                 .ufcon       = UFCON,
  86         },
  87         [2] = {
  88                 .hwport      = 2,
  89                 .flags       = 0,
  90                 .ucon        = UCON,
  91                 .ulcon       = ULCON,
  92                 .ufcon       = UFCON,
  93         }
  94 };
  95
  96 /* LCD driver info */
  97
  98 static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
  99         {
 100                 /* Configuration for 640x480 SHARP LQ080V3DG01 */
 101                 .regs   = {
 102
 103                         .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
 104                                    S3C2410_LCDCON1_TFT |
 105                                    S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
 106
 107                         .lcdcon2 = S3C2410_LCDCON2_VBPD(18) |   /* 19 */
 108                                    S3C2410_LCDCON2_LINEVAL(479) |
 109                                    S3C2410_LCDCON2_VFPD(10) |   /* 11 */
 110                                    S3C2410_LCDCON2_VSPW(14),    /* 15 */
 111
 112                         .lcdcon3 = S3C2410_LCDCON3_HBPD(43) |   /* 44 */
 113                                    S3C2410_LCDCON3_HOZVAL(639) | /* 640 */
 114                                    S3C2410_LCDCON3_HFPD(115),   /* 116 */
 115
 116                         .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
 117                                    S3C2410_LCDCON4_HSPW(95),    /* 96 */
 118
 119                         .lcdcon5 = S3C2410_LCDCON5_FRM565 |
 120                                    S3C2410_LCDCON5_INVVLINE |
 121                                    S3C2410_LCDCON5_INVVFRAME |
 122                                    S3C2410_LCDCON5_PWREN |
 123                                    S3C2410_LCDCON5_HWSWP,
 124                 },
 125
 126                 .type           = S3C2410_LCDCON1_TFT,
 127                 .width          = 640,
 128                 .height         = 480,
 129
 130                 .xres           = 640,
 131                 .yres           = 480,
 132                 .bpp            = 16,
 133                 .left_margin    = 44,
 134                 .right_margin   = 116,
 135         },
 136         {
 137                 /* Configuration for 480x640 toppoly TD028TTEC1 */
 138                 .regs   = {
 139
 140                         .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
 141                                    S3C2410_LCDCON1_TFT |
 142                                    S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
 143
 144                         .lcdcon2 = S3C2410_LCDCON2_VBPD(1) |    /* 2 */
 145                                    S3C2410_LCDCON2_LINEVAL(639) |/* 640 */
 146                                    S3C2410_LCDCON2_VFPD(3) |    /* 4 */
 147                                    S3C2410_LCDCON2_VSPW(1),     /* 2 */
 148
 149                         .lcdcon3 = S3C2410_LCDCON3_HBPD(7) |    /* 8 */
 150                                    S3C2410_LCDCON3_HOZVAL(479) | /* 479 */
 151                                    S3C2410_LCDCON3_HFPD(23),    /* 24 */
 152
 153                         .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
 154                                    S3C2410_LCDCON4_HSPW(7),     /* 8 */
 155
 156                         .lcdcon5 = S3C2410_LCDCON5_FRM565 |
 157                                    S3C2410_LCDCON5_INVVLINE |
 158                                    S3C2410_LCDCON5_INVVFRAME |
 159                                    S3C2410_LCDCON5_PWREN |
 160                                    S3C2410_LCDCON5_HWSWP,
 161                 },
 162
 163                 .type           = S3C2410_LCDCON1_TFT,
 164                 .width          = 480,
 165                 .height         = 640,
 166                 .xres           = 480,
 167                 .yres           = 640,
 168                 .bpp            = 16,
 169                 .left_margin    = 8,
 170                 .right_margin   = 24,
 171         },
 172         {
 173                 /* Config for 240x320 LCD */
 174                 .regs   = {
 175
 176                         .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
 177                                    S3C2410_LCDCON1_TFT |
 178                                    S3C2410_LCDCON1_CLKVAL(0x04),
 179
 180                         .lcdcon2 = S3C2410_LCDCON2_VBPD(1) |
 181                                    S3C2410_LCDCON2_LINEVAL(319) |
 182                                    S3C2410_LCDCON2_VFPD(6) |
 183                                    S3C2410_LCDCON2_VSPW(3),
 184
 185                         .lcdcon3 = S3C2410_LCDCON3_HBPD(12) |
 186                                    S3C2410_LCDCON3_HOZVAL(239) |
 187                                    S3C2410_LCDCON3_HFPD(7),
 188
 189                         .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
 190                                    S3C2410_LCDCON4_HSPW(3),
 191
 192                         .lcdcon5 = S3C2410_LCDCON5_FRM565 |
 193                                    S3C2410_LCDCON5_INVVLINE |
 194                                    S3C2410_LCDCON5_INVVFRAME |
 195                                    S3C2410_LCDCON5_PWREN |
 196                                    S3C2410_LCDCON5_HWSWP,
 197                 },
 198
 199                 .type           = S3C2410_LCDCON1_TFT,
 200                 .width          = 240,
 201                 .height         = 320,
 202                 .xres           = 240,
 203                 .yres           = 320,
 204                 .bpp            = 16,
 205                 .left_margin    = 13,
 206                 .right_margin   = 8,
 207         },
 208 };
 209
 210
 211 static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
 212         .displays       = qt2410_lcd_cfg,
 213         .num_displays   = ARRAY_SIZE(qt2410_lcd_cfg),
 214         .default_display = 0,
 215
 216         .lpcsel         = ((0xCE6) & ~7) | 1<<4,
 217 };
 218
 219 /* CS8900 */
 220
 221 static struct resource qt2410_cs89x0_resources[] = {
 222         [0] = {
 223                 .start  = 0x19000000,
 224                 .end    = 0x19000000 + 16,
 225                 .flags  = IORESOURCE_MEM,
 226         },
 227         [1] = {
 228                 .start  = IRQ_EINT9,
 229                 .end    = IRQ_EINT9,
 230                 .flags  = IORESOURCE_IRQ,
 231         },
 232 };
 233
 234 static struct platform_device qt2410_cs89x0 = {
 235         .name           = "cirrus-cs89x0",
 236         .num_resources  = ARRAY_SIZE(qt2410_cs89x0_resources),
 237         .resource       = qt2410_cs89x0_resources,
 238 };
 239
 240 /* LED */
 241
 242 static struct s3c24xx_led_platdata qt2410_pdata_led = {
 243         .gpio           = S3C2410_GPB0,
 244         .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
 245         .name           = "led",
 246         .def_trigger    = "timer",
 247 };
 248
 249 static struct platform_device qt2410_led = {
 250         .name           = "s3c24xx_led",
 251         .id             = 0,
 252         .dev            = {
 253                 .platform_data = &qt2410_pdata_led,
 254         },
 255 };
 256
 257 /* SPI */
 258
 259 static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
 260 {
 261         switch (cs) {
 262         case BITBANG_CS_ACTIVE:
 263                 s3c2410_gpio_setpin(S3C2410_GPB5, 0);
 264                 break;
 265         case BITBANG_CS_INACTIVE:
 266                 s3c2410_gpio_setpin(S3C2410_GPB5, 1);
 267                 break;
 268         }
 269 }
 270
 271 static struct s3c2410_spigpio_info spi_gpio_cfg = {
 272         .pin_clk        = S3C2410_GPG7,
 273         .pin_mosi       = S3C2410_GPG6,
 274         .pin_miso       = S3C2410_GPG5,
 275         .chip_select    = &spi_gpio_cs,
 276 };
 277
 278
 279 static struct platform_device qt2410_spi = {
 280         .name             = "s3c24xx-spi-gpio",
 281         .id               = 1,
 282         .dev = {
 283                 .platform_data = &spi_gpio_cfg,
 284         },
 285 };
 286
 287 /* Board devices */
 288
 289 static struct platform_device *qt2410_devices[] __initdata = {
 290         &s3c_device_usb,
 291         &s3c_device_lcd,
 292         &s3c_device_wdt,
 293         &s3c_device_i2c,
 294         &s3c_device_iis,
 295         &s3c_device_sdi,
 296         &s3c_device_usbgadget,
 297         &qt2410_spi,
 298         &qt2410_cs89x0,
 299         &qt2410_led,
 300 };
 301
 302 static struct mtd_partition qt2410_nand_part[] = {
 303         [0] = {
 304                 .name   = "U-Boot",
 305                 .size   = 0x30000,
 306                 .offset = 0,
 307         },
 308         [1] = {
 309                 .name   = "U-Boot environment",
 310                 .offset = 0x30000,
 311                 .size   = 0x4000,
 312         },
 313         [2] = {
 314                 .name   = "kernel",
 315                 .offset = 0x34000,
 316                 .size   = SZ_2M,
 317         },
 318         [3] = {
 319                 .name   = "initrd",
 320                 .offset = 0x234000,
 321                 .size   = SZ_4M,
 322         },
 323         [4] = {
 324                 .name   = "jffs2",
 325                 .offset = 0x634000,
 326                 .size   = 0x39cc000,
 327         },
 328 };
 329
 330 static struct s3c2410_nand_set qt2410_nand_sets[] = {
 331         [0] = {
 332                 .name           = "NAND",
 333                 .nr_chips       = 1,
 334                 .nr_partitions  = ARRAY_SIZE(qt2410_nand_part),
 335                 .partitions     = qt2410_nand_part,
 336         },
 337 };
 338
 339 /* choose a set of timings which should suit most 512Mbit
 340  * chips and beyond.
 341  */
 342
 343 static struct s3c2410_platform_nand qt2410_nand_info = {
 344         .tacls          = 20,
 345         .twrph0         = 60,
 346         .twrph1         = 20,
 347         .nr_sets        = ARRAY_SIZE(qt2410_nand_sets),
 348         .sets           = qt2410_nand_sets,
 349 };
 350
 351 /* UDC */
 352
 353 static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
 354 };
 355
 356 static char tft_type = 's';
 357
 358 static int __init qt2410_tft_setup(char *str)
 359 {
 360         tft_type = str[0];
 361         return 1;
 362 }
 363
 364 __setup("tft=", qt2410_tft_setup);
 365
 366 static void __init qt2410_map_io(void)
 367 {
 368         s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
 369         s3c24xx_init_clocks(12*1000*1000);
 370         s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
 371 }
 372
 373 static void __init qt2410_machine_init(void)
 374 {
 375         s3c_device_nand.dev.platform_data = &qt2410_nand_info;
 376
 377         switch (tft_type) {
 378         case 'p': /* production */
 379                 qt2410_fb_info.default_display = 1;
 380                 break;
 381         case 'b': /* big */
 382                 qt2410_fb_info.default_display = 0;
 383                 break;
 384         case 's': /* small */
 385         default:
 386                 qt2410_fb_info.default_display = 2;
 387                 break;
 388         }
 389         s3c24xx_fb_set_platdata(&qt2410_fb_info);
 390
 391         s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT);
 392         s3c2410_gpio_setpin(S3C2410_GPB0, 1);
 393
 394         s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
 395
 396         s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
 397
 398         platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
 399         s3c2410_pm_init();
 400 }
 401
 402 MACHINE_START(QT2410, "QT2410")
 403         .phys_io        = S3C2410_PA_UART,
 404         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
 405         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 406         .map_io         = qt2410_map_io,
 407         .init_irq       = s3c24xx_init_irq,
 408         .init_machine   = qt2410_machine_init,
 409         .timer          = &s3c24xx_timer,
 410 MACHINE_END
 411
 412